Softmax instruction set extension method and system based on RISC-V

Abstract

The invention belongs to the field of neural network hardware acceleration, and provides a Softmax instruction set extension method and system based on RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method based on the RISC-V. The Softmax instruction set extension method comprises an instruction fetching stage, in the decoding stage, corresponding instruction functions are analyzed for Opcode, Funct7 and Funct3 of the Softmax instruction, and corresponding control signals are generated. In the execution stage, data to be subjected to Softmax operation is taken out from the data memory and transmitted into the Softmax calculation unit according to a control signal; executing Softmax calculation according to the following formula, and writing a Softmax calculation result back to the target register; the calculation process is divided into four sub-modules of maximum solution, index calculation, summation and normalization, and a hardware acceleration strategy is designed, so that the operation delay and the resource overhead are greatly reduced, the degree of parallelism, the precision and the energy efficiency ratio of calculation are effectively improved, and the method is suitable for a high-performance neural network reasoning acceleration scene.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of neural network hardware acceleration, and particularly relates to a Softmax instruction set extension method and system based on RISC-V. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute prior art.

[0003] With the wide application of deep learning in natural language processing, speech recognition, image understanding and other fields, the Transformer structure gradually replaces the traditional recurrent neural network (RNN) and convolutional neural network (CNN) due to its strong modeling ability and parallel computing characteristics, and becomes the mainstream neural network architecture. In particular, in BERT, GPT and other models, the attention mechanism in the Transformer widely relies on the Softmax function to realize the normalization calculation of the attention weight, and then determines the information aggregation mode of the model. Therefore, as a core component in the Transformer structure, the performance of the Softmax calculation directly affects the inference speed and calculation delay of the entire neural network, and becomes one of the key bottlenecks in the design of high-performance neural network processors.

[0004] The Softmax function calculation includes complex numerical operations such as maximum value extraction, exponential operation and normalization division, and usually requires multiple multiplier and divider resources, occupying a large hardware area and consuming multiple clock cycles, which is difficult to meet the real-time inference requirements of low power consumption and low delay. Although there are optimization strategies based on lookup table, piecewise approximation or rotating coordinate system to improve the efficiency of the exponential and division units, these methods generally lack comprehensive balance and regulation of calculation accuracy, energy consumption and area, and have calculation redundancy and data transfer bottlenecks in large-scale input scenarios. SUMMARY

[0005] In order to solve the above problems, the present application provides a Softmax instruction set extension method and system based on RISC-V. The present application combines the RISC-V open instruction set architecture, extends the Softmax special instruction, and deploys it in the embedded neural network processing unit (NPU) with a lightweight pipeline structure, which can realize high energy efficiency and reconfigurable Softmax acceleration processing capability, has good engineering adaptability and product integration value, and is especially suitable for resource-constrained edge AI application scenarios.

[0006] According to some embodiments, the first aspect of the present application provides a Softmax instruction set extension method based on RISC-V, which adopts the following technical scheme: Based on the RISC-V Softmax instruction set extension method, the RISC-V processor adopts an N-stage pipeline structure, including: In the instruction fetch stage, the instruction fetch unit in the RISC-V processor fetches the Softmax instruction from the Softmax instruction memory according to the address generated by the instruction counter PC; In the decoding stage, the decoding unit analyzes the Opcode, funct7 and funct3 of the Softmax instruction to determine the corresponding instruction functions and generates corresponding control signals. In the execution phase, the execution unit takes the data to be Softmax calculated from the data memory and passes it to the Softmax calculation unit according to the control signal; the Softmax calculation is performed according to the following formula, and the Softmax calculation result is written back to the target register; ; in, Is the current The data to be calculated, , is the maximum value.

[0007] Furthermore, the Softmax calculation unit includes five processes: maximum value search, exponential solution, summation, logarithmic solution and multiplexed exponential calculation; When the RISC-V processor detects the Softmax instruction, the data memory sends the data to be Softmax-operated to the Softmax calculation unit for Softmax operation.

[0008] Furthermore, the data memory sends the data to be subjected to the Softmax operation to the Softmax calculation unit for performing the Softmax operation, specifically: The data to be processed by Softmax operation is first passed to the maximum value search unit for data comparison to obtain the maximum value, and the maximum value is returned to the Softmax calculation unit; The data to be processed by Softmax calculation is subtracted from the maximum value and then scaled by the temperature coefficient, and then passed to the exponential calculation unit for exponential calculation, and the exponential calculation result is returned to the Softmax calculation unit; The Softmax calculation unit passes the exponential calculation result to the summation unit, the summation unit sums the exponential calculation results and returns the summation result to the Softmax calculation unit; The Softmax calculation unit passes the summation result to the logarithm solution unit, and the logarithm solution unit performs a natural logarithm operation on the summation result and returns the logarithm solution result to the Softmax calculation unit; The Softmax calculation unit passes the logarithmic solution result to the exponential calculation unit, reuses the exponential calculation unit, subtracts the maximum value from the data to be Softmax calculated, subtracts the logarithmic solution result, and performs exponential calculation again to obtain the final Softmax calculation result and return it to the Softmax calculation unit.

[0009] Furthermore, the Softmax calculation unit is divided into nine steps, namely the initial IDLE stage, the DATA_CHECK data checking stage, the SPILT data segmentation stage, the FIND_MAX maximum value finding stage, the CLAC_EXP index calculation stage, the CLAC_SUM summation stage, the LN_UNIT logarithm calculation stage, the second CLAC_EXP index calculation stage and the final PACK result packaging stage; In the IDLE stage, whether to enter the next stage is controlled according to the start calculation signal and pipeline busy signal transmitted from the execution stage; In the DATA_CHECK phase, data is checked and the total amount of data for Softmax calculation is determined based on the funct7 passed in during the execution phase. In the SPILT stage, the data to be processed by the Softmax operation is segmented and placed into the target register according to the number of data and bit width information indicated in the instruction. In the FIND_MAX stage, the segmented data is passed to the maximum value search unit, and the maximum value result is obtained through parallel comparison and returned to the Softmax calculation unit; In the CLAC_EXP stage, the temperature coefficient is determined according to the funct3 passed in the execution stage. The data after subtracting the maximum value from the segmented data is scaled by the temperature coefficient. The data is then input into the exponential calculation unit for exponential operation, and the exponential calculation result is returned to the Softmax calculation unit. In the CLAC_SUM stage, the Softmax calculation unit passes the data after exponential calculation to the summation unit for summation, and returns the summation result to the Softmax calculation unit; In the LN_UNIT stage, the Softmax calculation unit passes the summation result and the data after subtracting the maximum value from each original data to the logarithm calculation unit in sequence, calculates the logarithm result and returns it to the Softmax calculation unit; In the second CLAC_EXP stage, the data to be Softmax calculated is subtracted from the maximum value and then from the logarithmic calculation result, and the calculation results are sequentially passed to the exponential calculation unit for the second exponential operation, and the final Softmax calculation results are sequentially passed to the Softmax calculation unit; In the PACK stage, the final Softmax operation result is packaged and judged whether it needs to be written into the second register based on the bit width of the data to be Softmax operated and the number of inputs; If the second register is needed, the write enable of the second register is set to a high level, and the above calculation result and the write enable are passed to the execution stage.

[0010] Furthermore, the execution stage receives the calculation result transmitted back by the Softmax calculation unit as an enable signal, detects whether the calculation is completed, and writes the calculation result and address information back to the target register if the calculation is completed.

[0011] Furthermore, the R-type instruction of RISC-V is adopted as the Softmax instruction format, wherein the Softmax instruction includes: rs1, rs2, rd, funct7, funct3 and opcode; The address width of rs1, rs2 and rd registers is 5 bits, the width of funct7 is 7 bits, the width of funct3 is 3 bits, and the width of opcode is 7 bits; rs1 records the register address of source operand 1, and rs2 records the register address of source operand 2; Funct7 is divided into two parts, where [2:0] is used to refer to the data bit width in the rs1 and rs2 addresses, and [6:3] refers to how much data in the rs1 and rs2 registers needs to be calculated for Softmax; funct3 represents the classification of Softmax, representing different temperature coefficients; Opcode represents the Softmax operation instruction.

[0012] Furthermore, the Opcode encoding of the Softmax instruction is defined as 1111011; The funct3 field includes: 000 for normal Softmax, 001 for Softmax with a temperature coefficient of 2, 010 for Softmax with a temperature coefficient of 4, and 011 for Softmax with a temperature coefficient of 8; Funct7 is divided into two parts. The [2:0] part is divided into 001 and 010, indicating that the bit width is 8 and 16 respectively. The [6:3] part 0010 to 1000 indicates that 2 to 8 data are involved in the calculation respectively. rs1 and rs1 represent the data to be normalized, and rd represents the normalized data.

[0013] According to some embodiments, a second solution of the present invention provides a RISC-V-based Softmax instruction set extension system, which adopts the following technical solutions: The RISC-V-based Softmax instruction set extension system comprises a RISC-V processor and a hardware acceleration device for Softmax instruction set extension integrated in the RISC-V processor; wherein the hardware acceleration device comprises a Softmax instruction memory, a decoding unit, a data memory, a Softmax calculation unit, a Softmax instruction memory and a target register. The Softmax calculation unit interacts with a maximum value finding unit, an exponential solving unit, a summation unit and a logarithm solving unit. When the Softmax instruction is executed, a fetch unit in the RISC-V processor first fetches data to be subjected to Softmax operation from the data memory through the loading data storage unit, and sends the data into the Softmax calculation unit to perform efficient calculation of the Softmax formula, and writes the result back to the target register.

[0014] According to some embodiments, the third aspect of the present application provides a computer readable storage medium.

[0015] A computer readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the steps in the RISC-V-based Softmax instruction set extension method according to the first aspect.

[0016] According to some embodiments, the fourth aspect of the present application provides a computer device.

[0017] A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the steps in the RISC-V-based Softmax instruction set extension method according to the first aspect.

[0018] Compared with the prior art, the present application has the following beneficial effects: The present application introduces a special Softmax extension instruction in the RISC-V processor, and designs an N-stage pipeline structure, thereby realizing deep integration of the Softmax calculation module and the RISC-V architecture, and taking into account programmability, flexibility and high energy-efficient computing performance.

[0019] The present application aims at the problems of complex calculation and large amount of calculation of the Softmax function in the Transformer neural network, and proposes an efficient Softmax calculation module acceleration scheme. By dividing the calculation process into four sub-modules of maximum value solving, exponential calculation, summation and normalization, and respectively designing tree-shaped parallel comparison structure, Taylor series approximation, addition and subtraction shift instead of division and other hardware acceleration strategies, the operation delay and resource overhead are greatly reduced, and the parallel degree, accuracy and energy efficiency ratio of the Softmax calculation are effectively improved, which is suitable for high-performance neural network inference acceleration scene.

[0020] The present application constructs a Softmax calculation processor array based on the RISC-V instruction set, adopts an N-stage pipeline structure for instruction fetching, decoding and execution operation, has good instruction expandability and structural flexibility. The processor can receive control instructions in parallel to complete data scheduling and calculation, supports multi-task concurrent execution, improves the overall throughput and configurability of the system. At the same time, the module uses Verilog to realize RTL level modeling, has the advantages of clear structure, low power consumption, easy integration, etc., has good engineering practical value and popularization prospect. BRIEF DESCRIPTION OF DRAWINGS

[0021] The drawings accompanying the specification of the present application form part of the present application and serve to further understand the present application, and the illustrative embodiments of the present application and the description thereof serve to explain the present application, and do not constitute an improper limitation on the present application.

[0022] Figure 1 is a hardware system architecture diagram of the Softmax instruction expansion based on the RISC-V three-stage pipeline in the embodiment of the present application; Figure 2 is a flowchart of the Softmax instruction calculation based on the three-stage pipeline in the embodiment of the present application; Figure 3 is a tree-shaped parallel calculation flowchart of the MAX maximum value finding module in the embodiment of the present application; Figure 4 is a calculation flowchart of the decimal part and the integer part in the exponential calculation process in the embodiment of the present application; Figure 5 is a tree-shaped parallel calculation flowchart of the SUM summation module in the embodiment of the present application; Figure 6 is a calculation flowchart of the integer part w and the part m in the range [1, 2) in the natural logarithm calculation module in the embodiment of the present application; Figure 7 is a structure diagram of the Softmax instruction expanded by the RISC-V in the embodiment of the present application; Figure 8 is a schematic diagram of the Softmax expansion instruction in the embodiment of the present application. DETAILED DESCRIPTION

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs.

[0025] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0026] In the absence of conflict, the embodiments of the present invention and the features thereof may be combined with each other.

[0027] Example 1 like Figure 1 As shown, this embodiment provides a RISC-V-based Softmax instruction set extension method. In this embodiment, the method includes the following steps: The RISC-V processor adopts a three-stage pipeline structure, and its main processes include: Step S1, in the instruction fetch stage, after the instruction fetch unit Reg in the RISC-V processor receives the instruction fetch signal from the control unit Ctrl, it fetches the Softmax instruction from the Softmax instruction memory according to the address generated by the Softmax instruction counter PC.

[0028] Step S2, in the decoding stage, for the Softmax instruction, the decoding unit ID transfers the address of the target register rd and the addresses of the source registers rs1 and rs2 according to Opcode and funct3. At the same time, the instruction fetch unit and the registers access each other's memory, exchange data, and parse the data in the rs1 and rs2 registers from the reg register file. The parsed information is passed to the execution stage to provide it with clear operation instructions, data and addresses to be processed.

[0029] The Opcode, funct7 and funct3 of the Softmax instruction are parsed to determine the corresponding instruction functions and generate corresponding control signals.

[0030] Step S3, in the execution stage, the execution unit EX first takes out the data to be processed by the Softmax operation from the data memory, and then transmits the data to the Softmax calculation unit for calculation according to the control signal generated by the Softmax instruction in the decoding stage.

[0031] Execute the Softmax operation and write the Softmax calculation result back to the corresponding target register.

[0032] The RISC-V processor of the present invention adopts a three-stage pipeline structure. Taking the three-stage pipeline as an example, in the instruction fetch stage, the processor takes out the Softmax instruction from the Softmax instruction memory according to the address generated by the instruction counter PC. In the decoding stage, the Softmax instruction signal is parsed in the decoding unit by analyzing the encoding of Opcode, funct7 and funct3 to obtain the corresponding instruction function, and generates relevant control signals to pass the address of the target register and the address of the source register to the execution stage. In the execution stage, before executing the normalization instruction Softmax, the data is first taken out from the data memory, and then according to the control signal generated by the Softmax instruction, the data is passed to the Softmax calculation unit to execute the Softamx calculation process, and finally the Softmax result is written back to the corresponding target register. Therefore, the efficiency of Softmax calculation of data can be greatly improved, while reducing code complexity, power consumption and memory overhead, and enhancing the versatility of the RISC-V instruction set.

[0033] When calculating the denominator of the Softmax function, each input element will undergo an e-exponential operation, which may result in a value that is too large. However, due to the limited bit width of the hardware, the range of values ​​that can be represented is limited, so overflow may occur. If overflow occurs during the Softmax hardware calculation process, it will cause a large error in the calculation result, which will significantly reduce the accuracy of the neural network. To solve this problem, this design first compares all elements of the input z and finds the maximum value among them. , then perform subtraction on each element The element values ​​of the input Softmax function are constrained to be within the range of 0. In addition, by merging the logarithmic function and reusing the exponential function to eliminate division, digital underflow is also avoided, making the calculation process friendly to hardware implementation, so that the Softmax formula can be adjusted to: ; in, Is the current The data to be calculated, , is the maximum value.

[0034] The present invention will be described in more detail below with reference to the accompanying drawings.

[0035] Step S4, as Figure 2 As shown in the figure, the Softmax operation is mainly completed by four computing units: the maximum value search unit, the exponential calculation unit, the summation unit, and the logarithmic calculation unit. The Softmax calculation unit is divided into nine steps: the initial IDLE phase, the DATA_CHECK data check phase, the SPILT data segmentation phase, the FIND_MAX maximum value search phase, the CLAC_EXP exponential calculation phase, the CLAC_SUM summation phase, the LN_UNIT logarithmic calculation phase, the second CLAC_EXP exponential calculation phase, and the final PACK result packaging phase.

[0036] Step S40, IDLE stage, controls whether to enter the next stage according to the start calculation signal and pipeline busy signal transmitted from the execution stage.

[0037] Step S41, DATA_CHECK stage, performs data check and determines how much data is required for Softmax calculation based on funct7 passed in during the execution stage.

[0038] Step S42, SPILT stage, divides the data, and divides the data to be calculated into 32-bit target registers according to the number of data and the bit width represented in the instruction.

[0039] Step S43, as Figure 3 As shown, in the FIND_MAX stage, the segmented data is passed to the MAX search unit (maximum value search unit). The Max search stage is a tree-like parallel comparison circuit design for finding the maximum value. It determines how much data is involved in the calculation based on the valid_data_count signal input by the Softmax calculation unit, and improves the calculation efficiency through multi-layer pipeline and parallel comparison strategy. This unit supports 32-bit configurable data width and has a fixed 8-way input processing capability. It combines precise control logic based on the state machine and multi-layer parallel comparison method to achieve efficient parallel data processing while minimizing clock cycle and hardware resource consumption. Its calculation process is divided into the following three layers of comparison: The first comparison stage compares the input data in pairs and passes the last input value to the next stage directly if the number of data paths is odd. The second-layer comparison stage adjusts the comparison strategy based on the number of first-layer outputs: direct comparison is performed when there are less than or equal to 2 results, and pairwise parallel comparison is used when there are 3 or more results; The final comparison stage determines the global maximum by processing different input scenarios, especially the boundary cases of an odd number of inputs.

[0040] Preferably, step S44 is as follows Figure 4 As shown, in the CLAC_EXP stage, the temperature coefficient is determined according to the funct3 passed in the execution stage, and the data after the segmented data is subtracted from the maximum value is scaled by the temperature coefficient. Then, the data is sequentially input into the exponential calculation unit for exponential operation, and the exponential calculation result is returned to the Softmax calculation unit. In the Softmax calculation, the direct implementation of the exponential operation with base e may be complicated. Therefore, it can be considered to convert it to an exponential operation with base 2. The conversion method is as follows:

[0041] After conversion, x / ln2 is a decimal value, which is divided into the integer part u and the decimal part v.

[0042]

[0043] For the integer part , its calculation can be realized by shift operation; and for the fractional part 2^v, it can be solved by lookup table or approximate calculation method. This design uses Taylor expansion for approximate calculation. Through this conversion, the original exponential operation f(x) = , (where −∞ <x<+∞)被替换为硬件上的乘加与移位操作,从而显著降低了计算的复杂性,使硬件实现更加高效。

[0044] In the exponential calculation unit, first, the input x is multiplied by 1 / ln2, thereby converting the exponential operation with base e into an exponential operation with base 2. The multiplication result It can be split into the integer part u and the fractional part v, and then filled in according to the complement rule. Then, Taylor expansion is used to calculate , and perform shift operations according to u to obtain the final Since the initial input data is each element minus the maximum value of the row and then scaled according to the temperature coefficient, u must be a negative number. Therefore, the right shift operation is used during the shift, and the displacement number is -u.

[0045] For the above Perform Taylor expansion, because The range is (-1, 0). In order to reduce the error of Taylor expansion, Taylor expansion is performed at -0.5. All constant terms appearing in the Taylor formula can be approximated by right shift operations. By using shift instead of multiplication, the hardware implementation becomes more efficient. The Taylor formula expansion is expressed as:

[0046] Step S45, as Figure 5 As shown, in the CLAC_SUM stage, the Softmax calculation unit passes the data after the exponential calculation to the summation unit for summation, and returns the summation result to the Softmax calculation unit; This pipeline consists of four stages, with the valid_data_count input from the Softmax calculation unit determining the amount of data required for the calculation. Dynamic configuration allows the same hardware to efficiently handle different workloads. This operation is based on a binary tree reduction, dividing the summation problem into multiple parallel operation stages. Each stage reduces the number of values ​​by approximately half, significantly reducing the critical path based on the tree-based summation approach.

[0047] Step S46, as Figure 6 As shown, the LN_UNIT logarithmic operation unit and the Softmax calculation unit sequentially pass the summation result and the data after subtracting the maximum value from each original data to the logarithmic calculation unit, calculate the logarithmic result and return it to the Softmax calculation unit; Because direct division calculation consumes hardware resources, this paper uses Log-Sum-Exp Softmax to simplify the division calculation unit (logarithm solving unit). The main idea is to eliminate division by combining logarithmic functions and reusing exponential functions. In addition, it avoids digital underflow, making the calculation process friendly to hardware implementation. The formula is expressed as:

[0048] First, let , where F is not less than 1, and is expressed as follows:

[0049] Define m∈[1,2) and w as integers where S satisfies the following equation:

[0050] Then we get:

[0051] The leading ones detector (LOD) can be used to find the position of the highest bit F, which is 1. By giving the decimal point and the position of the highest bit, the value of the integer w can be derived. The value of m can be obtained by right-shifting F by w bits. Since the range of m is [1, 2), and a three-level Taylor expansion is performed at 1.5, all constant terms in the Taylor formula can be approximated by right shift operations. By using shifts instead of multiplications, the hardware implementation becomes more efficient. The expanded formula is expressed as:

[0052] Step S47, the second CLAC_EXP stage, the data to be Softmax operated is subtracted from the maximum value and then from the logarithmic calculation result, and the operation results are sequentially passed to the exponential calculation unit for the second exponential operation, and the final Softmax operation results are sequentially passed to the Softmax calculation unit.

[0053] Step S48, PACK stage, packs the final Softmax operation result, and determines whether it needs to be written into the second register according to the bit width of the data to be Softmax operated and the number of inputs.

[0054] If the second register is needed, the write enable of the second register is set to high, and the above calculation result and the write enable are passed to the execution stage.

[0055] Step S5, the execution phase receives the result and enable signal sent back by the Softmax calculation unit, detects whether the calculation is completed, and if the calculation is completed, transmits the write enable, the address of the target register, the result after calculation, and other signals to the register unit, and writes the result back to the target register.

[0056] Figure 7 This is a schematic diagram of the RISC-V instruction set R-type instruction structure used in the present invention. The invention uses RISC-V R-type instructions as the custom instruction format. The extended instructions include: rs1, rs2, rd, funct7, funct3 and opcode; The address widths of rs1, rs2, and rd registers are 5 bits, the width of funct7 is 7 bits, the width of funct3 is 3 bits, and the width of Opcode is 7 bits; rs1 records the register address of source operand 1, and rs2 records the register address of source operand 2; funct7 is divided into two parts, where [2:0] refers to the data width in the addresses of rs1 and rs2, and [6:3] refers to how much data in the rs1 and rs2 registers needs to be calculated for Softmax; funct3 represents the classification of Softmax, representing different temperature coefficients; Opcode represents the Softmax operation instruction.

[0057] Figure 8The schematic diagram of the data Softmax extension instruction of the application is shown in the figure, the Opcode code of the Softmax instruction is defined as 1111011, the funct3 field is 000 for the normal type Softmax, 001 for the Softmax with a temperature coefficient of 2, 010 for the Softmax with a temperature coefficient of 4, and 011 for the Softmax with a temperature coefficient of 8. The funct7 is divided into two parts, the [2:0] part is divided into 001 and 010, which respectively represent the bit width of 8 and 16, and the [6:3] part is 0010 to 1000, which respectively represent 2 to 8 data participating in the calculation; rs1 and rs1 represent the data to be normalized. Rd represents the normalized data.

[0058] The embodiment improves the computing efficiency. By directly supporting data Softmax operation at the hardware level, the number of instructions required for execution and the computing time are greatly reduced, and the efficiency is improved more significantly when processing large-scale data sets. Reduce the code complexity. Developers can directly use the Softmax instruction to realize the probability distribution calculation in the multi-classification task, without the need to combine multiple basic instructions, which simplifies the programming process and reduces the code maintenance complexity. Optimize power consumption and memory usage. Reduce the extra power consumption caused by multiple data loading, storage and intermediate result calculation, and at the same time reduce the demand for memory, improve the memory usage efficiency. The application enhances the generality and reusability of the instruction set. The new instruction is not only used for Softmax, but also can support other data processing tasks, which increases the flexibility and application range of the RISC-V instruction set. It has scalability. If other normalization operations need to be supported, they can be realized by combining and extending the existing instructions, without the need to redesign new instructions, which has good scalability.

[0059] Embodiment two The embodiment provides a RISC-V-based Softmax instruction set extension system, including a RISC-V processor and a hardware acceleration device integrated in the RISC-V processor for Softmax instruction set extension; wherein the hardware acceleration device includes a Softmax instruction memory, a decoding unit, a data storage unit, a Softmax calculation unit, a Softmax instruction memory and a target register; The Softmax calculation unit interacts with the maximum value finding unit, the exponential solving unit, the summation unit and the logarithm solving unit; When the Softmax instruction is executed, the instruction fetching unit in the RISC-V processor first takes out the data to be operated by the Softmax from the data storage unit in the data storage unit, and sends it to the Softmax calculation unit for efficient Softmax formula calculation, and writes the result back to the target register.

[0060] Embodiment three This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the steps in the RISC-V-based Softmax instruction set extension method as described in the above embodiment 1 are implemented.

[0061] Example 4 This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps of the RISC-V-based Softmax instruction set extension method described in the first embodiment are implemented.

[0062] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage and optical storage, etc.) containing computer-usable program code.

[0063] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0064] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0065] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0066] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0067] Although the above describes the specific embodiments of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without any creative work are still within the scope of protection of the present invention.

Claims

1. The Softmax instruction set extension method based on RISC-V is characterized by: The RISC-V processor uses an N-stage pipeline structure, including: In the instruction fetch stage, the instruction fetch unit in the RISC-V processor fetches the Softmax instruction from the Softmax instruction memory according to the address generated by the instruction counter PC; In the decoding stage, the decoding unit analyzes the Opcode, funct7 and funct3 of the Softmax instruction to determine the corresponding instruction functions and generates corresponding control signals. In the execution phase, the execution unit takes the data to be Softmax calculated from the data memory and passes it to the Softmax calculation unit according to the control signal; the Softmax calculation is performed according to the following formula, and the Softmax calculation result is written back to the target register; ； in, Is the current The data to be calculated, , is the maximum value.

2. The RISC-V-based Softmax instruction set extension method according to claim 1, wherein: The Softmax calculation unit includes five processes: maximum value search, exponential solution, summation, logarithmic solution and multiplexed exponential calculation; When the RISC-V processor detects the Softmax instruction, the data memory sends the data to be Softmax-operated to the Softmax calculation unit for Softmax operation.

3. The RISC-V-based Softmax instruction set extension method according to claim 2, wherein: The data memory sends the data to be processed by the Softmax operation to the Softmax calculation unit for Softmax operation, specifically: The data to be processed by Softmax operation is first passed to the maximum value search unit for data comparison to obtain the maximum value, and the maximum value is returned to the Softmax calculation unit; The data to be processed by Softmax calculation is subtracted from the maximum value and then scaled by the temperature coefficient, and then passed to the exponential calculation unit for exponential calculation, and the exponential calculation result is returned to the Softmax calculation unit; The Softmax calculation unit passes the exponential calculation result to the summation unit, the summation unit sums the exponential calculation results and returns the summation result to the Softmax calculation unit; The Softmax calculation unit passes the summation result to the logarithm solution unit, and the logarithm solution unit performs a natural logarithm operation on the summation result and returns the logarithm solution result to the Softmax calculation unit; The Softmax calculation unit passes the logarithmic solution result to the exponential calculation unit, reuses the exponential calculation unit, subtracts the maximum value from the data to be Softmax calculated, subtracts the logarithmic solution result, and performs exponential calculation again to obtain the final Softmax calculation result and return it to the Softmax calculation unit.

4. The RISC-V-based Softmax instruction set extension method according to claim 3, wherein: The Softmax calculation unit is divided into nine steps, namely the initial IDLE stage, the DATA_CHECK data checking stage, the SPILT data segmentation stage, the FIND_MAX maximum value finding stage, the CLAC_EXP index calculation stage, the CLAC_SUM summation stage, the LN_UNIT logarithm calculation stage, the second CLAC_EXP index calculation stage and the final PACK result packaging stage; In the IDLE stage, whether to enter the next stage is controlled according to the start calculation signal and pipeline busy signal transmitted from the execution stage; In the DATA_CHECK phase, data is checked and the total amount of data for Softmax calculation is determined based on the funct7 passed in during the execution phase. In the SPILT stage, the data to be processed by the Softmax operation is segmented and placed into the target register according to the number of data and bit width information indicated in the instruction. In the FIND_MAX stage, the segmented data is passed to the maximum value search unit, and the maximum value result is obtained through parallel comparison and returned to the Softmax calculation unit; In the CLAC_EXP stage, the temperature coefficient is determined according to the funct3 passed in the execution stage. The data after subtracting the maximum value from the segmented data is scaled by the temperature coefficient. The data is then input into the exponential calculation unit for exponential operation, and the exponential calculation result is returned to the Softmax calculation unit. In the CLAC_SUM stage, the Softmax calculation unit passes the data after exponential calculation to the summation unit for summation, and returns the summation result to the Softmax calculation unit; In the LN_UNIT stage, the Softmax calculation unit passes the summation result and the data after subtracting the maximum value from each original data to the logarithm calculation unit in sequence, calculates the logarithm result and returns it to the Softmax calculation unit; In the second CLAC_EXP stage, the data to be Softmax operated is subtracted from the maximum value and then from the logarithmic calculation result, and the operation results are sequentially passed to the exponential calculation unit for the second exponential operation, and the final Softmax operation results are sequentially passed to the Softmax calculation unit; In the PACK stage, the final Softmax operation result is packaged and judged whether it needs to be written into the second register based on the bit width of the data to be Softmax operated and the number of inputs; If the second register is needed, the write enable of the second register is set to a high level, and the above calculation result and the write enable are passed to the execution stage.

5. The RISC-V-based Softmax instruction set extension method according to claim 1, wherein: The execution stage receives the calculation result transmitted by the Softmax calculation unit as an enable signal, detects whether the calculation is completed, and writes the calculation result and address information back to the target register if the calculation is completed.

6. The RISC-V-based Softmax instruction set extension method according to claim 1, wherein: The RISC-V R-type instruction is used as the Softmax instruction format, where the Softmax instruction includes: rs1, rs2, rd, funct7, funct3 and opcode; The address width of rs1, rs2 and rd registers is 5 bits, the width of funct7 is 7 bits, the width of funct3 is 3 bits, and the width of opcode is 7 bits; rs1 records the register address of source operand 1, and rs2 records the register address of source operand 2; Funct7 is divided into two parts, where [2:0] is used to refer to the data bit width in the rs1 and rs2 addresses, and [6:3] refers to how much data in the rs1 and rs2 registers needs to be calculated for Softmax; funct3 represents the classification of Softmax, representing different temperature coefficients; Opcode represents the Softmax operation instruction.

7. The RISC-V-based Softmax instruction set extension method according to claim 1, wherein: The Opcode encoding of the Softmax instruction is defined as 1111011; The funct3 field includes: 000 for normal Softmax, 001 for Softmax with a temperature coefficient of 2, 010 for Softmax with a temperature coefficient of 4, and 011 for Softmax with a temperature coefficient of 8; Funct7 is divided into two parts. The [2:0] part is divided into 001 and 010, indicating that the bit width is 8 and 16 respectively. The [6:3] part 0010 to 1000 respectively indicates that 2 to 8 data are involved in the calculation; rs1 and rs1 represent the data to be normalized, and rd represents the normalized data.

8. The RISC-V-based Softmax instruction set extension system is characterized by: The invention comprises a RISC-V processor and a hardware acceleration device for Softmax instruction set extension integrated in the RISC-V processor; wherein the hardware acceleration device comprises a Softmax instruction memory, a decoding unit, a data memory, a Softmax calculation unit, a Softmax instruction memory and a target register; The Softmax calculation unit interacts with the maximum value search unit, the exponential solution unit, the summation unit, and the logarithmic solution unit; When the Softmax instruction is executed, the instruction fetch unit in the RISC-V processor first retrieves the data to be Softmax operated from the data memory through the loading data storage unit, and sends it to the Softmax calculation unit for efficient calculation of the Softmax formula, and writes the result back to the target register.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the RISC-V-based Softmax instruction set extension method as described in any one of claims 1 to 7 are implemented.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps in the RISC-V-based Softmax instruction set extension method according to any one of claims 1 to 7 are implemented.

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