High-side driving circuit applied to gallium nitride fully-integrated half-bridge power chip

Abstract

The invention discloses a high-side driving circuit applied to a gallium nitride fully-integrated half-bridge power chip, and belongs to the field of power integrated circuits. The circuit comprises an input stage circuit, an anti-VSW negative voltage shift circuit and a low-power-consumption output stage circuit. Wherein the anti-VSW negative voltage shift circuit guarantees correct transmission of a signal under a VSW node negative voltage condition through a negative voltage transmission structure, and in addition, the anti-VSW negative voltage shift circuit can generate an advanced pulse control signal for the low-power-consumption output stage circuit; and the low-power-consumption output stage circuit only charges the bootstrap capacitor in a short time before the output state is changed through the advanced pulse control signal, so that the problem of high power consumption of a capacitor charging branch in a traditional scheme is greatly relieved. According to the invention, the signal transmission reliability of the high-side driving circuit under the negative-voltage working condition is remarkably improved, the static power consumption is effectively reduced, and the high reliability and low power consumption requirements of the gallium nitride fully-integrated half-bridge driving chip on the high-side access are considered.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power integrated circuits, in particular to a high-side drive circuit applied to a gallium nitride full-integrated half-bridge power chip. BACKGROUND

[0002] Gallium nitride (GaN) power devices are based on the third generation semiconductor material, and have characteristics such as wide bandgap, high frequency and high efficiency, and high voltage resistance, which can improve the switching speed and power density of electric energy systems such as half-bridge circuits. With the increase of system working frequency, the discrete driving scheme of using silicon-based driving chip to drive gallium nitride devices is prone to induce ringing, overshoot and other problems due to its large driving loop parasitic inductance, which seriously affects the reliability of the system. Benefiting from the current mature N-type gallium nitride full-integrated process, the half-bridge driving circuit and the gallium nitride power device can be integrated on one chip to avoid the reliability problems faced by the discrete scheme.

[0003] At present, the high-side drive circuit of the traditional integrated gallium nitride process faces the following problems:

[0004] 1. When a relatively large negative voltage appears at the V SW node, the logic circuit in the traditional integrated gallium nitride process high-side drive circuit cannot pick up the valid signal output from the level shift circuit, resulting in signal transmission failure.

[0005] 2. During the operation of the traditional integrated gallium nitride process high-side drive circuit, the self-lift capacitor needs to be continuously charged by the voltage drop on the resistor during the static period of the traditional output stage circuit, and there is a static current on the resistor. However, the resistor is located in the self-lift acceleration loop. If the resistance is increased to reduce the static current, the pull-up speed will be reduced, so the traditional output stage circuit faces the serious trade-off problem of speed and power consumption. SUMMARY

[0006] The present application aims to provide a high-side drive circuit applied to a gallium nitride full-integrated half-bridge power chip, which can effectively improve the anti-V SW negative voltage capability of the high-voltage level shift circuit and reduce the power consumption of the output stage circuit.

[0007] To achieve the above functions, the present application designs a high-side drive circuit applied to a gallium nitride full-integrated half-bridge power chip, which comprises: an input stage circuit, an anti-negative voltage level shift circuit, and a low-power consumption output stage circuit.

[0008] The input stage circuit inputs the overall input signal V IN and performs filtering;

[0009] The anti-negative voltage level shift circuit includes a pulse generation circuit, an anti-negative voltage level shift branch, an output stage control signal generation circuit, and a latch.

[0010] The pulse generating circuit processes the input signal after filtering by the input stage circuit to generate two narrow pulse signals, which correspond to the rising edge and falling edge of the input signal respectively;

[0011] The input signals of the anti-negative voltage level shift branch are two narrow pulse signals generated by the pulse generating circuit, and two processed narrow pulse signals are generated and output to the output stage control signal generating circuit respectively;

[0012] The input signals of the output stage control signal generating circuit are respectively the two narrow pulse signals output by the anti-negative voltage level shifting branch, the signals are processed and delayed respectively, and two narrow pulse signals are output respectively, the two signals before delay are output respectively to the low-power output stage circuit, and the two signals after delay are output respectively to the latch;

[0013] The latch is used to restore the input narrow pulse signal to a level signal;

[0014] The input signal of the low-power output stage circuit is the output signal of the latch and the two narrow pulse signals output by the output stage control signal generating circuit, and the output signal is the overall output signal V OUT , used to improve the output driving capability of the overall circuit.

[0015] As a preferred technical solution of the present invention: the anti-negative voltage level shifting branch included in the anti-negative voltage level shifting circuit specifically includes a first anti-V SW Negative voltage level shift branch, second anti-V SW Negative voltage level shift branch; the output stage control signal generating circuit included in the anti-negative voltage level shift circuit specifically includes a first output stage control signal generating circuit and a second output stage control signal generating circuit;

[0016] The first anti-V SW The input signal of the negative voltage level shift branch is the narrow pulse signal generated by the pulse generating circuit, and the output signal is connected to the first output stage control signal generating circuit, which is used to convert the level of the input narrow pulse signal from the low voltage domain to the high voltage domain and generate a negative voltage level shift signal at V SW Ensure correct signal transmission under negative pressure;

[0017] The second anti-V SW The input signal of the negative voltage level shift branch is the narrow pulse signal generated by the pulse generating circuit, and the output signal is connected to the second output stage control signal generating circuit, which is used to convert the level of the input narrow pulse signal from the low voltage domain to the high voltage domain and generate a negative voltage level shift signal at V SW Ensure correct signal transmission under negative pressure;

[0018] The input signal of the first output stage control signal generation circuit is the first anti-V SW The output signal of the negative voltage level shift branch is used to shift the first anti-V SW The narrow pulse signal output by the negative voltage level shift branch is shaped and subjected to NAND logic processing, and then delayed, and the signal before delay is output to the low-power output stage circuit, and the signal after delay is output to the latch.

[0019] The input signal of the second output stage control signal generation circuit is the second anti-V SW The output signal of the negative voltage level shift branch is used to shift the second anti-V SW The narrow pulse signal output by the negative voltage level shift branch is shaped and subjected to NAND logic processing, and then delayed, and the signal before delay is output to the low-power output stage circuit, and the signal after delay is output to the latch.

[0020] As a preferred technical solution of the present application, the first anti-V SW The negative voltage level shift branch comprises: a high-voltage NMOS tube M HVE1 , a high-voltage NMOS tube M HVE3 , an NMOS tube M E25 , a capacitor C3, a resistor R3, a resistor R5, and a first inverter INV1.

[0021] The first anti-V SW The connection relationship of the negative voltage level shift branch is that the gate of the high-voltage NMOS tube M HVE1 is connected to the ground signal GND of the low-voltage domain power supply rail and the drain of the NMOS tube M E25 , the source of the high-voltage NMOS tube M HVE1 is connected to the gate of the NMOS tube M E25 , the source of the NMOS tube M E25 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to the output end of the first inverter INV1, the drain of the high-voltage NMOS tube M HVE1 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the power supply signal V DDH of the high-voltage domain power supply rail, the gate of the high-voltage NMOS tube M HVE3 is connected to the input end of the first inverter INV1, and the input end of the first inverter INV1 is connected to the output end of the pulse generation circuit.

[0022] The source of the high-voltage NMOS tube M HVE3 is connected to the ground signal GND of the low-voltage domain power supply rail, the drain of the high-voltage NMOS tube M HVE3 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power supply signal V DDH of the high-voltage domain power supply rail.

[0023] As a preferred technical solution of the present application: the second anti-V SW The negative voltage level shifting branch comprises: a high-voltage NMOS tube M HVE2 , a high-voltage NMOS tube M HVE4 , an NMOS tube M E26 , a capacitor C4, a resistor R4, a resistor R6, and a second inverter INV2.

[0024] The second anti-V SW The connection relationship of the negative voltage level shifting branch is: the gate of the high-voltage NMOS tube M HVE2 is connected to the ground signal GND of the low-voltage domain power supply rail and the drain of the NMOS tube M E26 , the source of the high-voltage NMOS tube M HVE2 is connected to the gate of the NMOS tube M E26 , the source of the NMOS tube M E26 , and one end of the capacitor C4, the other end of the capacitor C4 is connected to the output end of the second inverter INV2, the drain of the high-voltage NMOS tube M HVE2 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power signal V DDH of the high-voltage domain power supply rail. HVE4 The gate of the high-voltage NMOS tube M HVE4 is connected to the input end of the second inverter INV2, and the input end of the second inverter INV2 is connected to the output end of the pulse generating circuit.

[0025] The source of the high-voltage NMOS tube M HVE4 is connected to the ground signal GND of the low-voltage domain power supply rail, and the drain of the high-voltage NMOS tube M DDH is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the power signal V .

[0026] As a preferred technical solution of the present application: the first output stage control signal generating circuit comprises: an NMOS tube M E9 , an NMOS tube M E10 , an NMOS tube M E11 , an NMOS tube M E12 , an NMOS tube M E13 , an NMOS tube M E14 , an NMOS tube M E15 , an NMOS tube M E16 , a capacitor C5, a resistor R7, a resistor R9, a first clamping circuit, and a second clamping circuit.

[0027] The connection relationship of the first output stage control signal generating circuit is: the gate of the NMOS tube M E9 is connected to the high-voltage NMOS tube M SW in the first anti-V negative voltage level shifting branch.HVE3 The drain of NMOS tube M E11 The gate of NMOS tube M E13 The gate of the first clamp circuit and one end of the first clamp circuit are connected, and the other end of the first clamp circuit is connected to the ground signal V SW , NMOS tube M E9 The source of the NMOS tube M is connected E10 The drain of NMOS tube M E9 The drain of the NMOS tube M E15 The gate of the resistor R7 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the NMOS tube M E16 The drain of NMOS tube M E10 The gate of the first resistor is connected to V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE1 The drain of NMOS tube M E12 The gate of NMOS tube M E14 The gate and one end of the second clamp circuit, the other end of the second clamp circuit is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E10 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E10 The drain of the NMOS tube M E9 The source of NMOS tube M E11 The drain of the NMOS tube M E15 The source of NMOS tube M E11 The source of the NMOS tube M is connected E12 The drain of NMOS tube M E12 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E13 The drain of the latch is connected to the S port and one end of the resistor R9, and the other end of the resistor R9 is connected to the NMOS tube M E11 The drain of the capacitor C5 and one end of the capacitor C5 are connected to the NMOS tube M E16 The drain of NMOS tube M E13 The source of the NMOS tube M is connected E14 The drain of NMOS tube M E14 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E15 The gate of the NMOS tube M is connected E9 The drain of NMOS tube M E15 The source of the NMOS tube M is connected E11 The drain of NMOS tube M E15 The drain of the NMOS tube M E16the gate of the NMOS transistor M DDH the source of the NMOS transistor M E16 is connected to the power signal V of the high-voltage domain power rail DDH .

[0028] As a preferred technical solution of the present application: the second output stage control signal generation circuit comprises: NMOS transistor M E17 NMOS transistor M E18 NMOS transistor M E19 NMOS transistor M E20 NMOS transistor M E21 NMOS transistor M E22 NMOS transistor M E23 NMOS transistor M E24 capacitor C6, resistor R8, resistor R 10 first clamping circuit, second clamping circuit

[0029] The connection relationship of the second output stage control signal generation circuit is: the gate of the NMOS transistor M E21 is connected to the second anti-V SW negative voltage level shift branch high-voltage NMOS transistor M HVE4 drain, the gate of the NMOS transistor M E19 , the gate of the NMOS transistor M E17 and one end of the third clamping circuit, the other end of the third clamping circuit is connected to the ground signal V of the high-voltage domain power rail SW the source of the NMOS transistor M E21 is connected to the drain of the NMOS transistor M E22 , the drain of the NMOS transistor M E21 is connected to the gate of the NMOS transistor M E24 and one end of the resistor R8, the other end of the resistor R8 is connected to the drain of the NMOS transistor M E23 , the gate of the NMOS transistor M E22 is connected to the second anti-V SW negative voltage level shift branch high-voltage NMOS transistor M HVE2 drain, the gate of the NMOS transistor M E20 , the gate of the NMOS transistor M E18 and one end of the fourth clamping circuit, the other end of the fourth clamping circuit is connected to the ground signal V of the high-voltage domain power rail SW , the source of the NMOS transistor M E22 is connected to the ground signal V of the high-voltage domain power rail SW , the drain of the NMOS transistor M E22 is connected to the source of the NMOS transistor M E21 , the drain of the NMOS transistor M E19 is connected to the source of the NMOS transistor M E24The source of NMOS tube M E19 The source of the NMOS tube M is connected E20 The drain of NMOS tube M E20 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E17 The drain of the latch is connected to the R port and the resistor R 10 One end of the resistor R 10 The other end is connected to NMOS tube M E19 The drain of the capacitor C6 and one end of the capacitor C6 are connected to the NMOS tube M E23 The drain of NMOS tube M E17 The source of the NMOS tube M is connected E18 The drain of NMOS tube M E18 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E24 The gate of the NMOS tube M is connected E21 The drain of NMOS tube M E24 The source of the NMOS tube M is connected E19 The drain of NMOS tube M E24 The drain of the NMOS tube M E23 The gate and high voltage domain power rail power supply signal V DDH , NMOS tube M E23 The source of the high voltage domain power rail is connected to the power signal V DDH .

[0030] As a preferred technical solution of the present invention: the low-power output stage circuit includes a first-stage low-power inverter circuit and a second-stage low-power inverter circuit with the same structure; wherein the first-stage low-power inverter circuit includes: an NMOS transistor M E1 、NMOS tube M E2 、NMOS tube M E3 、NMOS tube M E4 , capacitor C1, resistor R1; the second-stage low-power inverter circuit includes: NMOS tube M E5 、NMOS tube M E6 、NMOS tube M E7 、NMOS tube M E8 , capacitor C2, resistor R2;

[0031] The connection relationship of the low power output stage circuit is: NMOS tube M E1 The gate of the latch is connected to the Q port and the NMOS tube M E2 The gate of NMOS tube M E1 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube ME1 The drain of the NMOS tube M E3 The gate of the resistor R1 and one end of the resistor R1 are connected to the NMOS tube M E4 The drain of NMOS tube M E2 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E2 The drain of the NMOS tube M E3 The source of NMOS tube M E5 The gate of the NMOS tube M is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the NMOS tube M E4 The drain of NMOS tube M E3 The gate of the NMOS tube M is connected E1 The drain of NMOS tube M E3 The drain of the high voltage domain power rail is connected to the power signal V DDH , NMOS tube M E4 The gate of the NMOS transistor M is connected to the second output stage control signal generating circuit. E19 The drain of NMOS tube M E4 The source is connected to the power supply signal V DDH , NMOS tube M E5 The gate of the NMOS tube M is connected E6 The gate and NMOS tube M E2 The drain of NMOS tube M E5 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E5 The drain of the NMOS tube M E7 The gate of the resistor R2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the NMOS tube M E8 The drain of NMOS tube M E6 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E6 The drain of the NMOS tube M E7 The source of the overall output signal port V OUT and one end of capacitor C2, and the other end of capacitor C2 is connected to NMOS tube M E8 The drain of NMOS tube M E7 The gate of the NMOS tube M is connected E5 The drain of NMOS tube M E7 The drain of the high voltage domain power rail is connected to the power signal V DDH , NMOS tube M E8 The gate of the NMOS transistor M is connected to the first output stage control signal generating circuit. E11 The drain of NMOS tube M E8The source of the high-voltage domain power rail DDH .

[0032] As a preferred technical solution of the application: the input of the pulse generating circuit is the output signal of the input stage circuit, and the output is two narrow pulse signals, and the connection relationship is: the signal input port of the pulse generating circuit is connected with the output end of the input stage circuit, the input end of the input stage circuit is connected with the input signal V IN of the whole circuit, the pulse signal V RP+ generated by the pulse generating circuit is connected with the first resistor V SW , the gate of the high-voltage NMOS tube M HVE3 in the negative voltage level shifting branch and the input end of the inverter INV1, the pulse signal V FP+ generated by the pulse generating circuit is connected with the second resistor V SW , the gate of the high-voltage NMOS tube M HVE4 in the negative voltage level shifting branch and the input end of the inverter INV2, the power port is connected with the power signal V DDL of the low-voltage domain power rail, and the ground port is connected with the ground signal GND of the low-voltage domain power rail.

[0033] As a preferred technical solution of the application: the R port and the S port of the latch are input ports, and the Q port is an output port, the S port is connected with the drain of the NMOS tube M E13 in the first output stage control signal generating circuit, the R port is connected with the drain of the NMOS tube M E17 in the second output stage control signal generating circuit, and the Q port is connected with the gate of the NMOS tube M E1 in the low-power output stage circuit, the power port of the latch is connected with the power signal V DDH of the high-voltage domain power rail, and the ground port of the latch is connected with the ground signal V SW .

[0034] As a preferred technical solution of the application: the NMOS tube, the resistor and the capacitor constituting the circuit are all devices based on the gallium nitride process.

[0035] Advantages: Compared with the prior art, the application has the following advantages:

[0036] 1. effectively improve the anti-V SW node negative voltage capability of the high-side drive circuit: in view of the problem of insufficient anti-negative voltage capability of the high-voltage level shifting circuit of the traditional integrated gallium nitride process high-side drive circuit, the application improves the anti-V SW node negative voltage capability of the high-side drive circuit.The negative voltage transmission structure in the negative voltage level shift branch generates an effective low voltage signal, so that the signal can be picked up by a subsequent logic circuit, the transmission of the signal from a low voltage domain to a high voltage domain is guaranteed, signal loss is avoided, and the system reliability is effectively improved without significantly increasing power consumption.

[0037] 2. Effectively reduce the static power consumption of the high-side drive circuit: in order to solve the problem of high static power consumption of the high-side drive circuit of the traditional gallium nitride full-integrated half-bridge power chip, in the low-power gallium nitride output stage circuit provided in the application, two bootstrap capacitors are alternately and intermittently charged and discharged by using a pre-charge input pulse, that is, the bootstrap capacitors are charged only when the bootstrap acceleration circuit is pulled up, and no charging is required at other times, so that a continuous static current is not required to generate a voltage drop on the resistor. By using the pre-charge technology, the static power consumption of the high-side drive circuit is greatly reduced without sacrificing the flip speed of the drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 is a typical application diagram of a gallium nitride full-integrated power chip according to an embodiment of the application;

[0039] Figure 2 is a high-side drive circuit structure diagram of a traditional gallium nitride full-integrated half-bridge drive chip according to an embodiment of the application;

[0040] Figure 2 in which: 001, output stage circuit; 002, pulse generation circuit; 003, level shift branch; 004, latch;

[0041] Figure 3 is a high-side drive circuit working waveform error generation principle diagram of a traditional gallium nitride full-integrated half-bridge power chip according to an embodiment of the application;

[0042] Figure 4 is a high-side drive circuit structure diagram of a gallium nitride full-integrated half-bridge power chip according to an embodiment of the application;

[0043] Figure 4 in which: 001, low-power output stage circuit; 002, pulse generation circuit; 003, first anti-V SW negative voltage level shift branch; 004, second anti-V SW negative voltage level shift branch; 005, first output stage control signal generation circuit; 006, second output stage control signal generation circuit; 007, latch;

[0044] Figure 5 is a waveform schematic diagram of a pulse generation circuit according to an embodiment of the application;

[0045] Figure 6 is a structure diagram of a clamping circuit according to an embodiment of the application;

[0046] Figure 7 1 is a schematic diagram of operating waveforms of a high-side drive circuit applied to a gallium nitride fully integrated half-bridge power chip according to an embodiment of the present invention;

[0047] Figure 8 2 is a schematic diagram of operating waveforms of a low-power output stage circuit provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0049] Figure 1 A typical application diagram of a fully integrated GaN power chip is shown. From the perspective of signal flow, the half-bridge driver circuit consists of a high-side path and a low-side path. The high-side path is responsible for accurately transmitting logic control signals in the high-voltage domain and is the focus of the design. The core components of the high-side path are the high-voltage level shift circuit and the output stage circuit. The former is responsible for converting the drive control signal from the fixed power rail GND to V DDL transferred to the floating power rail V SW ~V DDH , realizing the control of high-voltage circuit system by low-voltage signal, the latter’s function is to improve the output driving capability of the circuit.

[0050] Figure 2 The high-side driver circuit structure of a traditional GaN fully integrated half-bridge driver chip is shown in Figure 1. The high-side driver circuit of a traditional GaN fully integrated half-bridge driver chip includes an input stage circuit, a level shift circuit, and an output stage circuit 001. The level shift circuit includes a pulse generation circuit 002, a level shift branch 003, and a latch 004. The pulse generation circuit 002 generates two narrow pulse signals V according to the rising and falling edges of the input signal. RP 、V FP The two narrow pulse signals enter the level shift branch 003 and are converted to the high voltage domain power rail, and the output signal V RIN 、V SIN The voltage range is V SW ~V DDH The latch 004 restores the signal and then inputs it to the output stage circuit 001. The output stage circuit 001 is composed of two GaN inverter circuits, which ensure that the signal polarity remains unchanged while improving the circuit's ability to drive the gate of the subsequent power device.

[0051] Figure 3 This is the schematic diagram of the high-side drive circuit operating waveform error of the traditional GaN fully integrated half-bridge power chip. Figure 2The circuit structure diagram, in the high and low side output dead time, there will be low side power tube off and high side power tube has not opened, the load inductance is in order to continue to flow, to V SW The node discharges. Since the gallium nitride transistor has no parasitic diode, the reverse conduction voltage drop is large, so V SW The node voltage will drop to a large negative voltage, greater than the switching threshold V TH Of the latch 004, at this time the output signal V RIN -V SW The level of the level shifting branch 003 cannot be lower than the switching threshold V TH , so that the rear stage latch 004 cannot pick up the valid signal output from the level shifting circuit, resulting in signal transmission failure, resulting in insufficient negative voltage resistance of the high voltage level shifting circuit.

[0052] Because the gallium nitride process lacks P-type transistor, it is difficult to realize high-performance pull-up branch. Therefore, the traditional method adopts N-type transistor and resistance capacitor to constitute the gallium nitride output stage circuit 001. The circuit includes two gallium nitride inverter circuits, the pull-down branch of the inverter circuit is composed of N-type transistor, and the pull-up branch is composed of bootstrap acceleration circuit including N-type transistor and capacitor resistance. On the premise of not sacrificing power consumption, the pull-up driving capability is ensured. However, when the inverter circuit is pulled down, there is still static current in the branch where the resistance is located, resulting in high static power consumption of the output stage circuit.

[0053] Compared with the high side driving circuit of the traditional gallium nitride full integrated half-bridge power chip, the high side driving circuit applied to the gallium nitride full integrated half-bridge power chip provided by the embodiment of the application, referring Figure 4 , comprises: an input stage circuit, a negative voltage resistant level shifting circuit and a low power consumption output stage circuit 001; the NMOS transistor, the resistance and the capacitor constituting the circuit are all devices based on the gallium nitride process.

[0054] The input stage circuit inputs the whole input signal V IN , and filters;

[0055] The negative voltage resistant level shifting circuit comprises a pulse generating circuit 002, a negative voltage resistant level shifting branch, an output stage control signal generating circuit and a latch 007.

[0056] The pulse generating circuit 002 processes the input signal filtered by the input stage circuit, generates two narrow pulse signals, and the two narrow pulse signals correspond to the rising edge and the falling edge of the input signal respectively.

[0057] The input signals of the negative voltage resistant level shifting branch are the two narrow pulse signals generated by the pulse generating circuit 002, and the two narrow pulse signals processed respectively are output to the output stage control signal generating circuit respectively.

[0058] The input signals of the output stage control signal generating circuit are respectively the two narrow pulse signals output by the anti-negative voltage level shifting branch, the signals are processed and delayed respectively, and two narrow pulse signals are output respectively, the two signals before delay are output respectively to the low power output stage circuit, and the two signals after delay are output respectively to the latch 007;

[0059] The anti-negative voltage level shifting branch included in the anti-negative voltage level shifting circuit specifically includes a first anti-V SW Negative voltage level shift branch 003, second anti-V SW Negative voltage level shift branch 004; the output stage control signal generating circuit included in the anti-negative voltage level shift circuit specifically includes a first output stage control signal generating circuit 005 and a second output stage control signal generating circuit 006;

[0060] The first anti-V SW The input signal of the negative voltage level shift branch 003 is the narrow pulse signal generated by the pulse generating circuit 002, and the output signal is connected to the first output stage control signal generating circuit 005, which is used to convert the level of the input narrow pulse signal from the low voltage domain to the high voltage domain and generate a negative voltage level shift signal at V SW Ensure correct signal transmission under negative pressure;

[0061] The first anti-V SW Negative voltage level shift branch 003 includes: high voltage NMOS tube M HVE1 , high voltage NMOS tube M HVE3 、NMOS tube M E25 , capacitor C3, resistor R3, resistor R5, first inverter INV1; wherein, high-voltage NMOS tube M HVE1 、NMOS tube M E25 , capacitor C3, resistor R5, and first inverter INV1 form a first negative voltage transmission structure for SW Ensure correct signal transmission when the node is under negative pressure;

[0062] The first anti-V SW The connection relationship of the negative voltage level shift branch 003 is: high voltage NMOS tube M HVE1 The gate of the NMOS tube M is connected to the ground signal GND of the low-voltage domain power rail. E25 The drain of the high-voltage NMOS tube M HVE1 The source of the NMOS tube M is connected E25 The gate of NMOS tube M E25 The source of the capacitor C3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the output end of the first inverter INV1. HVE1The drain of the resistor R5 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the power signal V DDH , high voltage NMOS tube M HVE3 The gate is connected to the input end of the first inverter INV1, and the input end of the first inverter INV1 is connected to the output end of the pulse generating circuit;

[0063] High voltage NMOS tube M HVE3 The source of the low-voltage domain power rail is connected to the ground signal GND, and the high-voltage NMOS tube M HVE3 The drain of the resistor R3 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power supply signal V DDH .

[0064] The second anti-V SW The input signal of the negative voltage level shift branch 004 is the narrow pulse signal generated by the pulse generating circuit, and the output signal is connected to the second output stage control signal generating circuit 006, which is used to convert the level of the input narrow pulse signal from the low voltage domain to the high voltage domain and generate a negative voltage level shift signal at V SW Ensure correct signal transmission under negative pressure;

[0065] The second anti-V SW Negative voltage level shift branch 004 includes: high voltage NMOS tube M HVE2 , high voltage NMOS tube M HVE4 、NMOS tube M E26 , capacitor C4, resistor R4, resistor R6, second inverter INV2; wherein, high-voltage NMOS tube M HVE2 、NMOS tube M E26 , capacitor C4, resistor R4, and second inverter INV1 form a second negative voltage transmission structure for SW Ensure correct signal transmission when the node is under negative pressure;

[0066] The second anti-V SW The connection relationship of the negative voltage level shift branch 004 is: high voltage NMOS tube M HVE2 The gate of the NMOS tube M is connected to the ground signal GND of the low-voltage domain power rail. E26 The drain of the high-voltage NMOS tube M HVE2 The source of the NMOS tube M is connected E26 The gate of NMOS tube M E26 The source of the capacitor C4 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is connected to the output end of the second inverter INV2. The high-voltage NMOS tube M HVE2 The drain of the resistor R6 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply signal V DDH , high voltage NMOS tube M HVE4The gate of the high-voltage NMOS transistor M

[0067] The source of the high-voltage NMOS transistor M HVE4 is connected to the ground signal GND of the low-voltage domain power supply rail, and the drain of the high-voltage NMOS transistor M HVE4 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the power supply signal V DDH .

[0068] The input signal of the first output stage control signal generation circuit 005 is the first anti-V SW negative voltage level shift branch 003 output signal, which is used to shape the narrow pulse signal output by the first anti-V SW negative voltage level shift branch 003, and then perform an AND NOT logic process, and then delay, output the signal before the delay to the low-power output stage circuit 001, and output the signal after the delay to the latch 007;

[0069] The first output stage control signal generation circuit 005 includes: NMOS transistors M E9 , NMOS transistors M E10 , NMOS transistors M E11 , NMOS transistors M E12 , NMOS transistors M E13 , NMOS transistors M E14 , NMOS transistors M E15 , NMOS transistors M E16 , a capacitor C5, a resistor R7, a resistor R9, a first clamping circuit, and a second clamping circuit; wherein the NMOS transistors M E9 , the NMOS transistors M E10 , the NMOS transistors M E11 , the NMOS transistors M E12 , the NMOS transistors M E15 , the NMOS transistors M E16 , and the resistor R7 constitute an AND NOT gate circuit, which is used to perform an AND NOT logic process on the narrow pulse signal output by the first anti-V SW negative voltage level shift branch 003 to generate a V R_START signal, the capacitor C5 and the resistor R9 constitute a delay circuit, which is used to delay the V R_START signal to generate a V RPH signal, and the clamping circuit is used to protect the transistors in the output stage control signal generation circuit from being broken down by overvoltage;

[0070] The connection relationship of the first output stage control signal generation circuit 005 is that the gate of the NMOS transistor M E9 is connected to the first anti-V SWThe high-voltage NMOS transistor M in the negative voltage level shift branch 003 HVE3 The drain of NMOS tube M E11 The gate of NMOS tube M E13 The gate of the first clamp circuit and one end of the first clamp circuit are connected, and the other end of the first clamp circuit is connected to the ground signal V SW , NMOS tube M E9 The source of the NMOS tube M is connected E10 The drain of NMOS tube M E9 The drain of the NMOS tube M E15 The gate of the resistor R7 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the NMOS tube M E16 The drain of NMOS tube M E10 The gate of the first resistor is connected to V SW The high-voltage NMOS transistor M in the negative voltage level shift branch 003 HVE1 The drain of NMOS tube M E12 The gate of NMOS tube M E14 The gate and one end of the second clamp circuit, the other end of the second clamp circuit is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E10 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E10 The drain of the NMOS tube M E9 The source of NMOS tube M E11 The drain of the NMOS tube M E15 The source of NMOS tube M E11 The source of the NMOS tube M is connected E12 The drain of NMOS tube M E12 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E13 The drain of the latch is connected to the S port and one end of the resistor R9, and the other end of the resistor R9 is connected to the NMOS tube M E11 The drain of the capacitor C5 and one end of the capacitor C5 are connected to the NMOS tube M E16 The drain of NMOS tube M E13 The source of the NMOS tube M is connected E14 The drain of NMOS tube M E14 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E15 The gate of the NMOS tube M is connected E9 The drain of NMOS tube M E15 The source of the NMOS tube M is connected E11 The drain of NMOS tube M E15the drain of NMOS transistor M E16 the gate of NMOS transistor M DDH the source of NMOS transistor M E16 the source of NMOS transistor M DDH .

[0071] the input signal of the second output stage control signal generation circuit 005 is the output signal of the second anti-V SW negative voltage level shift branch 004, for shaping the narrow pulse signal output by the second anti-V SW negative voltage level shift branch 004, and then performing a NAND logic process, and then delaying, outputting the signal before the delay to the low-power output stage circuit 001, and outputting the signal after the delay to the latch 007.

[0072] The second output stage control signal generation circuit 006 comprises: NMOS transistor M E17 , NMOS transistor M E18 , NMOS transistor M E19 , NMOS transistor M E20 , NMOS transistor M E21 , NMOS transistor M E22 , NMOS transistor M E23 , NMOS transistor M E24 , capacitor C6, resistor R8, resistor R 10 , first clamping circuit, second clamping circuit; wherein the NMOS transistor M E19 , NMOS transistor M E20 , NMOS transistor M E21 , NMOS transistor M E22 , NMOS transistor M E23 , NMOS transistor M E24 , resistor R8 constitutes a NAND gate circuit, for performing a NAND logic process on the narrow pulse signal output by the second anti-V SW negative voltage level shift branch 004 to generate V F_START signal, capacitor C6, resistor R 10 constitute a delay circuit, for delaying the V F_START signal to generate V FPH signal, and the clamping circuit is used to protect the transistors in the output stage control signal generation circuit from being broken down by overvoltage;

[0073] The connection relationship of the second output stage control signal generation circuit 006 is: the gate of NMOS transistor M E21 is connected to the high-voltage NMOS transistor M SW in the second anti-V HVE4 negative voltage level shift branch 004, the drain of NMOS transistor M E19gate of the NMOS transistor M E17 gate of the NMOS transistor M SW source of the NMOS transistor M E21 drain of the NMOS transistor M E22 drain of the NMOS transistor M E21 drain of the NMOS transistor M E24 gate of the NMOS transistor M E23 drain of the NMOS transistor M E22 gate of the NMOS transistor M SW high-voltage NMOS transistor M HVE2 drain of the NMOS transistor M E20 gate of the NMOS transistor M E18 gate of the NMOS transistor M SW source of the NMOS transistor M E22 source of the NMOS transistor M SW source of the NMOS transistor M E22 drain of the NMOS transistor M E21 source of the NMOS transistor M E19 drain of the NMOS transistor M E24 source of the NMOS transistor M E19 drain of the NMOS transistor M E20 source of the NMOS transistor M E20 source of the NMOS transistor M SW source of the NMOS transistor M E17 drain of the NMOS transistor M 10 one end of the resistor R 10 other end of the resistor R E19 drain of the NMOS transistor M E23 drain of the NMOS transistor M E17 source of the NMOS transistor M E18 drain of the NMOS transistor M E18 source of the NMOS transistor M SW source of the NMOS transistor M E24 gate of the NMOS transistor M E21 drain of the NMOS transistor M E24 source of the NMOS transistor M E19 drain of the NMOS transistor M E24 drain of the NMOS transistor M E23The gate and high voltage domain power rail power supply signal V DDH , NMOS tube M E23 The source of the high voltage domain power rail is connected to the power signal V DDH .

[0074] The latch 007 is used to restore the input narrow pulse signal to a level signal;

[0075] The R port and S port of the latch 007 are input ports, and the Q port is an output port. The S port is connected to the NMOS transistor M in the first output stage control signal generating circuit 005. E13 The drain of the R port is connected to the NMOS tube M in the second output stage control signal generating circuit 006. E17 The drain of the Q port is connected to the NMOS tube M in the low power output stage circuit 001. E1 The gate of latch 007 is connected to the power supply signal V of the high voltage domain power rail. DDH , the ground port of latch 007 is connected to the ground signal V of the high voltage domain power rail SW The latch 007 is used to convert two narrow pulse signals into a single output signal V OUT , a narrow pulse signal controls V OUT The signal rises from low level to high level, and another narrow pulse signal controls V OUT The signal drops from high level to low level, V OUT The period and pulse width of the signal are related to the overall high-side path input signal V INH Stay consistent.

[0076] The input of the pulse generating circuit 002 is the output signal of the input stage circuit, and the output is two narrow pulse signals. The connection relationship is: the signal input port of the pulse generating circuit 002 is connected to the output end of the input stage circuit, and the input end of the input stage circuit is connected to the overall circuit input signal V IN , the pulse signal V generated by the pulse generating circuit 002 RP+ Access the first anti-V SW The high-voltage NMOS transistor M in the negative voltage level shift branch 003 HVE3 The gate of the inverter INV1 and the input terminal of the pulse generating circuit 002 generate a pulse signal V FP+ Connect to the second anti-V SW The high-voltage NMOS transistor M in the negative voltage level shift branch 004 HVE4 The gate of the inverter and the input of INV2, the power port is connected to the power signal V of the low-voltage domain power rail DDL , the ground port is connected to the ground signal GND of the low-voltage domain power rail.

[0077] The input signal of the low power output stage circuit 001 is the output signal of the latch 007 and the two narrow pulse signals output by the output stage control signal generating circuit. The output signal is the overall output signal V OUT , used to improve the output driving capability of the overall circuit.

[0078] The low-power output stage circuit 001 includes a first-stage low-power inverter circuit and a second-stage low-power inverter circuit with the same structure; wherein the first-stage low-power inverter circuit includes: an NMOS transistor M E1 、NMOS tube M E2 、NMOS tube M E3 、NMOS tube M E4 , capacitor C1, resistor R1; the second-stage low-power inverter circuit includes: NMOS tube M E5 、NMOS tube M E6 、NMOS tube M E7 、NMOS tube M E8 , capacitor C2, resistor R2; the low power output stage circuit 001 uses the output stage control signal to generate the output pulse signal V F_START 、V R_START Control NMOS tube M respectively E4 、NMOS tube M E8 The circuit is periodically switched on and off to pre-charge the bootstrap capacitors C1 and C2, thereby completing the periodic pull-up process. The low-power output stage circuit 001 has a strong output driving capability while consuming relatively low power.

[0079] The connection relationship of the low power output stage circuit 001 is: NMOS tube M E1 The gate of the latch is connected to the Q port and the NMOS tube M E2 The gate of NMOS tube M E1 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E1 The drain of the NMOS tube M E3 The gate of the resistor R1 and one end of the resistor R1 are connected to the NMOS tube M E4 The drain of NMOS tube M E2 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E2 The drain of the NMOS tube M E3 The source of NMOS tube M E5 The gate of the NMOS tube M is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the NMOS tube M E4 The drain of NMOS tube M E3 The gate of the NMOS tube M is connected E1the drain of the NMOS transistor M E3 the drain of the NMOS transistor M DDH the drain of the NMOS transistor M E4 the gate of the NMOS transistor M E19 the drain of the NMOS transistor M E4 the source of the NMOS transistor M DDH the gate of the NMOS transistor M E5 the gate of the NMOS transistor M E6 the gate of the NMOS transistor M E2 the drain of the NMOS transistor M E5 the source of the NMOS transistor M SW the drain of the NMOS transistor M E5 the gate of the NMOS transistor M E7 the gate of the NMOS transistor M E8 the drain of the NMOS transistor M E6 the source of the NMOS transistor M SW the drain of the NMOS transistor M E6 the gate of the NMOS transistor M E7 the source of the NMOS transistor M OUT the gate of the NMOS transistor M E8 the drain of the NMOS transistor M E7 the gate of the NMOS transistor M E5 the drain of the NMOS transistor M E7 the drain of the NMOS transistor M DDH the gate of the NMOS transistor M E8 the gate of the NMOS transistor M E11 the drain of the NMOS transistor M E8 the source of the NMOS transistor M DDH .

[0080] The working principle of the high-side driving circuit for the gallium nitride full-integrated half-bridge power chip designed by the application is as follows: an input signal V INH After being filtered by the input stage circuit, the input signal enters the input port of the pulse generating circuit 002, and the waveform diagram of the pulse generating circuit 002 is as shown in Figure 5 The circuit structure diagram is shown in Figure 4 The pulse generating circuit is composed of an inverter INV3, an inverter INV4, an inverter INV5, an NOR gate NOR1, an NOR gate NOR2 and a delay circuit, and outputs two narrow pulse signals VRP+ , V FP+ , the amplitude range of the signal is from ground signal GND to power signal V DDL . V RP+ , V FP+ The signals are input to corresponding inverters INV1, INV2 respectively, and two inverted narrow pulse signals V RP- , V FP- are output respectively.

[0081] V RP+ The signal is input to the input port of the first negative voltage level shift branch 003, that is, the input end of the inverter INV1. The first negative voltage level shift branch 003 outputs V SW , the amplitude range of the signal is from floating ground signal V SW The first negative voltage level shift branch 003 includes high-voltage NMOS tube M HVE1 , high-voltage NMOS tube M HVE3 , NMOS tube M E25 , capacitor C3, resistor R3, resistor R5, and inverter INV1. The output is V RP+ , which is the inverse of V P1 , and V N3 , which is processed by the first negative voltage transmission structure, the amplitude range of the signal is from floating ground signal V SW to floating power signal V DDH . The first negative voltage transmission structure is composed of high-voltage NMOS tube M HVE1 , NMOS tube M E25 , capacitor C3, resistor R5, and inverter INV1.

[0082] V FP+ The signal is input to the input port of the second negative voltage level shift branch 004, that is, the input end of the inverter INV2. The second negative voltage level shift branch 004 outputs V SW , the amplitude range of the signal is from floating ground signal V SW The second negative voltage level shift branch 004 includes high-voltage NMOS tube M HVE2 , high-voltage NMOS tube M HVE4 , NMOS tube M E26 , capacitor C4, resistor R4, resistor R6, and inverter INV2. The output is V FP+ , which is the inverse of V P2 , and V N4 , which is processed by the second negative voltage transmission structure, the amplitude range of the signal is from floating ground signal V SW to floating power signal V DDH . The second negative voltage transmission structure is composed of high-voltage NMOS tube M HVE2 , NMOS tube M E26 , capacitor C4, resistor R4, and inverter INV2.

[0083] V P1、V N3 The signal is input to the two input ports of the first output stage control signal generating circuit 005, and is processed by the NAND gate circuit to generate V R_START Signal. Among them, the NAND gate circuit is composed of NMOS tube M E9 、NMOS tube M E10 、NMOS tube M E11 、NMOS tube M E12 、NMOS tube M E15 、NMOS tube M E16 , resistor R7. V R_START The signal is delayed and processed to generate V RPH The delay circuit is composed of capacitor C5 and resistor R9.

[0084] V P2 、V N4 The signal is input to the two input ports of the second output stage control signal generating circuit 006, and is processed by the NAND gate circuit to generate V F_START Signal. Among them, the NAND gate circuit is composed of NMOS tube M E19 、NMOS tube M E20 、NMOS tube M E21 、NMOS tube M E22 、NMOS tube M E23 、NMOS tube M E24 , resistor R8. V F_START The signal is delayed and processed to generate V FPH Signal. The delay circuit consists of capacitor C6, resistor R 10 constitute.

[0085] The specific implementation of the clamp circuit is as follows: Figure 6 As shown, the high voltage NMOS tube M HVE1 、NMOS tube M E1 、NMOS tube M E2 、NMOS tube M E3 、NMOS tube M E4 Composition, when anti-V SW The output node V of the negative voltage level shift branch P1 or V P2 Relative to V SW The node voltage is higher than three times the threshold voltage V TH When the two branches where the NMOS tube is located are turned on, the forward clamp is realized; when the node V P1 or V P2 Relative to V SW The node voltage is lower than the threshold voltage V TH When the high voltage NMOS tube M HVE1 Reverse conduction to achieve reverse clamping.

[0086] The working waveform schematic diagram of the high-side drive circuit applied to the gallium nitride full-integrated half-bridge power chip is shown in FIG. 1. Figure 7 Figure 7 In the figure, the abscissa corresponds to zero voltage. In the power supply system, the switch node V SW may appear negative voltage during the dead time of the half-bridge high and low side power tubes. The traditional high-side drive circuit may have reliability problems under the negative V SW condition. The high negative voltage resistance of the embodiment of the present application is described below taking the negative V SW condition as an example.

[0087] First, the signal transmission corresponding to the rising edge of V INH is analyzed. Before the arrival of V RP- , the lower plate V N1 of C3 is clamped to a voltage of about V TH by M E25 . When the rising edge of V INH arrives, the pulse generation circuit 002 outputs a narrow pulse V RP+ , and the inverter INV1 converts the narrow pulse V RP+ into an inverted narrow pulse V RP- . After the arrival of the pulse V RP- , V N1 is charged downward to V TH -V DDL by C3. At this time, M E25 is turned off, M HVE1 is turned on, and V N3 is pulled down to V TH -V DDL . This voltage is a negative voltage lower than V SW , and M E10 , M E12 and M E14 are all turned off, and the negative pulse V RP- is captured by the V SW supply rail circuit. It should be noted that during the V RP- pulse, R5 charges C3 through M HVE1 , and V N1 and V N3 voltages slowly rise. By reasonably setting the sizes of R5 and C3, it can be ensured that the V N3 voltage value is always valid low relative to the V SW supply rail circuit during the pulse. After the end of the pulse, V RP- is pulled up, V N1 is synchronously pulled up by C3, and finally is clamped by M E25 , and the size is about V TH . At this time, M HVE1 ​off, R5 quickly pulls up V N3 node pull-up, first resistor V SW negative voltage level shift branch complete V INH rising edge corresponding narrow pulse V RP+ transmission. In V INH rising edge, V FP+ and V FP- respectively remain low and high, M HVE2 and M HVE4 are not turned on, V N4 and V P2 are kept high.

[0088] V INH rising edge is transmitted to V SW power rail through the above process, and is input to the first output stage control signal generating circuit. A low enough V N3 pulse will turn off M E10 , M E12 and M E14 , and M E16 pre-charged bootstrap capacitor C5 through R7 charges the gate of M E15 , M E15 is turned on, V R_START node is quickly pulled up, further raising the voltage on the plate of C5, forming positive feedback, always ensuring that M E15 is in the on state, the output signal V RPH of the first output stage control signal generating circuit remains high, and V Q high state is latched by the latch. After the pulse ends, V Q still remains high. At this point, the high-side driver circuit has completed the transmission of the rising edge of V SW under negative voltage conditions to V INH .

[0089] Secondly, the signal transmission corresponding to the falling edge of V INH is analyzed. The pulse V FP+ turns on M HVE4 , V P2 is always maintained at about V SW -V TH during the pulse period, M E17 , M E19 and M E21 are turned off, and M E23 pre-charged bootstrap capacitor C6 through R8 charges the gate of M E24 , M E24 is turned on, V F_START node is quickly pulled up, further raising the voltage on the plate of C6, forming positive feedback, always ensuring that M E24In the on state, the output signal V of the first output stage control signal generating circuit FPH Keep it high, V Q The low level state is latched by the latch. After the pulse ends, V Q Still maintains a low level. So far, the high-side drive circuit has completed the V SW Under negative pressure, V INH Transmission on the falling edge.

[0090] In summary, the embodiment of the high-side drive circuit for a fully integrated gallium nitride half-bridge power chip provided by the present invention can SW Reliably complete V under negative pressure INH In contrast, the output signal V RIN and V SIN The low potential is limited by GND. When V SW The absolute value of the negative voltage is greater than the switching threshold voltage V TH When V RIN and V SIN Cannot be lower than V TH +V SW , making it impossible for the subsequent latch 004 to pick up the valid signal output from the level shift circuit, resulting in signal transmission failure.

[0091] Figure 8 Schematic diagram of the working waveform of the low-power output stage circuit provided by the embodiment of the present invention. In this figure, the vertical axis corresponding to the horizontal axis is V SW Voltage. Compared to Figure 2 The output stage circuit 001 in the embodiment of the present invention provides a low power output stage circuit 001 M E4 and M E8 The gate is no longer connected to a fixed potential V DDH Instead, it is connected to the pulse signals V outputted by the first output stage control signal generating circuit 005 and the second output stage control signal generating circuit 006 respectively. R_START and V F_START . By anti-V SW The working principle of the negative voltage level shift branch is analyzed. When the input signal V Q Before switching from high level to low level, V F_START A positive pulse will be generated, V R_START Keep 0 potential, V F_START Will M E4 Turn on and charge capacitor C1. Q After flipping to low level, C1 is fully charged. E1 and M E2 Close, C1 connects to M through R1E3 The gate is charged, M E3 Tube open, V O1 is pulled high, further raising the voltage of the upper plate of C1, M E4 Shutdown, C1 upper board voltage is higher than V DDH , forming a positive feedback, so that M E3 The tube is always fully open, and the final V O1 is quickly pulled up to V DDH , and then M E5 and M E6 Both tubes are open, V OUT is pulled down, V R_START is 0 potential, M E8 After the charge on C2 is discharged through R2, even if M E5 When it is turned on, the R2 branch will not generate static current. Q Before switching from low level to high level, V F_START is 0 potential, V R_START A pulse is generated at V IN After turning high, V F_START Continue to maintain 0 potential, so even if M E1 When the charge on C1 is discharged, the R1 branch does not generate static current, but is connected to V Q The working principle of the first stage driving circuit is the same when it is flipped from high level to low level. O1 Before turning low, V R_START The generated pulse will pre-charge C2 fully, O1 After the flip is completed, M E7 Complete V OUT Quick pull up.

[0092] Depend on Figure 8 It can be seen that in the embodiment of the low-power output stage circuit 001 provided by the present invention, during the static period, the quiescent currents I1 and I2 flowing through the branch where the resistors R1 and R2 are located are zero, that is, there is no static power consumption. During the static period of the traditional output stage circuit 001, the bootstrap capacitor needs the voltage drop on the resistor to maintain continuous charging, and there is a quiescent current on the resistor. However, the resistor is located in the bootstrap acceleration loop. If the resistance is increased to reduce the quiescent current, the pull-up speed will be reduced. Therefore, the traditional output stage circuit 001 faces a severe compromise problem between speed and power consumption. In contrast, in the low-power output stage circuit 001 provided by the present invention, the two bootstrap capacitors utilize pre-charge input pulses to alternately charge and discharge intermittently, that is, they are only charged when the bootstrap acceleration circuit is pulled up, and do not need to be charged at other times. Therefore, there is no need for a continuous quiescent current to generate a voltage drop on the resistor, and the static power consumption of the circuit is greatly reduced.

[0093] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application.

Claims

1. A high-side drive circuit for a fully integrated gallium nitride half-bridge power chip, characterized in that: include: Input stage circuit, anti-negative voltage level shift circuit, low power output stage circuit; The input stage circuit inputs the overall input signal V IN , and filter; The anti-negative voltage level shift circuit includes a pulse generating circuit, an anti-negative voltage level shift branch, an output stage control signal generating circuit, and a latch; The pulse generating circuit processes the input signal after filtering by the input stage circuit to generate two narrow pulse signals, which correspond to the rising edge and falling edge of the input signal respectively; The input signals of the anti-negative voltage level shift branch are two narrow pulse signals generated by the pulse generating circuit, and two processed narrow pulse signals are generated and output to the output stage control signal generating circuit respectively; The input signals of the output stage control signal generating circuit are respectively the two narrow pulse signals output by the anti-negative voltage level shifting branch, the signals are processed and delayed respectively, and two narrow pulse signals are output respectively, the two signals before delay are output respectively to the low-power output stage circuit, and the two signals after delay are output respectively to the latch; The latch is used to restore the input narrow pulse signal to a level signal; The input signal of the low-power output stage circuit is the output signal of the latch and the two narrow pulse signals output by the output stage control signal generating circuit, and the output signal is the overall output signal V OUT , used to improve the output driving capability of the overall circuit.

2. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 1, characterized in that: The anti-negative voltage level shifting branch included in the anti-negative voltage level shifting circuit specifically includes a first anti-V SW Negative voltage level shift branch, second anti-V SW Negative voltage level shift branch; the output stage control signal generating circuit included in the anti-negative voltage level shift circuit specifically includes a first output stage control signal generating circuit and a second output stage control signal generating circuit; The first anti-V SW The input signal of the negative voltage level shift branch is the narrow pulse signal generated by the pulse generating circuit, and the output signal is connected to the first output stage control signal generating circuit, which is used to convert the level of the input narrow pulse signal from the low voltage domain to the high voltage domain and generate a negative voltage level shift signal at V SW Ensure correct signal transmission under negative pressure; The second anti-V SW The input signal of the negative voltage level shift branch is the narrow pulse signal generated by the pulse generating circuit, and the output signal is connected to the second output stage control signal generating circuit, which is used to convert the level of the input narrow pulse signal from the low voltage domain to the high voltage domain and generate a negative voltage level shift signal at V SW Ensure correct signal transmission under negative pressure; The input signal of the first output stage control signal generating circuit is the first anti-V SW The output signal of the negative voltage level shift branch is used to convert the first anti-V SW The narrow pulse signal output by the negative voltage level shift branch is shaped, and a non-AND logic process is performed at the same time, and then a delay is performed, and the signal before the delay is output to the low-power output stage circuit, and the signal after the delay is output to the latch; The input signal of the second output stage control signal generating circuit is the second anti-V SW The output signal of the negative voltage level shift branch is used to convert the second anti-V SW The narrow pulse signal output by the negative voltage level shift branch is shaped, and is subjected to a NAND logic process, and then delayed. The signal before the delay is output to the low-power output stage circuit, and the signal after the delay is output to the latch.

3. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The first anti-V SW The negative voltage level shift branch includes: high voltage NMOS tube M HVE1 , high voltage NMOS tube M HVE3 、NMOS tube M E25 , capacitor C3, resistor R3, resistor R5, first inverter INV1; The first anti-V SW The connection relationship of the negative voltage level shift branch is: high voltage NMOS tube M HVE1 The gate of the NMOS tube M is connected to the ground signal GND of the low-voltage domain power rail. E25 The drain of the high-voltage NMOS tube M HVE1 The source of the NMOS tube M is connected E25 The gate of NMOS tube M E25 The source of the capacitor C3 is connected to one end of the capacitor C3, and the other end of the capacitor C3 is connected to the output end of the first inverter INV1. HVE1 The drain of the resistor R5 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the power signal V DDH , high voltage NMOS tube M HVE3 The gate is connected to the input end of the first inverter INV1, and the input end of the first inverter INV1 is connected to the output end of the pulse generating circuit; High voltage NMOS tube M HVE3 The source of the low-voltage domain power rail is connected to the ground signal GND, and the high-voltage NMOS tube M HVE3 The drain of the resistor R3 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the power supply signal V DDH .

4. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The second anti-V SW The negative voltage level shift branch includes: high voltage NMOS tube M HVE2 , high voltage NMOS tube M HVE4 、NMOS tube M E26 , capacitor C4, resistor R4, resistor R6, second inverter INV2; The second anti-V SW The connection relationship of the negative voltage level shift branch is: high voltage NMOS tube M HVE2 The gate of the NMOS tube M is connected to the ground signal GND of the low-voltage domain power rail. E26 The drain of the high-voltage NMOS tube M HVE2 The source of the NMOS tube M is connected E26 The gate of NMOS tube M E26 The source of the capacitor C4 is connected to one end of the capacitor C4, and the other end of the capacitor C4 is connected to the output end of the second inverter INV2. The high-voltage NMOS tube M HVE2 The drain of the resistor R6 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply signal V DDH , high voltage NMOS tube M HVE4 The gate is connected to the input end of the second inverter INV2, and the input end of the second inverter INV2 is connected to the output end of the pulse generating circuit; High voltage NMOS tube M HVE4 The source of the low-voltage domain power rail is connected to the ground signal GND, and the high-voltage NMOS tube M HVE4 The drain of is connected to one end of resistor R4, and the other end of resistor R4 is connected to the power signal V DDH .

5. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The first output stage control signal generating circuit includes: an NMOS transistor M E9 、NMOS tube M E10 、NMOS tube M E11 、NMOS tube M E12 、NMOS tube M E13 、NMOS tube M E14 、NMOS tube M E15 、NMOS tube M E16 , capacitor C5, resistor R7, resistor R9, first clamping circuit, second clamping circuit; The connection relationship of the first output stage control signal generating circuit is: NMOS transistor M E9 The gate of the first resistor is connected to V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE3 The drain of NMOS tube M E11 The gate of NMOS tube M E13 The gate of the first clamp circuit and one end of the first clamp circuit are connected, and the other end of the first clamp circuit is connected to the ground signal V SW , NMOS tube M E9 The source of the NMOS tube M is connected E10 The drain of NMOS tube M E9 The drain of the NMOS tube M E15 The gate of the resistor R7 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the NMOS tube M E16 The drain of NMOS tube M E10 The gate of the first resistor is connected to V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE1 The drain of NMOS tube M E12 The gate of NMOS tube M E14 The gate and one end of the second clamp circuit, the other end of the second clamp circuit is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E10 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E10 The drain of the NMOS tube M E9 The source of NMOS tube M E11 The drain of the NMOS tube M E15 The source of NMOS tube M E11 The source of the NMOS tube M is connected E12 The drain of NMOS tube M E12 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E13 The drain of the latch is connected to the S port and one end of the resistor R9, and the other end of the resistor R9 is connected to the NMOS tube M E11 The drain of the capacitor C5 and one end of the capacitor C5 are connected to the NMOS tube M E16 The drain of NMOS tube M E13 The source of the NMOS tube M is connected E14 The drain of NMOS tube M E14 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E15 The gate of the NMOS tube M is connected E9 The drain of NMOS tube M E15 The source of the NMOS tube M is connected E11 The drain of NMOS tube M E15 The drain of the NMOS tube M E16 The gate and high voltage domain power rail power supply signal V DDH , NMOS tube M E16 The source of the high voltage domain power rail is connected to the power signal V DDH .

6. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The second output stage control signal generating circuit includes: an NMOS transistor M E17 、NMOS tube M E18 、NMOS tube M E19 、NMOS tube M E20 、NMOS tube M E21 、NMOS tube M E22 、NMOS tube M E23 、NMOS tube M E24 , capacitor C6, resistor R8, resistor R 10 , a first clamping circuit, a second clamping circuit; The connection relationship of the second output stage control signal generating circuit is: NMOS transistor M E21 The gate of the second resistor V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE4 The drain of NMOS tube M E19 The gate of NMOS tube M E17 The gate of the third clamp circuit and one end of the third clamp circuit are connected to the ground signal V of the high voltage domain power rail. SW , NMOS tube M E21 The source of the NMOS tube M is connected E22 The drain of NMOS tube M E21 The drain of the NMOS tube M E24 The gate of the resistor R8 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the NMOS tube M E23 The drain of NMOS tube M E22 The gate of the second resistor V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE2 The drain of NMOS tube M E20 The gate of NMOS tube M E18 The gate of the fourth clamp circuit and one end of the fourth clamp circuit, the other end of the fourth clamp circuit is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E22 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E22 The drain of the NMOS tube M E21 The source of NMOS tube M E19 The drain of the NMOS tube M E24 The source of NMOS tube M E19 The source of the NMOS tube M is connected E20 The drain of NMOS tube M E20 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E17 The drain of the latch is connected to the R port and the resistor R 10 One end of the resistor R 10 The other end is connected to NMOS tube M E19 The drain of the capacitor C6 and one end of the capacitor C6 are connected to the NMOS tube M E23 The drain of NMOS tube M E17 The source of the NMOS tube M is connected E18 The drain of NMOS tube M E18 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E24 The gate of the NMOS tube M is connected E21 The drain of NMOS tube M E24 The source of the NMOS tube M is connected E19 The drain of NMOS tube M E24 The drain of the NMOS tube M E23 The gate and high voltage domain power rail power supply signal V DDH , NMOS tube M E23 The source of the high voltage domain power rail is connected to the power signal V DDH .

7. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The low-power output stage circuit includes a first-stage low-power inverter circuit and a second-stage low-power inverter circuit with the same structure; wherein the first-stage low-power inverter circuit includes: an NMOS transistor M E1 、NMOS tube M E2 、NMOS tube M E3 、NMOS tube M E4 , capacitor C1, resistor R1; the second-stage low-power inverter circuit includes: NMOS tube M E5 、NMOS tube M E6 、NMOS tube M E7 、NMOS tube M E8 , capacitor C2, resistor R2; The connection relationship of the low power output stage circuit is: NMOS tube M E1 The gate of the latch is connected to the Q port and the NMOS tube M E2 The gate of NMOS tube M E1 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E1 The drain of the NMOS tube M E3 The gate of the resistor R1 and one end of the resistor R1 are connected to the NMOS tube M E4 The drain of NMOS tube M E2 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E2 The drain of the NMOS tube M E3 The source of NMOS tube M E5 The gate of the NMOS tube M is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the NMOS tube M E4 The drain of NMOS tube M E3 The gate of the NMOS tube M is connected E1 The drain of NMOS tube M E3 The drain of the high voltage domain power rail is connected to the power signal V DDH , NMOS tube M E4 The gate of the NMOS transistor M is connected to the second output stage control signal generating circuit. E19 The drain of NMOS tube M E4 The source is connected to the power supply signal V DDH , NMOS tube M E5 The gate of the NMOS tube M is connected E6 The gate and NMOS tube M E2 The drain of NMOS tube M E5 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E5 The drain of the NMOS tube M E7 The gate of the resistor R2 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the NMOS tube M E8 The drain of NMOS tube M E6 The source is connected to the ground signal V of the high voltage domain power rail SW , NMOS tube M E6 The drain of the NMOS tube M E7 The source of the overall output signal port V OUT and one end of capacitor C2, and the other end of capacitor C2 is connected to NMOS tube M E8 The drain of NMOS tube M E7 The gate of the NMOS tube M is connected E5 The drain of NMOS tube M E7 The drain of the high voltage domain power rail is connected to the power signal V DDH , NMOS tube M E8 The gate of the NMOS transistor M is connected to the first output stage control signal generating circuit. E11 The drain of NMOS tube M E8 The source of the power supply signal V is connected to the high voltage domain power rail DDH .

8. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The input of the pulse generating circuit is the output signal of the input stage circuit, and the output is two narrow pulse signals. The connection relationship is: the signal input port of the pulse generating circuit is connected to the output end of the input stage circuit, and the input end of the input stage circuit is connected to the overall circuit input signal V IN , the pulse signal V generated by the pulse generating circuit RP+ Access the first anti-V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE3 The gate of the inverter and the input of the inverter INV1, the pulse generating circuit generates a pulse signal V FP+ Connect to the second anti-V SW High-voltage NMOS tube M in the negative voltage level shift branch HVE4 The gate of the inverter and the input of INV2, the power port is connected to the power signal V of the low-voltage domain power rail DDL , the ground port is connected to the ground signal GND of the low-voltage domain power rail.

9. The high-side drive circuit for a GaN fully integrated half-bridge power chip according to claim 2, characterized in that: The R port and S port of the latch are input ports, the Q port is the output port, and the S port is connected to the NMOS transistor M in the first output stage control signal generating circuit. E13 The drain of the R port is connected to the NMOS tube M in the second output stage control signal generating circuit. E17 The drain of the Q port is connected to the NMOS tube M in the low power output stage circuit. E1 The gate of the latch is connected to the power supply signal V of the high-voltage domain power rail. DDH , the ground port of the latch is connected to the ground signal V of the high voltage domain power rail SW .

10. The high-side drive circuit for a gallium nitride fully integrated half-bridge power chip according to claim 1, characterized in that: The NMOS tubes, resistors, and capacitors that make up the circuit are all devices based on gallium nitride technology.

Images