Resonant gate drive circuit with reconfigurable dead time control

Abstract

The invention discloses a resonant gate drive circuit with reconfigurable dead time control, which belongs to the field of integrated circuits and comprises a reconfigurable dead time control circuit and a resonant drive circuit. The reconfigurable dead time control circuit is formed by cascading a pulse wave generation circuit, a shift register circuit and a logic operation circuit in three stages, and the input end of the reconfigurable dead time control circuit is connected with an external control signal; the resonant driving circuit is composed of six transistors, two inductors and a capacitor, and the output end of the resonant driving circuit is connected with a driven circuit. The pulse wave generating circuit comprises six sets of D triggers, output signals form six independent control signals through the shift register circuit and the logic operation circuit, six transistors of the resonance driving circuit are directly driven to be in the on-off state, resonance is generated through an inductor and a driven circuit load capacitor, and driving energy recovery is achieved. And variable-frequency and variable-duty-ratio output is realized by changing partial pulse duration of the input signal. The circuit provided by the invention can flexibly regulate and control key parameters by only depending on an external control signal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a resonant gate drive circuit with reconfigurable dead time control. Background Art

[0002] Driven by the continued demand for miniaturization in portable devices, achieving high efficiency and miniaturization of switching power supplies has become a key development direction in this technology. Increasing the switching frequency is an effective way to reduce the size and weight of switching power supplies. However, this also leads to a significant increase in power switch losses, especially gate drive losses.

[0003] Traditional gate drive losses are typically proportional to the switching frequency. Under high switching frequency conditions, higher drive losses become one of the main bottlenecks that restrict power converters from further increasing their frequency and power density. Specifically, in a typical peripheral circuit configuration, a half-bridge driver chip can only drive a pair of half-bridge power transistors. Its drive losses increase linearly with frequency, severely limiting further increases in the converter's switching frequency. In addition, some converter topologies require a large number of power MOS transistors. If the traditional half-bridge driver chip solution is used, a series of problems will result, including a large number of required driver chips, a sharp increase in drive losses, an extremely complex auxiliary power supply structure, and an excessively large space occupied by the drive system, thereby reducing the overall power density of the system.

[0004] To effectively reduce system drive losses, high-frequency resonant gate drive technology has emerged. This technology utilizes the principle of LC resonance to recover energy from the gate capacitor, significantly reducing drive losses and demonstrating clear advantages in high-frequency applications. In recent years, resonant gate drive circuits with various structures have been proposed. However, existing solutions generally have the following drawbacks: excessive circuit footprint, low drive energy recovery efficiency, complex control signals, insufficient drive capability, difficulty in flexibly adjusting duty cycle and dead time, and the tendency for multi-channel signal control to produce timing deviations. These shortcomings limit the widespread application of resonant gate drive technology in high-efficiency, high-frequency, and high-power density power supply systems. Summary of the Invention

[0005] Technical problem: In response to the problems of existing resonant gate drive circuits, such as large footprint, low energy recovery efficiency, poor flexibility in duty cycle and dead time control, and easy timing deviation in multi-channel signal control, the present invention proposes a resonant gate drive circuit with reconfigurable dead time control. It only relies on one external control signal to flexibly control key parameters, greatly reducing the PAD resource occupancy and control logic complexity during drive circuit integration, eliminating external dead zone ICs and complex decoupling algorithms, and eliminating the risk of duty cycle drift and soft switching failure caused by multi-signal synchronization timing deviations, thereby achieving higher drive energy recovery efficiency and flexible and adjustable duty cycle and dead time of the output signal.

[0006] Technical solution: The present invention adopts the following technical solution: a resonant gate drive circuit with reconfigurable dead time control, comprising: a reconfigurable dead time control circuit and a resonant drive circuit.

[0007] Among them, the reconfigurable dead time control circuit includes: a pulse wave generation circuit, a shift register circuit and a logic operation circuit; the resonant drive circuit is composed of six metal oxide semiconductor field effect transistors (MOSFETs) S1, S2, S3, S4, S5, and S6, two inductors L1 and L2, and a capacitor Ce, and the output terminals Vgsr1 and Vgsr2 are connected to the driven circuit.

[0008] The pulse wave generating circuit includes six groups of D flip-flops DFF1 to DFF6, which output signals Q1 to Q6 to the shift register circuit; the shift register circuit includes ten groups of cascaded D flip-flops DFF7 to DFF16 and NAND gate units. The output signals Q7 to Q16 are input into the logic operation circuit after logical operation through the NAND gate units, forming six independent control signals G1 to G6, which are output to the resonant drive circuit to directly drive the switching state of transistors S1 to S6.

[0009] The resonant drive circuit generates resonance through inductors L1 and L2 and the driven circuit load capacitors Cgsr1 and Cgsr2 to achieve drive energy recovery, and achieves variable frequency and duty cycle output by changing the duration of some pulses of the input signal PWM1.

[0010] Preferably, the reconfigurable dead time control circuit is composed of a three-stage cascade of a pulse wave generating circuit, a shift register circuit and a logic operation circuit.

[0011] The input control signal PWM1 is connected in parallel to the data terminals (D terminals) of the six D-type flip-flops DFF1 to DFF6 of the pulse wave generating circuit. The output signals Q1 to Q6 are fed back to the reset terminal (Reset) of this stage through the inverter delay chain, forming a self-limiting pulse sequence.

[0012] In the shift register circuit, the output signals Q1~Q6 of the previous-stage pulse wave generating circuit are connected to the clock terminal (CLK) of the current-stage D-type flip-flops DFF7~DFF16. The output signals Q7~Q16 are sent to the data terminal (D terminal) of the next D-type flip-flop after logical operation through the NAND gate unit, realizing a signal delay with adjustable phase step Δt.

[0013] The logic operation circuit receives the output signals Q7~Q16 of the shift register circuit, synthesizes six independent control signals G1~G6 through combinational logic, and directly drives the gate timing of transistors S1~S6 in the resonant drive circuit.

[0014] Preferably, the resonant drive circuit includes a power switch network, a resonant energy recovery network and a drive interface unit.

[0015] Transistors S1 and S2 are PMOS, and transistors S3, S4, S5, and S6 are NMOS. The connection definitions of each transistor are as follows: The gate of the transistor S1 is connected to the control signal G1 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to the inductor L1, the drain of the transistor S3 and the output terminal Vgsr1; The gate of the transistor S2 is connected to the control signal G2 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to the inductor L2, the drain of the transistor S4 and the output terminal Vgsr2; The gates of transistors S3 and S4 are connected to the control signals G3 and G4 output by the logic operation circuit respectively, and the sources are grounded; The gates of transistors S5 and S6 are connected to control signals G5 and G6 output by the logic operation circuit respectively, the drains are connected to inductors L1 and L2 respectively, the sources are connected to the same-end node of capacitor Ce, and the other end of Ce is connected to ground GND.

[0016] In the driving interface unit, one end of the load capacitors Cgsr1 and Cgsr2 is connected to the two output terminals Vgsr1 and Vgsr2 of the resonant driving circuit respectively, and the other end is grounded GND.

[0017] Preferably, the input end of the reconfigurable dead time control circuit is connected to the control signal PWM1 generated by the DSP chip to generate drive signals G1~G6, control the switching state of transistors S1~S6, and realize resonance between inductors L1 and L2 and gate capacitances Cgsr1 and Cgsr2 of the driven circuit, thereby realizing the recovery of driving energy, and can realize variable frequency and duty cycle output by changing the partial pulse length of the input signal PWM1.

[0018] Depending on the input control signals G1 to G6, the resonant gate drive circuit operates in different operating modes. The resonant effect between inductors L1 and L2 and the driven circuit load capacitors Cgsr1 and Cgsr2 is used to construct an energy recovery path to achieve gate drive energy recovery for the main power topology.

[0019] Preferably, there are eight different working modes, and a single cycle of the input signal PWM1 is correspondingly divided into timing phases T1~T8, among which T4 and T8 directly regulate the dead time between the output signals of the output terminals Vgsr1 and Vgsr2, and T2 and T6 independently control the duty cycle of the output signals of the output terminals Vgsr1 and Vgsr2; by independently adjusting the phase difference through DSP, the required dead time and duty cycle can be flexibly set, thereby realizing the collaborative reconstruction of dual parameters by a single PWM1 input.

[0020] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. The resonant gate drive circuit of the present invention relies on only one external control signal to flexibly adjust key parameters, reducing the PAD area and drive signal timing error by 83% during integration, eliminating the need for an external dead zone IC and complex decoupling algorithm, and significantly reducing drive losses at high frequencies.

[0021] 2. The single-signal control circuit of the present invention can eliminate the risk of duty cycle drift and soft switching failure caused by multi-signal synchronization timing deviation, achieve higher drive energy recovery efficiency, significantly reduce drive loss, and the duty cycle and dead time of the output signal are flexibly adjustable.

[0022] 3. The circuit control of the present invention is simple, and can realize soft switching and dual-channel output of MOS transistors, drive a large number of transistors. The devices used are small in size, easy to integrate, and have low power consumption, saving cost and space, and having a wide range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a topological diagram of a converter circuit used in the present invention; Figure 2 This is a structural diagram of the resonant gate drive circuit of the present invention; Figure 3 This is a reconfigurable dead zone control circuit diagram of the present invention; Figure 4 This is a resonant drive circuit diagram of the present invention; Figure 5 It is a control signal module diagram of the present invention; Figure 6 is a key waveform timing diagram of an embodiment of the present invention; Figure 7 1 is a schematic diagram of a current loop in different modes according to an embodiment of the present invention; Figure 8 This is a key waveform timing diagram after dead time reconstruction according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the application are further described in detail below with reference to the accompanying drawings. The described embodiments are only part of the embodiments involved in the present invention. All non-innovative embodiments based on this embodiment by other researchers in the field are within the scope of protection of the present invention.

[0025] In a preferred embodiment of the present invention, Figure 1 As shown, the resonant gate drive circuit with reconfigurable dead time control is suitable for driving the secondary-side synchronous rectification transistors SR1, SR2, SR3 and SR4 in the LLC-DCX converter.

[0026] The gates of the transistors SR1 and SR3 are connected to the output terminal Vgsr1 of the resonant gate drive circuit, and the gates of the transistors SR2 and SR4 are connected to the output terminal Vgsr2 of the resonant gate drive circuit.

[0027] The resonant gate drive circuit of this embodiment is as follows: Figure 2 As shown, it consists of a reconfigurable dead-time control circuit and a resonant drive circuit. The input signal of the reconfigurable dead-time control circuit is the PWM1 signal, and the output signals are G1 to G6. The input signal of the resonant drive circuit is connected to G1-G6, and the output end is connected to the driven circuit.

[0028] Specifically, the dead time control circuit can be reconfigured, such as Figure 3 As shown, it is composed of three cascade stages: a pulse wave generating circuit, a shift register circuit and a logic operation circuit.

[0029] The pulse wave generation circuit uses six groups of homogeneous D-type flip-flop units (DFF1-DFF6). The D terminals of the six groups of D-type flip-flops are connected to the PWM1 signal. The output signals Q1-Q6 are fed back to the Reset terminal through the inverter delay chain to generate self-limiting pulses with programmable pulse width.

[0030] The shift register circuit consists of ten sets of cascaded D flip-flops (DFF7-DFF16) and NAND gate units. The CLK terminal of the cascade unit is connected to Q1-Q6, and the outputs Q7-Q16 are fed into the D terminal of the next stage through NAND gate logic to achieve a delay with adjustable phase step Δt.

[0031] The logic operation circuit decodes the combinational logic based on Q7 to Q16 and outputs six gate drive signals G1 to G6 to the power tubes S1 to S6 of the resonant gate drive circuit.

[0032] The resonant drive circuit of this embodiment is as follows: Figure 4 As shown in the figure, it includes three parts: power switch network, resonant energy recovery network and drive interface.

[0033] In the power switch network, the gates of PMOS transistors S1 and S2 are connected to control signals G1 and G2, respectively, and their sources are connected to power supply VCC. The gates of NMOS transistors S3 and S4 are connected to G3 and G4, respectively, and their sources are grounded. The drains of S1 and S3, along with inductor L1, are connected to the first output terminal Vgsr1. The drains of S2 and S4, along with inductor L2, are connected to the second output terminal Vgsr2.

[0034] In the resonant energy recovery network, the gates of MOS transistors S5 and S6 are connected to G5 and G6, the drains are connected to the non-output ends of L1 and L2 respectively, and the sources are connected to the resonant capacitor Ce through the node N1. The other end of Ce is grounded.

[0035] In the driver interface, Figure 4 The drive circuit is also included, which can be equivalent to load capacitors Cgsr1 and Cgsr2. One end of the equivalent load capacitors Cgsr1 and Cgsr2 is connected to two output terminals Vgsr1 and Vgsr2 of the resonant gate drive circuit, respectively, and the other ends of both are grounded GND.

[0036] Furthermore, the resonant gate drive circuit control signal input module of this embodiment is as follows: Figure 5 As shown, the input module can optionally use a digital signal processor (DSP) chip to generate a pulse-width modulation (PWM) control signal. The PWM1 signal period is set to the target high-frequency operating frequency (typically 1 MHz to 2 MHz) and configured with an appropriate amplitude and duty cycle. A single PWM1 cycle is divided into timing phases T1 to T8. Phases T4 and T8 directly control the dead time between the output signals Vgsr1 and Vgsr2, while phases T2 and T6 independently control their duty cycles. Modifying the phase parameters via the DSP allows for collaborative reconstruction of the dual target values ​​without the need for additional external control pins.

[0037] like Figure 6 As shown, this embodiment controls the on / off state of transistors S1-S6 by controlling the logic state of input signal PWM1. The time period between t3 and t4 is dead time TD1, and the time period between t7 and t8 is dead time TD2.

[0038] Inductor current i L1 、i L2 are the currents flowing through the inductors L1 and L2 respectively, and the driving voltage Vgsr is the voltage of the two output terminals Vgsr1 and Vgsr2 of the resonant driving circuit. By accurately setting the logic state of the input signal PWM1, the output signals Vgsr1, Vgsr2, and the inductor current i L1 、i L2precise control.

[0039] As a preferred solution, the dual-output non-isolated resonant gate drive circuit proposed in this embodiment can be divided into eight modes in one working cycle, such as Figure 7 As shown in the figure, the red part is the current path under this mode, and the arrow indicates the direction of the current.

[0040] Combine Figure 6 and Figure 7 , the circuit operation under eight modes can be specifically analyzed: like Figure 7 As shown in (a), working mode 1 (t0-t1): at time t0, transistor S5 is turned on, inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, resonates and charges the load capacitor, Vgsr1 voltage gradually rises, and inductor current i L1 It is sinusoidal and flows into the load capacitor Cgsr1.

[0041] During this period, the inductor current i L1 It can be described by the following formula: ; in, Indicates the Vgsr1 voltage value, Indicates the Cgsr1 capacitance value.

[0042] like Figure 7 As shown in (b), working mode 2 (t1-t2): At t1, the voltage of Vgsr1 rises to Vcc, that is, the source-drain voltage difference of transistor S1 is zero, and the resonant current i L1 =0. At this point, transistor S1 is turned on and S5 is turned off, achieving zero voltage turn-on of S1 and zero current turn-off of S5. Afterwards, the voltage at the output terminal Vgsr1 is clamped to Vcc, and no current flows through inductors L1 and L2.

[0043] like Figure 7 As shown in (c), working mode 3 (t2-t3): At time t2, transistor S1 is turned off, S5 is turned on, inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, resonates and discharges the load capacitor, and the gate drive energy is recovered to capacitor Ce. The voltage at the output terminal Vgsr1 gradually decreases, and the inductor current i L1 It is sinusoidal and the current flow direction is opposite to that in working mode 1.

[0044] like Figure 7 As shown in (d), working mode 4 (t3-t4): at time t3, the voltage of the output terminal Vgsr1 drops to 0, that is, the source-drain voltage difference of the transistor S3 is zero, and the resonant current i L1=0. At this point, transistor S3 is turned on and S5 is turned off, achieving zero voltage turn-on of S3 and zero current turn-off of S5. Afterwards, the voltages at the output terminals Vgsr1 and Vgsr2 are both zero, and no current flows through inductors L1 and L2. This period is the dead time TD1.

[0045] like Figure 7 As shown in (e), working mode 5 (t4-t5): at time t4, transistor S6 is turned on, inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, resonates and charges the load capacitor, the output terminal Vgsr2 voltage gradually rises, and the inductor current i L2 It is sinusoidal and flows into the load capacitor Cgsr2.

[0046] During this period, the inductor current i L2 It can be described by the following formula: ; in, Indicates the Vgsr2 voltage value, Indicates the capacitance value of Cgsr2.

[0047] like Figure 7 As shown in (f), working mode 6 (t5-t6): at t5, the voltage of the output terminal Vgsr2 rises to Vcc, that is, the source-drain voltage difference of the transistor S2 is zero, and the resonant current i L2 =0. At this point, transistor S2 is turned on and S6 is turned off, achieving zero voltage turn-on of S2 and zero current turn-off of S6. Afterwards, the voltage at the output terminal Vgsr2 is clamped to Vcc, and no current flows through inductors L1 and L2.

[0048] like Figure 7 As shown in (g), working mode 7 (t6-t7): at time t6, transistor S2 is turned off, S6 is turned on, inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, resonates and discharges the load capacitor, gate drive energy is recovered to capacitor Ce, the output terminal Vgsr2 voltage gradually decreases, and the inductor current i L2 It is sinusoidal and the current flow direction is opposite to that in working mode 5.

[0049] like Figure 7 As shown in (h), working mode 8 (t7-t8): at t7, the voltage of the output terminal Vgsr2 drops to 0, that is, the source-drain voltage difference of the transistor S4 is zero, and the resonant current i L2 =0. At this point, transistor S4 is turned on and S6 is turned off, achieving zero voltage turn-on of S4 and zero current turn-off of S6. Afterwards, the voltages at the output terminals Vgsr1 and Vgsr2 are both zero, and no current flows through inductors L1 and L2. This period is the dead time TD2.

[0050] Furthermore, if Figure 8 As shown, the dual-output non-isolated resonant gate drive circuit with reconfigurable dead zone proposed by the present invention can achieve reconfiguration of the dead zone time by accurately adjusting the input signal PWM1 timing control.

[0051] As a preferred solution, in this embodiment, it is manifested as follows: Increase the PWM1 signal T4 time period to increase the dead time DT1; Reduce the PWM1 signal T8 time period to reduce the dead time DT2.

[0052] Therefore, by adjusting the timing state of the single input signal PWM1, the dead times DT1 and DT2 can be independently reconstructed.

[0053] In summary, the dual-output non-isolated resonant gate drive circuit with reconfigurable dead zone proposed in this embodiment controls the states of the MOSFET switches (S1-S6) by precisely regulating the timing state of the input signal PWM1, thereby achieving resonance between the inductors L1 and L2 and the equivalent gate capacitances Cgsr1 and Cgsr1 of the driven circuit, efficiently recovering gate drive energy, reducing drive losses by 85%, and improving the power supply system efficiency by more than 1 percentage point.

[0054] At the same time, the circuit structure is streamlined and easy to control. It can not only flexibly adjust the duty cycle, but also has the ability to independently and accurately adjust the dead time DT1 and DT2, expanding the application scenarios. In addition, the drive system only requires one external control signal, which saves 83% of the PAD area compared to traditional multi-channel drive control solutions and eliminates multi-channel signal adaptation deviations. Based on the above characteristics, the circuit of the present invention can be widely used in advanced power supply systems such as AI servers and data center power supplies.

[0055] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A resonant gate drive circuit with reconfigurable dead time control, characterized in that: include: Reconfigurable dead time control circuit and resonant drive circuit; The reconfigurable dead time control circuit is composed of a three-stage cascade of a pulse wave generating circuit, a shift register circuit and a logic operation circuit, and its input end is connected to the control signal PWM1 generated by the DSP chip; The resonant driving circuit is composed of six metal oxide semiconductor field effect transistors S1 to S6, two inductors L1 and L2, and a capacitor Ce, and the output terminals Vgsr1 and Vgsr2 are connected to the driven circuit; The pulse wave generating circuit includes six groups of isomorphic D flip-flops DFF1 to DFF6, which output signals Q1 to Q6 to a shift register circuit; the shift register circuit includes ten groups of cascaded D flip-flops DFF7 to DFF16 and NAND gate units. The output signals Q7 to Q16 are input to a logic operation circuit after undergoing a logic operation by the NAND gate units, forming six independent control signals G1 to G6, which are output to a resonant drive circuit to directly drive the on / off states of transistors S1 to S6. The resonant drive circuit generates resonance through inductors L1 and L2 and the driven circuit load capacitors Cgsr1 and Cgsr2 to achieve drive energy recovery, and achieves variable frequency and duty cycle output by changing the duration of some pulses of the input signal PWM1.

2. The resonant gate drive circuit with reconfigurable dead time control according to claim 1, wherein: The resonant drive circuit includes a power switch network, a resonant energy recovery network and a drive interface unit. The transistors S1 and S2 are PMOS, and the transistors S3, S4, S5 and S6 are NMOS.

3. The resonant gate drive circuit with reconfigurable dead time control according to claim 2, wherein: In the power switch network, the gate of the transistor S1 is connected to the control signal G1 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to the inductor L1, the drain of the transistor S3 and the output terminal Vgsr1; The gate of the transistor S2 is connected to the control signal G2 output by the logic operation circuit, the source is connected to VCC, and the drain is connected to the inductor L2, the drain of the transistor S4 and the output terminal Vgsr2; The gates of the transistors S3 and S4 are connected to the control signals G3 and G4 output by the logic operation circuit respectively, and the sources are grounded.

4. The resonant gate drive circuit with reconfigurable dead time control according to claim 2, wherein: In the resonant energy recovery network, the gates of transistors S5 and S6 are respectively connected to the control signals G5 and G6 output by the logic operation circuit, the drains are respectively connected to the inductors L1 and L2, the sources are commonly connected to the same-end node of capacitor Ce, and the other end of capacitor Ce is connected to ground GND.

5. The resonant gate drive circuit with reconfigurable dead time control according to claim 2, wherein: In the driving interface unit, one end of the load capacitors Cgsr1 and Cgsr2 is connected to the two output terminals Vgsr1 and Vgsr2 of the resonant driving circuit respectively, and the other end is grounded GND.

6. The resonant gate drive circuit with reconfigurable dead time control according to claim 1, wherein: In the pulse wave generating circuit, the input control signal PWM1 is connected in parallel to the data terminals of six groups of D flip-flops DFF1 to DFF6, and the output signals Q1 to Q6 are respectively fed back to the reset terminals of the current stage through the inverter delay chain to form a self-limiting pulse sequence.

7. The resonant gate drive circuit with reconfigurable dead time control according to claim 6, wherein: In the shift register circuit, the output signals Q1 to Q6 of the previous stage pulse wave generating circuit are connected to the clock terminal of the current stage D flip-flops DFF7 to DFF16. The output signals Q7 to Q16 are sent to the data terminal of the next D flip-flop after a logic operation by the NAND gate unit, thereby realizing a signal delay with adjustable phase step Δt. The logic operation circuit receives the output signals Q7-Q16 of the shift register circuit, synthesizes six independent control signals G1-G6 through combinational logic, and outputs them to directly drive the gate timing of transistors S1-S6 in the resonant drive circuit.

8. The resonant gate drive circuit with reconfigurable dead time control according to claim 7, wherein: According to the different input control signals G1~G6, the resonant gate drive circuit operates in different operating modes, and utilizes the resonance between the inductors L1 and L2 and the driven circuit load capacitors Cgsr1 and Cgsr2 to construct an energy recovery path to achieve the recovery of the main power topology gate drive energy.

9. The resonant gate drive circuit with reconfigurable dead time control according to claim 8, wherein: The resonant gate drive circuit has eight operating modes, and the operating conditions of the resonant gate drive circuit in each operating mode are as follows: Working mode 1: At time t0, transistor S5 is turned on, inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, and resonates and charges load capacitor Cgsr1. The voltage at output terminal Vgsr1 gradually rises, and the current i flowing through inductor L1 L1 It is sinusoidal and flows into the load capacitor Cgsr1; Working mode 2: At time t1, the voltage of the output terminal Vgsr1 rises to the power supply Vcc, the source-drain voltage difference of the transistor S1 is zero, and the current i flowing through the inductor L1 is L1 =0; control transistor S1 to be turned on and transistor S5 to be turned off, the voltage at the output terminal Vgsr1 is clamped to Vcc, and no current flows through inductors L1 and L2; Working mode 3: At time t2, transistor S1 is turned off and transistor S5 is turned on. Inductor L1 resonates with load capacitor Cgsr1 and capacitor Ce, and discharges load capacitor Cgsr1. Gate drive energy is recovered to capacitor Ce. The voltage at output terminal Vgsr1 gradually decreases, and the current i flowing through inductor L1 decreases. L1 It is sinusoidal, and the current flow direction is opposite to that of working mode 1; Working mode 4: At time t3, the voltage of the output terminal Vgsr1 drops to 0, the source-drain voltage difference of the transistor S3 is zero, and the resonant current i L1 =0; control transistor S3 to be turned on and transistor S5 to be turned off, the voltages at the output terminals Vgsr1 and Vgsr2 are both 0, no current flows through the inductor output voltages L1 and L2, and the working period of working mode 4 is the dead time TD1; Working mode 5: At time t4, transistor S6 is turned on, inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, resonates and charges load capacitor Cgsr2, the voltage at output terminal Vgsr2 gradually rises, and the current i flowing through inductor L2 L2 It is sinusoidal and flows into the load capacitor Cgsr2; Working mode 6: At t5, the voltage at the output terminal Vgsr2 rises to Vcc, the source-drain voltage difference of the transistor S2 is zero, and the resonant current i L2 =0; control transistor S2 to be turned on and transistor S6 to be turned off, the voltage at the output terminal Vgsr2 is clamped to Vcc, and no current flows through inductors L1 and L2; Working mode 7: At time t6, transistor S2 is turned off and transistor S6 is turned on. Inductor L2 resonates with load capacitor Cgsr2 and capacitor Ce, and discharges load capacitor Cgsr2. Gate drive energy is recovered to capacitor Ce. The voltage at output terminal Vgsr2 gradually decreases, and the current i flowing through inductor L2 decreases. L2 It is sinusoidal, and the current flow direction is opposite to that of working mode 5; Working mode 8: At time t7, the voltage of the output terminal Vgsr2 drops to 0, the source-drain voltage difference of the transistor S4 is zero, and the resonant current i L2 is 0; the control transistor S4 is turned on and the transistor S6 is turned off, the voltages at the output terminals Vgsr1 and Vgsr2 are both 0, no current flows through the inductors L1 and L2, and the working mode 8 works during the dead time TD2.

10. The resonant gate drive circuit with reconfigurable dead time control according to claim 9, wherein: A single cycle of the input signal PWM1 is divided into timing phases T1 to T8, where T4 and T8 directly regulate the dead time TD1 and TD2 between the output signals of the output terminals Vgsr1 and Vgsr2, and T2 and T6 independently control the duty cycle of the output signals of the output terminals Vgsr1 and Vgsr2. The phase parameters are independently adjusted by DSP to set the required dead time and duty cycle, thereby realizing the collaborative reconstruction of dual parameters of a single PWM1 input.

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