Front-end receiving circuit

Abstract

The invention relates to the technical field of signal processing, in particular to a local circuit of an electronic system or electronic equipment for digital information transmission, and provides a front-end receiving circuit. The circuit comprises a first-stage amplifier and a second-stage amplifier, wherein the first-stage amplifier comprises an input transistor pair, a cross-coupled load arranged on the load side of the input transistor pair and an adjustable resistance-capacitance unit arranged on the bias side of the input transistor pair; the second-stage amplifier is used for carrying out first-time swing amplification on the output differential signal of the first-stage amplifier under the action of the bias current source, so that the common-mode level of the output differential signal of the first-stage amplifier is increased to the common-mode level of the output differential signal of the second-stage amplifier; and the third-stage amplifier is used for carrying out second-time swing amplification so as to increase the common-mode level of the output differential signal of the second-stage amplifier to the common-mode level of the output differential signal of the third-stage amplifier. Therefore, the high-efficiency front-end receiving circuit capable of overcoming waveform distortion is realized.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, specifically to a local circuit of an electronic system or electronic device for digital information transmission, and more particularly to a front-end receiving circuit. Background Art

[0002] In applications such as data centers, cloud computing, and artificial intelligence, the scale and rate of digital information transmission need to be continuously improved, which places higher demands on the local circuits of electronic systems or electronic devices used for digital information transmission. In addition, with the continuous development of advanced semiconductor processes and the ever-changing requirements of application scenarios, higher design requirements are placed on the local circuits of electronic systems or electronic devices at the receiving end of digital information transmission. For example, the front-end receiving circuit for Double Data Rate Synchronous Dynamic Random Access Memory (DDR SRAM) may need to meet different reference voltages specified by different protocols and receive and send data in the voltage domain specified by the reference voltage. With the evolution of memory technology, higher requirements are placed on low power consumption and high bandwidth. For example, High Bandwidth Memory (HBM) requires minimizing the area of ​​the front-end receiving circuit while increasing the rate to meet the needs of high-performance computing and graphics processing. In addition, front-end receiving circuits must address challenges such as waveform distortion, compatibility between front-end and back-end circuits, and the wide temperature range requirements of automotive applications. In particular, single-ended signals generally face greater waveform distortion challenges than differential signals in high-speed data transmission applications. These challenges, combined with the need to reduce circuit area, lower power consumption, and improve performance, create technical challenges for the design of local circuits in electronic systems or electronic devices used for digital information transmission, specifically for front-end receiving circuits. Existing front-end receiving circuits generally employ current mode logic (CML) and continuous time linear equalization (CTLE) structural designs, but these challenges struggle to simultaneously address the requirements of overcoming waveform distortion, supporting compatibility between front-end and back-end circuits, reducing circuit area, lowering power consumption, and improving performance.

[0003] To this end, the present application provides a front-end receiving circuit that can be applied to electronic systems for digital information transmission or local circuits of electronic devices to address technical challenges in the prior art. Summary of the Invention

[0004] In a first aspect, the present application provides a front-end receiving circuit. The front-end receiving circuit includes: a first-stage amplifier, wherein the first-stage amplifier includes an input transistor pair, a cross-coupling load disposed on the load side of the input transistor pair, and an adjustable resistance and capacitance unit disposed on the bias side of the input transistor pair, the control side of the input transistor pair is used to receive an input single-ended signal and a reference voltage signal, the cross-coupling load is used to convert the input single-ended signal into an output differential signal of the first-stage amplifier and provide duty cycle calibration for the input single-ended signal, and the adjustable resistance and capacitance unit is used to cooperate with the input transistor pair and the cross-coupling load to provide duty cycle calibration for the input single-ended signal. a second-stage amplifier, wherein the second-stage amplifier is used to perform a first swing amplification on the output differential signal of the first-stage amplifier under the action of a bias current source, so as to increase the common-mode level of the output differential signal of the first-stage amplifier to the common-mode level of the output differential signal of the second-stage amplifier; and a third-stage amplifier, wherein the third-stage amplifier is used to perform a second swing amplification on the output differential signal of the second-stage amplifier, so as to increase the common-mode level of the output differential signal of the second-stage amplifier to the common-mode level of the output differential signal of the third-stage amplifier.

[0005] Through the first aspect of the present application, by optimizing the circuit structure design of the first-stage amplifier, the second-stage amplifier, and the third-stage amplifier, the challenges of waveform distortion of single-ended signals are addressed, and the problems of single-to-dual conversion and adaptability of the front-end and back-end circuits are taken into consideration. It is achieved that the output pole position can be adaptively adjusted and the gain boost performance can be improved within a larger bandwidth range according to channel loss, the duty cycle deviation caused by the single-ended input of the high-speed signal is improved, and low-power and low-latency level conversion is provided on the basis of overcoming the waveform distortion of the single-ended signal and providing channel insertion loss compensation, thereby achieving a balanced optimization design in terms of circuit area, circuit power consumption, and circuit performance.

[0006] In a possible implementation manner of the first aspect of the present application, the transistor type of the input transistor pair is determined based on a common-mode level of the input single-ended signal.

[0007] In a possible implementation of the first aspect of the present application, when the common-mode level of the input single-ended signal is lower than a first preset threshold, the transistor type of the input transistor pair is a P-type metal oxide semiconductor, and when the common-mode level of the input single-ended signal is higher than a second preset threshold, the transistor type of the input transistor pair is an N-type metal oxide semiconductor.

[0008] In a possible implementation of the first aspect of the present application, the common-mode level of the reference voltage signal is determined based on the common-mode level of the input single-ended signal, and the common-mode level of the input single-ended signal is determined based on a communication protocol associated with the front-end receiving circuit.

[0009] In a possible implementation of the first aspect of the present application, the given frequency range is determined based on the resistance and capacitance time constant of the adjustable resistance and capacitance unit, the transconductance of the input transistor pair, and the load resistance and load capacitance included in the cross-coupling load, and the given gain is determined based on the resistance and capacitance time constant of the adjustable resistance and capacitance unit and the transconductance of the input transistor pair.

[0010] In a possible implementation of the first aspect of the present application, the given frequency range and the given gain are pre-set, and the adjustment of the adjustable resistance and capacitance unit is used to adaptively adjust the offset of the given frequency range or the offset of the given gain.

[0011] In a possible implementation of the first aspect of the present application, the adjustable resistance and capacitance unit includes a first adjustable resistor and a first adjustable capacitor connected in parallel between the bias sides of the input transistor pair, and the first adjustable resistor and the first adjustable capacitor are respectively connected to the front-end receiving circuit through a switchable switch to selectively provide high-frequency channel loss compensation for the input single-ended signal.

[0012] In a possible implementation of the first aspect of the present application, the adjustable resistance and capacitance unit also includes a second adjustable resistor and a second adjustable capacitor connected in series between the bias sides of the input transistor pair, and the second adjustable resistor and the second adjustable capacitor are connected to the front-end receiving circuit through a switchable switch to selectively provide low-frequency channel loss compensation for the input single-ended signal.

[0013] In a possible implementation of the first aspect of the present application, the first swing amplification is used to adapt the DC operating point of the third-stage amplifier and improve the adaptability of the front-end receiving circuit to different process angle voltage and temperature conditions, and the second swing amplification is used to adapt the DC operating point of the subsequent circuit associated with the front-end receiving circuit.

[0014] In a possible implementation of the first aspect of the present application, the second-stage amplifier includes a fully differential inverting amplifier circuit, which converts the output differential signal of the first-stage amplifier into the output differential signal of the second-stage amplifier under the action of the bias current source, and the current magnitude of the bias current source is determined by simulating the variation range of the common-mode level of the output differential signal of the first-stage amplifier.

[0015] In a possible implementation of the first aspect of the present application, the third-stage amplifier includes an inverting amplifier circuit with a latch structure, and the inverting amplifier circuit with a latch structure is used to convert the output differential signal of the second-stage amplifier into the output differential signal of the third-stage amplifier, and the fully differential inverting amplifier circuit and the inverting amplifier circuit with a latch structure are together used to provide duty cycle calibration for the input single-ended signal.

[0016] In a possible implementation of the first aspect of the present application, the level of the input single-ended signal is a current mode logic level, and the level of the output differential signal of the third-stage amplifier is a complementary metal oxide semiconductor level.

[0017] In a possible implementation of the first aspect of the present application, the front-end receiving circuit is used for waveform distortion correction in a single-to-dual application scenario.

[0018] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation methods of any of the above aspects when executing the computer program.

[0019] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0020] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic diagram of a front-end receiving circuit provided in an embodiment of the present application;

[0023] Figure 2 Provided in the embodiments of this application Figure 1 A schematic diagram of a first-stage amplifier of a first embodiment of the front-end receiving circuit shown;

[0024] Figure 3 Provided in the embodiments of this application Figure 1 A schematic diagram of a first-stage amplifier of a second embodiment of the front-end receiving circuit shown;

[0025] Figure 4 Provided in the embodiments of this application Figure 1 Schematic diagram of the second-stage amplifier in the front-end receiving circuit shown. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0027] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality" means two or more. In addition, unless otherwise specified, the terms "first" and "second" are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or order.

[0028] Figure 1 This is a schematic diagram of a front-end receiving circuit provided in an embodiment of the present application. Figure 1 As shown, the front-end receiving circuit includes a first-stage amplifier A101, a second-stage amplifier A103, and a third-stage amplifier 105. The first-stage amplifier A101 includes an input transistor pair, a cross-coupled load disposed on the load side of the input transistor pair, and an adjustable resistance and capacitance unit disposed on the bias side of the input transistor pair. The control side of the input transistor pair is configured to receive an input single-ended signal and a reference voltage signal. The cross-coupled load is configured to convert the input single-ended signal into an output differential signal of the first-stage amplifier A101 and provide duty cycle calibration for the input single-ended signal. The adjustable resistance and capacitance unit is configured to cooperate with the input transistor pair and the cross-coupled load to provide channel loss compensation with a given gain within a given frequency range of the input single-ended signal. The second-stage amplifier A103 is configured to, under the action of a bias current source, perform a first swing amplification on the output differential signal of the first-stage amplifier A101, thereby raising the common-mode level of the output differential signal of the first-stage amplifier A101 to the common-mode level of the output differential signal of the second-stage amplifier A103. The third-stage amplifier 105 is used to perform a second swing amplification on the output differential signal of the second-stage amplifier A103 , so as to increase the common-mode level of the output differential signal of the second-stage amplifier A103 to the common-mode level of the output differential signal of the third-stage amplifier 105 .

[0029] Figure 1 The front-end receiving circuit shown can be used in data centers, cloud computing, artificial intelligence and other applications. It can be used in electronic systems or local circuits of electronic devices for digital information transmission. For example, it can be deployed at the receiving end for data recovery, thereby meeting the requirements of overcoming waveform distortion, supporting the adaptability between front-end and back-end circuits, reducing circuit area, reducing power consumption and improving performance. In some embodiments, Figure 1 The front-end receiver circuit shown can meet the requirements of High Bandwidth Memory (HBM) for minimizing the front-end receiver circuit area while achieving higher data rates. It can also be used to meet the low power consumption and high bandwidth requirements of other high-performance memories. Furthermore, single-ended signals generally face greater waveform distortion challenges than differential signals in high-speed data transmission applications. Furthermore, adapting single-ended signals to dual-ended signals requires consideration of hardware resources and losses. Figure 1 The front-end receiving circuit shown in the figure, through optimized circuit structure design including the first, second, and third-stage amplifiers, addresses the challenge of waveform distortion in single-ended signals and takes into account the compatibility issues of single-stage to dual-stage circuits. It achieves adaptive adjustment of the output pole position and improved gain boost performance over a wide bandwidth to account for channel loss, mitigates duty cycle deviation caused by single-ended input of high-speed signals, and provides low-power and low-latency level conversion while overcoming waveform distortion of single-ended signals and providing channel insertion loss compensation, thus achieving a balanced optimized design in terms of circuit area, circuit power consumption, and circuit performance. These are described in detail below.

[0030] See Figure 1 , Figure 1The structure of the front-end receiving circuit shown is a three-stage amplifier structure. The first-stage amplifier A101 includes an input transistor pair, a cross-coupling load disposed on the load side of the input transistor pair, and an adjustable resistance and capacitance unit disposed on the bias side of the input transistor pair. In addition, the control side of the input transistor pair is used to receive an input single-ended signal and a reference voltage signal. The cross-coupling load is used to convert the input single-ended signal into an output differential signal of the first-stage amplifier A101 and provide duty cycle calibration for the input single-ended signal. The adjustable resistance and capacitance unit is used to cooperate with the input transistor pair and the cross-coupling load to provide channel loss compensation for a given gain in a given frequency range of the input single-ended signal. In this way, through the first-stage amplifier A101, it is possible to adapt to input signals passing through different channels and add a continuous time linear equalization (CTLE) function to compensate for channel insertion loss. The circuit design of the first-stage amplifier A101 provides a small-signal amplifier with a cross-coupled pair load. Compared to solutions using source-capacitor degeneration structures and adding zeros through source negative feedback in current-mode logic (CML) structures, this amplifier not only provides channel insertion loss compensation similar to CTLE, but also adds a resistor-capacitor gain boost adjustment method. This allows for optimal gain boost performance tailored to varying channel insertion losses, thereby better compensating for high-frequency signal losses. Furthermore, using a cross-coupled load, such as a cross-coupled pair, instead of a resistive load can improve the duty cycle distortion of the first-stage output signal caused by single-ended signal input. Furthermore, compared to resistive loads, cross-coupled loads offer greater flexibility in adjusting the output pole position, thus providing a more suitable common-mode level while achieving a wider bandwidth.

[0031] Continue reading Figure 1The second-stage amplifier A103 is configured to, under the action of a bias current source, perform a first swing amplification on the output differential signal of the first-stage amplifier A101, thereby raising the common-mode level of the output differential signal of the first-stage amplifier A101 to the common-mode level of the output differential signal of the second-stage amplifier A103. The third-stage amplifier 105 is configured to perform a second swing amplification on the output differential signal of the second-stage amplifier A103, thereby raising the common-mode level of the output differential signal of the second-stage amplifier A103 to the common-mode level of the output differential signal of the third-stage amplifier 105. In some embodiments, the second-stage amplifier A103 is a fully differential inverting amplifier with a bias current, and the third-stage amplifier 105 is an inverting amplifier circuit with a latch structure. The input transistor pair of the first-stage amplifier A101 can be an N-type metal oxide semiconductor (NMOS) or a P-type metal oxide semiconductor (PMOS). Taking PMOS as an example, the circuit of the first-stage amplifier A101 includes a pair of PMOS transistors, with the input signal serving as the control voltage (gate) for the pair of PMOS transistors. The bias electrode (source) of the pair of PMOS transistors serves as the output of the circuit of the first-stage amplifier A101. Furthermore, in some embodiments, a resistor and a capacitor are connected in parallel to the bias electrode (source) of the pair of PMOS transistors, thereby forming an adjustable resistance-capacitance unit. By adjusting the resistance value of the resistor and the capacitance value of the capacitor, optimized performance can be provided for input signals of different channels to overcome high-frequency signal loss caused by the channel. Furthermore, a cross-coupling load unit is connected to the load stage (drain) of the pair of PMOS transistors. The cross-coupling load unit can cooperate with the adjustable resistance-capacitance unit to better adjust the position of the output pole, helping to achieve high-frequency loss compensation within a wider bandwidth and improving duty cycle distortion when a single-ended signal is input. In some embodiments, the bias current source of the circuit of the second-stage amplifier A103 uses a set value to provide a certain proportion of swing amplification. The current source of the circuit of the second-stage amplifier A103 is set through simulation based on the common-mode level of the output differential signal of the first-stage amplifier A101, thereby increasing the common-mode level of the output differential signal of the first-stage amplifier A101 and better adapting to the process voltage temperature (PVT). Here, the common-mode level of the input single-ended signal of the circuit of the first-stage amplifier A101 is known or can be measured.In some embodiments, the use of a PMOS (below a first preset threshold) or NMOS (above a second preset threshold) in the first-stage circuit is determined based on the common-mode level of the input single-ended signal. This can better support the requirements of the application environment. For example, memory-related protocols specify the range of variation in the common-mode level of the input single-ended signal. In some embodiments, based on the common-mode level of the output differential signal of the first-stage amplifier A101, the setting value of the bias current source of the circuit of the second-stage amplifier A103 is determined through simulation, thereby determining the common-mode level of the output differential signal of the second-stage amplifier A103, thereby better adapting the circuit of the third-stage amplifier 105.

[0032] Continue reading Figure 1 , Figure 1The front-end receiving circuit shown utilizes a three-stage amplifier structure. In the circuit design of the first-stage amplifier A101, a cross-coupled load is used on the load side to convert single-ended signals to differential signals and provide duty cycle optimization. Additionally, an adjustable resistor-capacitor unit, such as a parallel resistor-capacitor structure, is used on the bias side to provide channel loss compensation with different gains for specific frequency bands. In some embodiments, the specific frequency band is determined by the resistor-capacitor time constant, the transconductance (gm) of the input transistor pair, and the load resistance and capacitance of the cross-coupled load. The different gains are determined by the resistor-capacitor time constant and the transconductance of the input transistor pair. Here, the reference voltage (Vref) of the input transistor pair can be understood as a static set level. The common-mode level of the differential output signal of the single-to-dual conversion of the first-stage amplifier A101 circuit, i.e., the output differential signal of the first-stage amplifier A101, is determined by the current and load size of the first stage. This allows for flexible adaptation to the needs of the application scenario. For example, if the common-mode level of the input single-ended signal is below a preset threshold, a PMOS transistor can be used as the input transistor pair, along with a corresponding reference voltage. Alternatively, if the common-mode level of the input single-ended signal is above another preset threshold, an NMOS transistor can be used as the input transistor pair, along with a corresponding reference voltage. Furthermore, the preset threshold for measuring the common-mode level of the input single-ended signal is related to the power supply voltage. For example, assuming a 0.8 volt power supply, a PMOS transistor can be used when the common-mode level of the input single-ended signal is below 400 millivolts, and an NMOS transistor is suitable when the common-mode level of the input single-ended signal is above 500 millivolts. In this way, by combining the requirements of the application scenario, the application scenario externally indicates the frequency range in which the input signal has the highest loss, thus providing a basis for the circuit configuration of the first-stage amplifier A101. If the application scenario requirements shift, such as if the frequency range of the input signal changes, the adjustable resistor and capacitor unit automatically adapts. In some embodiments, in order to further enhance the ability of automatic adaptation through adjustable resistance and capacitance units, series resistors and capacitors can be added as low-frequency compensation, and parallel resistors and capacitors can be used as high-frequency compensation, and both can be controlled by a switch to select whether to provide or not provide corresponding channel loss compensation.

[0033] Continue reading Figure 1The front-end receiving circuit is optimized in terms of circuit structure design including the first-stage amplifier A101, the second-stage amplifier A103 and the third-stage amplifier 105. In response to the challenge of waveform distortion of single-ended signals and taking into account the problems of single-to-dual conversion and adaptability of the front-end and back-end circuits, on the one hand, the input single-ended signal is converted into the output differential signal of the first-stage amplifier A101 through a cross-coupling load and duty cycle calibration is provided for the input single-ended signal. On the other hand, channel loss compensation for a given gain in a given frequency range of the input single-ended signal is provided through the collaboration between the adjustable resistance and capacitance unit, the input transistor pair and the cross-coupling load; the adjustment function of the adjustable resistance and capacitance unit can change the resistance and capacitance time constant, thereby improving the input signal of different channels. Improved performance, combined with cross-coupled loads, can improve the duty cycle distortion caused by single-ended signal input, help to flexibly adjust the position of the output pole, and help to provide a more appropriate common-mode level on the basis of achieving a larger bandwidth; using the second-stage amplifier A103 to perform the first swing amplification and the third-stage amplifier 105 to perform the second swing amplification, this two-stage swing amplification design reduces the swing and conversion of the input single-ended signal on the power consumption of the overall circuit structure. It can not only improve the duty cycle deviation caused by the single-ended input of the high-speed signal, but also first output a larger swing signal in the second-stage amplifier A103 and then output a full-swing differential output signal in the third-stage amplifier 105, which helps to amplify the signal to a complementary metal oxide semiconductor (CMOS) level more quickly. In one example, using Figure 1 The designed front-end receiving circuit can improve single-ended signal distortion and maintain duty cycle deviation within 5% when receiving a 7.2 Gigabits per second (Gbps) input single-ended signal with a channel insertion loss of -3.5dB at 3.6 gigahertz (GHz). Adjustable gain boost can also be used to compensate for the -3dB channel insertion loss. By converting CML levels to CMOS levels through a two-stage inverter structure, a circuit area of ​​260 square microns and power consumption of less than 1 milliwatt can be achieved on a 9-nanometer process node.

[0034] In short, Figure 1The front-end receiving circuit shown, through optimization of circuit structure design, addresses the challenges of waveform distortion of single-ended signals, as well as the issues of single-to-dual conversion and adaptability of the front-end and back-end circuits. It can adaptively adjust the output pole position and improve gain boost performance in response to channel loss within a wide bandwidth range, improve the duty cycle deviation caused by single-ended input of high-speed signals, and provide low-power and low-latency level conversion on the basis of overcoming the waveform distortion of single-ended signals and providing channel insertion loss compensation. This achieves a balanced optimization design in terms of circuit area, circuit power consumption and circuit performance, which helps to meet the wide temperature range requirements of automotive applications.

[0035] Figure 2 Provided in the embodiments of this application Figure 1 Schematic diagram of the first stage amplifier of the first embodiment of the front-end receiving circuit shown in FIG. Figure 2As shown, the first-stage amplifier B201 includes an input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220), a cross-coupled load A230 deployed on the load side (drain (load electrode) 212 of P-type field effect transistor A210 and drain (load electrode) 222 of P-type field effect transistor B220) of the input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220), and an adjustable resistance and capacitance unit A232 deployed on the bias side (source (bias electrode) 216 of P-type field effect transistor A210 and source (bias electrode) 226 of P-type field effect transistor B220) of the input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220). The control side (gate (control electrode) 214 of P-type field effect transistor A210 and gate (control electrode) 224 of P-type field effect transistor B220) of the input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220) is used to receive an input single-ended signal A240 and a reference voltage signal A242. The cross-coupled load A230 is used to convert the input single-ended signal A240 into an output differential signal A250 of the first-stage amplifier B201 and provide duty cycle calibration for the input single-ended signal A240. The adjustable resistance and capacitance unit A232 is used to cooperate with the input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220) and the cross-coupled load A230 to provide channel loss compensation with a given gain for a given frequency range of the input single-ended signal A240. In this way, in response to the challenges of waveform distortion of single-ended signals, as well as the problems of single-to-dual conversion and adaptability of the front- and back-end circuits, on the one hand, the input single-ended signal A240 is converted into the output differential signal A250 of the first-stage amplifier B201 through the cross-coupling load A230 and duty cycle calibration is provided for the input single-ended signal A240. On the other hand, through the collaboration between the adjustable resistor and capacitor unit A232, the input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220) and the cross-coupling load A230, channel loss compensation for a given gain in a given frequency range of the input single-ended signal A240 is provided; through the adjustment function of the adjustable resistor and capacitor unit A232, the resistor and capacitor time constants can be changed, thereby improving the performance for input signals of different channels. Combined with the cross-coupling load A230, the duty cycle distortion caused by the input of single-ended signals can be improved, which helps to flexibly adjust the position of the output pole and help provide a more suitable common-mode level on the basis of achieving a larger bandwidth. In addition, Figure 2 PMOS is used in this circuit, which reflects the flexible adaptation of the application scenario to select the corresponding input transistor pair (P-type field effect transistor A210 and P-type field effect transistor B220) semiconductor type. In addition, Figure 2 The working voltage A251 and the ground terminal A252 are also shown as an example.

[0036] Figure 3 Provided in the embodiments of this application Figure 1 FIG. 1 is a schematic diagram of a first-stage amplifier of a second embodiment of a front-end receiving circuit. Figure 3 As shown, the first-stage amplifier C301 includes an input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320), a cross-coupled load B330 deployed on the load side (source (load electrode) 312 of N-type field effect transistor A310 and source (load electrode) 322 of N-type field effect transistor B320) of the input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320), and an adjustable resistance and capacitance unit B332 deployed on the bias side (drain (bias electrode) 316 of N-type field effect transistor A310 and drain (bias electrode) 326 of N-type field effect transistor B320) of the input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320). The control side (gate (control electrode) 314 of N-type field effect transistor A310 and gate (control electrode) 324 of N-type field effect transistor B320) of the input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320) is used to receive an input single-ended signal B340 and a reference voltage signal B342. The cross-coupled load B330 is used to convert the input single-ended signal B340 into an output differential signal B350 of the first-stage amplifier C301 and provide duty cycle calibration for the input single-ended signal B340. The adjustable resistance and capacitance unit B332 is used to cooperate with the input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320) and the cross-coupled load B330 to provide channel loss compensation with a given gain within a given frequency range of the input single-ended signal B340. In this way, in response to the challenges of waveform distortion of single-ended signals, as well as the problems of single-to-dual conversion and adaptability of the front- and back-end circuits, on the one hand, the input single-ended signal B340 is converted into the output differential signal B350 of the first-stage amplifier C301 through the cross-coupling load B330 and duty cycle calibration is provided for the input single-ended signal B340. On the other hand, through the collaboration between the adjustable resistor and capacitor unit B332, the input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320) and the cross-coupling load B330, channel loss compensation for a given gain in a given frequency range of the input single-ended signal B340 is provided; through the adjustment function of the adjustable resistor and capacitor unit B332, the resistor and capacitor time constants can be changed, thereby improving the performance for input signals of different channels. Combined with the cross-coupling load B330, the duty cycle distortion caused by the single-ended signal input can be improved, which helps to flexibly adjust the position of the output pole and help provide a more suitable common-mode level on the basis of achieving a larger bandwidth. In addition, Figure 3NMOS is used in the circuit, which reflects the flexible adaptation of the application scenario to select the corresponding input transistor pair (N-type field effect transistor A310 and N-type field effect transistor B320) semiconductor type. In addition, Figure 3 The working voltage B351 and the ground terminal B352 are also shown as an example.

[0037] See Figure 1 、 Figure 2 and Figure 3 In one possible implementation, the transistor type of the input transistor pair is determined based on the common-mode level of the input single-ended signal. Generally, the common-mode level of the input single-ended signal of the first-stage amplifier circuit is known or measurable. In some embodiments, whether the first-stage circuit uses PMOS (below a first preset threshold) or NMOS (above a second preset threshold) is determined based on the common-mode level of the input single-ended signal. This can better support the requirements of the application environment. For example, memory-related protocols specify the range of variation of the common-mode level of the input single-ended signal. In this way, the requirements of the application scenario can be flexibly adapted. For example, if the common-mode level of the input single-ended signal is below a certain preset threshold, a PMOS transistor can be used as the input transistor pair, and a corresponding reference voltage can be used. For another example, if the common-mode level of the input single-ended signal is above another preset threshold, an NMOS transistor can be used as the input transistor pair, and another corresponding reference voltage can be used. Furthermore, the preset threshold used to measure the common-mode level of the input single-ended signal is associated with the power supply voltage. For example, assuming that the power supply voltage is 0.8 volts, it can be set so that when the common-mode level of the input single-ended signal is lower than 400 millivolts, PMOS is used; when the common-mode level of the input single-ended signal is higher than 500 millivolts, NMOS is suitable. In this way, combined with the needs of the application scenario, the application scenario also externally tells the input signal in which frequency ranges there is a large loss, thereby providing a basis for the configuration of the circuit of the first-stage amplifier. If the needs of the application scenario shift, for example, the frequency range of the input signal changes to a certain extent, automatic adaptation is performed through the adjustable resistance and capacitance unit. In some embodiments, in order to further enhance the ability of automatic adaptation through the adjustable resistance and capacitance unit, series resistance and capacitance can be added as low-frequency compensation, and parallel resistance and capacitance can be used as high-frequency compensation, and both can be selected through a controllable switching switch to select whether to provide or not provide corresponding channel loss compensation.

[0038] In some embodiments, when the common-mode level of the input single-ended signal is below a first preset threshold, the transistor type of the input transistor pair is a P-type metal oxide semiconductor, and when the common-mode level of the input single-ended signal is above a second preset threshold, the transistor type of the input transistor pair is an N-type metal oxide semiconductor. Generally, the common-mode level of the input single-ended signal of the first-stage amplifier circuit is known or measurable. In some embodiments, the use of a PMOS transistor (below the first preset threshold) or an NMOS transistor (above the second preset threshold) in the first-stage circuit is determined based on the common-mode level of the input single-ended signal. This can better support the requirements of the application environment. For example, memory-related protocols specify the range of common-mode levels of input single-ended signals. This allows for flexible adaptation to the requirements of the application scenario. For example, if the common-mode level of the input single-ended signal is below a certain preset threshold, a PMOS transistor can be used as the input transistor pair, and a corresponding reference voltage can be used. For another example, if the common-mode level of the input single-ended signal is above another preset threshold, an NMOS transistor can be used as the input transistor pair, and another corresponding reference voltage can be used. Furthermore, the preset threshold for measuring the common-mode level of the input single-ended signal is associated with the power supply voltage. For example, assuming the power supply voltage is 0.8 volts, it can be set so that when the common-mode level of the input single-ended signal is lower than 400 millivolts, PMOS is used; when the common-mode level of the input single-ended signal is higher than 500 millivolts, NMOS is suitable. In this way, combined with the needs of the application scenario, the application scenario also externally informs the input signal in which frequency ranges there is greater loss, thereby providing a basis for the configuration of the circuit of the first-stage amplifier. If the needs of the application scenario shift, for example, the frequency range of the input signal changes to a certain extent, automatic adaptation is performed through the adjustable resistance and capacitance unit. In some embodiments, in order to further enhance the ability of automatic adaptation through the adjustable resistance and capacitance unit, series resistors and capacitors can be added as low-frequency compensation, and parallel resistors and capacitors can be used as high-frequency compensation, and both can be selected through a controllable switch to select whether to provide or not provide corresponding channel loss compensation.

[0039] In some embodiments, the common-mode level of the reference voltage signal is determined based on the common-mode level of the input single-ended signal, and the common-mode level of the input single-ended signal is determined based on the communication protocol associated with the front-end receiving circuit. In this way, the requirements of the application scenario can be flexibly adapted. For example, if the common-mode level of the input single-ended signal is lower than a preset threshold, a PMOS transistor can be used as the input transistor pair, and a corresponding reference voltage can be used. For another example, if the common-mode level of the input single-ended signal is higher than another preset threshold, an NMOS transistor can be used as the input transistor pair, and another corresponding reference voltage can be used. The common-mode level of the input single-ended signal is determined based on the communication protocol associated with the front-end receiving circuit, which means that the common-mode level of the input single-ended signal can be set in combination with external requirements such as the communication protocol, and the common-mode level of the reference voltage signal can be determined based on the common-mode level of the input single-ended signal. In addition, the transistor type of the input transistor pair is determined based on the common-mode level of the input single-ended signal. In this way, the common-mode level of the corresponding input single-ended signal and the transistor type of the corresponding input transistor pair are set based on the communication protocol associated with the front-end receiving circuit, which helps to adapt to the needs of the application scenario, thereby better realizing the ability to adaptively adjust the output pole position and improve the gain boost performance in response to channel loss within a larger bandwidth range, improving the duty cycle deviation caused by the single-ended input of the high-speed signal, and, on the basis of overcoming the waveform distortion of the single-ended signal and providing channel insertion loss compensation, also providing low-power and low-latency level conversion, achieving a balanced optimization design in terms of circuit area, circuit power consumption and circuit performance.

[0040] In one possible implementation, the given frequency range is determined based on the resistance-capacitance time constant of the adjustable resistance-capacitance unit, the transconductance of the input transistor pair, and the load resistance and load capacitance of the cross-coupled load. The given gain is determined based on the resistance-capacitance time constant of the adjustable resistance-capacitance unit and the transconductance of the input transistor pair. In the circuit design of the first-stage amplifier, a cross-coupled load is used on the load side to convert single-ended to differential and provide duty cycle optimization. In addition, an adjustable resistance-capacitance unit, such as a parallel resistor-capacitor structure, is used on the bias side to provide different gains for channel loss compensation in a specific frequency band. In some embodiments, the specific frequency band is determined by the resistance-capacitance time constant, the transconductance (gm) of the input transistor pair, and the load resistance and load capacitance of the cross-coupled load. Different gains are determined by the resistance-capacitance time constant and the transconductance of the input transistor pair. In this way, combined with the needs of the application scenario, the application scenario externally indicates in which frequency ranges the input signal has greater loss, thereby providing a basis for the configuration of the first-stage amplifier circuit. If the requirements of the application scenario shift, for example, if the frequency range of the input signal changes, the adjustable resistor and capacitor unit can automatically adapt. In some embodiments, to further enhance the ability of the adjustable resistor and capacitor unit to automatically adapt, a series resistor and capacitor can be added for low-frequency compensation, and a parallel resistor and capacitor can be used for high-frequency compensation. Both can be controlled by a switch to select whether to provide or not provide corresponding channel loss compensation. In this way, in response to the challenges of waveform distortion of single-ended signals, as well as taking into account the problems of single-to-dual conversion and adaptability of the previous and next-stage circuits, on the one hand, the input single-ended signal is converted into the output differential signal of the first-stage amplifier and duty cycle calibration is provided for the input single-ended signal through a cross-coupling load. On the other hand, through the collaboration between the adjustable resistor and capacitor unit, the input transistor pair and the cross-coupling load, channel loss compensation for a given gain in a given frequency range of the input single-ended signal is provided; through the adjustment function of the adjustable resistor and capacitor unit, the resistor and capacitor time constants can be changed, thereby improving the performance for input signals of different channels. Combined with the cross-coupling load, the duty cycle distortion caused by the single-ended signal input can be improved, which helps to flexibly adjust the position of the output pole and help provide a more suitable common-mode level on the basis of achieving a larger bandwidth.

[0041] In one possible implementation, the given frequency range and the given gain are pre-set, and the adjustable resistance and capacitance unit is adjusted to adapt to an offset within the given frequency range or an offset within the given gain. Thus, by adjusting the adjustable resistance and capacitance unit, the resistance and capacitance time constants can be changed, thereby adapting to an offset within the given frequency range or an offset within the given gain, thereby facilitating adaptation to the offset required by the application scenario.

[0042] In one possible implementation, the adjustable resistance and capacitance unit includes a first adjustable resistor and a first adjustable capacitor connected in parallel between the bias sides of the input transistor pair, and the first adjustable resistor and the first adjustable capacitor are respectively connected to the front-end receiving circuit through a switchable switch so as to selectively provide high-frequency channel loss compensation for the input single-ended signal. In this way, high-frequency channel loss compensation for the input single-ended signal is provided by connecting the first adjustable resistor and the first adjustable capacitor in parallel between the bias sides of the input transistor pair. Moreover, by selectively providing high-frequency channel loss compensation for the input single-ended signal through the switchable switch, it is possible to choose to provide or not provide high-frequency channel loss compensation for the input single-ended signal. In this way, the flexibility of operation and the adaptability to the needs of different application scenarios are improved.

[0043] In some embodiments, the adjustable resistance and capacitance unit further includes a second adjustable resistor and a second adjustable capacitor connected in series between the bias sides of the input transistor pair, and the second adjustable resistor and the second adjustable capacitor are connected to the front-end receiving circuit through a switchable switch so as to selectively provide low-frequency channel loss compensation for the input single-ended signal. In this way, by connecting the second adjustable resistor and the second adjustable capacitor in series between the bias sides of the input transistor pair, low-frequency channel loss compensation for the input single-ended signal is provided. Moreover, by switching the switch so as to selectively provide low-frequency channel loss compensation for the input single-ended signal, it is possible to choose to provide or not provide low-frequency channel loss compensation for the input single-ended signal. In this way, the flexibility of operation and the adaptability to the needs of different application scenarios are improved.

[0044] In one possible implementation, the first swing amplification is used to adapt the DC operating point of the third-stage amplifier and improve the adaptability of the front-end receiving circuit to different process corner voltage and temperature conditions. The second swing amplification is used to adapt the DC operating point of the subsequent circuit associated with the front-end receiving circuit. In some embodiments, the bias current source of the second-stage amplifier circuit uses a set value to provide a certain proportion of swing amplification. The current source of the second-stage amplifier circuit is set through simulation based on the common-mode level of the output differential signal of the first-stage amplifier, thereby improving the common-mode level of the output differential signal of the first-stage amplifier and better adapting to process corner voltage and temperature conditions. Thus, using the second-stage amplifier for the first swing amplification and the third-stage amplifier for the second swing amplification, this two-stage swing amplification design reduces the impact of the swing and conversion of the input single-ended signal on the power consumption of the overall circuit structure. It not only improves the duty cycle deviation caused by high-speed signals on single-ended input, but also facilitates faster signal amplification to CMOS levels by first outputting a larger swing signal in the second-stage amplifier and then outputting a full-swing differential output signal in the third-stage amplifier.

[0045] In some embodiments, the second-stage amplifier includes a fully differential inverting amplifier circuit. The fully differential inverting amplifier circuit, under the action of a bias current source, converts the output differential signal of the first-stage amplifier into the output differential signal of the second-stage amplifier. The current magnitude of the bias current source is determined by simulating the range of variation of the common-mode level of the output differential signal of the first-stage amplifier. Thus, the bias current source of the second-stage amplifier circuit uses a set value to provide a certain percentage of swing amplification. The current source of the second-stage amplifier circuit is set through simulation based on the common-mode level of the output differential signal of the first-stage amplifier, thereby increasing the common-mode level of the output differential signal of the first-stage amplifier and better adapting to process corner voltage and temperature. Furthermore, based on the common-mode level of the output differential signal of the first-stage amplifier, the set value of the bias current source of the second-stage amplifier circuit is determined through simulation, thereby determining the common-mode level of the output differential signal of the second-stage amplifier and further better adapting to the circuit of the third-stage amplifier. In this way, the second-stage amplifier is used to perform the first swing amplification and the third-stage amplifier is used to perform the second swing amplification. This two-stage swing amplification design reduces the impact of the swing and conversion of the input single-ended signal on the power consumption of the overall circuit structure. It can not only improve the duty cycle deviation caused by the single-ended input of the high-speed signal, but also first output the larger swing signal in the second-stage amplifier and then output the full-swing differential output signal in the third-stage amplifier, which helps to amplify the signal to CMOS level more quickly.

[0046] In some embodiments, the third-stage amplifier includes an inverting amplifier circuit with a latching structure, the inverting amplifier circuit with a latching structure configured to convert the output differential signal of the second-stage amplifier into the output differential signal of the third-stage amplifier, and the fully differential inverting amplifier circuit and the inverting amplifier circuit with a latching structure are used together to provide duty cycle calibration for the input single-ended signal. Thus, through optimization of the circuit structure design, addressing the challenges of waveform distortion of single-ended signals and considering the compatibility issues of single-to-dual conversion between previous and subsequent stage circuits, the output pole position can be adaptively adjusted to channel loss over a wide bandwidth, and gain boost performance can be improved. This improves the duty cycle deviation caused by high-speed signals at single-ended input. Furthermore, while overcoming waveform distortion of single-ended signals and providing channel insertion loss compensation, low-power and low-latency level conversion is also provided, achieving a balanced optimized design with respect to circuit area, circuit power consumption, and circuit performance.

[0047] In one possible embodiment, the input single-ended signal has a current-mode logic level, and the output differential signal of the third-stage amplifier has a complementary metal-oxide-semiconductor level. Thus, through optimization of the circuit structure design, addressing the challenges of waveform distortion of single-ended signals and taking into account the compatibility issues of single-to-dual conversion between previous and subsequent stage circuits, the output pole position can be adaptively adjusted to channel loss within a wide bandwidth, and gain boost performance can be improved. This improves the duty cycle deviation caused by single-ended input of high-speed signals. Furthermore, while overcoming waveform distortion of single-ended signals and providing channel insertion loss compensation, low-power and low-latency level conversion is also provided, achieving a balanced and optimized design with respect to circuit area, power consumption, and performance.

[0048] In one possible embodiment, the front-end receiving circuit is used for waveform distortion correction in a single-to-dual application scenario. Thus, by optimizing the circuit structure design of the first-stage amplifier, the second-stage amplifier, and the third-stage amplifier, the challenges of waveform distortion in single-ended signals are addressed, and the issues of single-to-dual conversion and adaptability of the previous and next-stage circuits are taken into consideration. This allows adaptive adjustment of the output pole position and improved gain boost performance in response to channel loss within a wide bandwidth, improving duty cycle deviation caused by single-ended input of high-speed signals. Furthermore, while overcoming waveform distortion of single-ended signals and providing channel insertion loss compensation, low-power and low-latency level conversion is also provided, achieving a balanced optimized design with respect to circuit area, circuit power consumption, and circuit performance.

[0049] Figure 4 Provided in the embodiments of this application Figure 1 The schematic diagram of the second stage amplifier in the front-end receiving circuit is shown in FIG. Figure 4As shown, the second-stage amplifier B403 includes a fully differential inverting amplifier circuit (fully differential inverting amplifier A480 and fully differential inverting amplifier B482). Under the action of bias current source 470, the fully differential inverting amplifier circuit (fully differential inverting amplifier A480 and fully differential inverting amplifier B482) converts the output differential signal C450 of the first-stage amplifier into the output differential signal 460 of the second-stage amplifier. The current level of bias current source 470 is determined by simulating the variation range of the common-mode level of the output differential signal C450 of the first-stage amplifier. Figure 4 Also shown is the operating voltage C451.

[0050] See Figure 4 The bias current source 470 of the second-stage amplifier B403 circuit uses a set value to provide a certain percentage of swing amplification. Simulation is used to set the current source of the second-stage amplifier B403 circuit based on the common-mode level of the output differential signal C450 of the first-stage amplifier, thereby increasing the common-mode level of the output differential signal C450 of the first-stage amplifier and improving adaptation to process corner voltage and temperature. Furthermore, simulation is used to determine the set value of the bias current source 470 of the second-stage amplifier B403 circuit based on the common-mode level of the output differential signal C450 of the first-stage amplifier, thereby determining the common-mode level of the output differential signal 460 of the second-stage amplifier and further improving adaptation to the third-stage amplifier circuit. In this way, the second-stage amplifier B403 is used to perform the first swing amplification and the third-stage amplifier is used to perform the second swing amplification. This two-stage swing amplification design reduces the impact of the swing and conversion of the input single-ended signal on the power consumption of the overall circuit structure. It can not only improve the duty cycle deviation caused by the single-ended input of the high-speed signal, but also first output a large swing signal in the second-stage amplifier B403 and then output a full-swing differential output signal in the third-stage amplifier, which helps to amplify the signal to CMOS level more quickly.

[0051] See Figure 1 、 Figure 2 、 Figure 3 and Figure 4The front-end receiving circuit utilizes a three-stage amplifier structure. In the circuit design of the first-stage amplifier, a cross-coupled load is used on the load side of the input transistor pair, and an adjustable resistor-capacitor unit is used on the bias side of the input transistor pair. A bias current source is used in the second-stage amplifier, and the second-stage amplifier, under the action of the bias current source, is used to perform a first swing amplification on the output differential signal of the first-stage amplifier, thereby raising the common-mode level of the output differential signal of the first-stage amplifier to the common-mode level of the output differential signal of the second-stage amplifier. This optimized circuit design takes into account that the bias current of the first-stage amplifier circuit will vary with temperature and voltage over a wide temperature range, which may cause the bandwidth of the first-stage amplifier to fluctuate unexpectedly. For example, at low temperatures, the current decreases, resulting in a decrease in bandwidth; at high temperatures, the current increases, resulting in an increase in bandwidth. Therefore, considering that when the front-end receiving circuit receives a signal, the reduced bandwidth will affect the output amplitude of the first-stage amplifier, which directly affects the final output result. In order to address the problem of bandwidth reduction caused by current over a wide temperature range, the above-mentioned circuit optimization design is utilized, a three-stage amplifier structure is adopted, and, optionally, the bias current source is designed to be a constant temperature current. In some embodiments, taking the ratio of the gate-source voltage VGS of the field-effect transistor to the resistor R associated with the bias current source as an example, VGS / R can be set to be a current with a negative temperature coefficient, and ΔVGS / R can be set to be a current with a positive temperature coefficient. In this way, by proportionally mixing the two currents with positive and negative temperature coefficients into a current with a constant temperature coefficient, the bandwidth loss at low temperatures such as -40°C can be compensated. Therefore, the front-end receiving circuit provided in the embodiment of the present application effectively overcomes the problem of bandwidth reduction caused by current over a wide temperature range by utilizing its optimized circuit design.

[0052] The methods and devices provided in the embodiments of the present application are based on the same inventive concept. Since the principles of the methods and devices for solving problems are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0053] The present application also provides a computer-readable storage medium having computer instructions stored therein. When the computer instructions are executed on a computer device (e.g., one or more processors), the method steps in the above-described method embodiments can be implemented. The specific implementation of the above-described method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above-described method embodiments and / or the specific functions described in the above-described apparatus embodiments, and will not be further described here.

[0054] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part through software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part as a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that contains a collection of one or more available media. Available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable storage medium.

[0055] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including the instruction device, which implements the function specified in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0056] In the above embodiments, the descriptions of each embodiment have different emphases. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in sequence, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A front-end receiving circuit, characterized in that: The front-end receiving circuit includes: a first-stage amplifier, wherein the first-stage amplifier comprises an input transistor pair, a cross-coupled load disposed on a load side of the input transistor pair, and an adjustable resistance and capacitance unit disposed on a bias side of the input transistor pair, the control side of the input transistor pair being configured to receive an input single-ended signal and a reference voltage signal, the cross-coupled load being configured to convert the input single-ended signal into an output differential signal of the first-stage amplifier and to provide duty cycle calibration for the input single-ended signal, and the adjustable resistance and capacitance unit being configured to cooperate with the input transistor pair and the cross-coupled load to provide channel loss compensation for a given gain within a given frequency range of the input single-ended signal; a second-stage amplifier, wherein the second-stage amplifier is configured to, under the action of a bias current source, perform a first swing amplification on the output differential signal of the first-stage amplifier, so as to raise the common-mode level of the output differential signal of the first-stage amplifier to the common-mode level of the output differential signal of the second-stage amplifier; The third-stage amplifier is configured to perform a second swing amplification on the output differential signal of the second-stage amplifier so as to increase the common-mode level of the output differential signal of the second-stage amplifier to the common-mode level of the output differential signal of the third-stage amplifier.

2. The front-end receiving circuit according to claim 1, wherein: The transistor type of the input transistor pair is determined based on a common-mode level of the input single-ended signal.

3. The front-end receiving circuit according to claim 2, wherein: When the common-mode level of the input single-ended signal is lower than a first preset threshold, the transistor type of the input transistor pair is a P-type metal oxide semiconductor, and when the common-mode level of the input single-ended signal is higher than a second preset threshold, the transistor type of the input transistor pair is an N-type metal oxide semiconductor.

4. The front-end receiving circuit according to claim 2, wherein: The common mode level of the reference voltage signal is determined based on the common mode level of the input single-ended signal, and the common mode level of the input single-ended signal is determined based on a communication protocol associated with the front-end receiving circuit.

5. The front-end receiving circuit according to claim 1, wherein: The given frequency range is determined based on the resistance and capacitance time constant of the adjustable resistance and capacitance unit, the transconductance of the input transistor pair, and the load resistance and load capacitance included in the cross-coupling load, and the given gain is determined based on the resistance and capacitance time constant of the adjustable resistance and capacitance unit and the transconductance of the input transistor pair.

6. The front-end receiving circuit according to claim 1, wherein: The given frequency range and the given gain are preset, and the adjustment of the adjustable resistance and capacitance unit is used to adaptively adjust the offset of the given frequency range or the offset of the given gain.

7. The front-end receiving circuit according to claim 1, wherein: The adjustable resistance and capacitance unit includes a first adjustable resistor and a first adjustable capacitor connected in parallel between the bias sides of the input transistor pair. The first adjustable resistor and the first adjustable capacitor are respectively connected to the front-end receiving circuit through a switchable switch to selectively provide high-frequency channel loss compensation for the input single-ended signal.

8. The front-end receiving circuit according to claim 7, wherein: The adjustable resistance and capacitance unit also includes a second adjustable resistor and a second adjustable capacitor connected in series between the bias sides of the input transistor pair. The second adjustable resistor and the second adjustable capacitor are connected to the front-end receiving circuit through a switchable switch to selectively provide low-frequency channel loss compensation for the input single-ended signal.

9. The front-end receiving circuit according to claim 1, wherein: The first swing amplification is used to adapt the DC operating point of the third-stage amplifier and improve the adaptability of the front-end receiving circuit to different process corner voltage and temperature conditions. The second swing amplification is used to adapt the DC operating point of the subsequent stage circuit associated with the front-end receiving circuit.

10. The front-end receiving circuit according to claim 9, wherein: The second-stage amplifier includes a fully differential inverting amplifier circuit, which converts the output differential signal of the first-stage amplifier into the output differential signal of the second-stage amplifier under the action of the bias current source. The current size of the bias current source is determined by simulating the variation range of the common-mode level of the output differential signal of the first-stage amplifier.

11. The front-end receiving circuit according to claim 10, wherein: The third-stage amplifier includes an inverting amplifier circuit with a latch structure, which is used to convert the output differential signal of the second-stage amplifier into the output differential signal of the third-stage amplifier, and the fully differential inverting amplifier circuit and the inverting amplifier circuit with a latch structure are together used to provide duty cycle calibration for the input single-ended signal.

12. The front-end receiving circuit according to claim 1, wherein: The level of the input single-ended signal is a current mode logic level, and the level of the output differential signal of the third-stage amplifier is a complementary metal oxide semiconductor level.

13. The front-end receiving circuit according to claim 1, wherein: The front-end receiving circuit is used for waveform distortion correction in a single-to-dual application scenario.

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