Clock data recovery method and device based on injection locking

Abstract

The invention provides a clock data recovery method and device based on injection locking. The method comprises the following steps: sampling an analog clock signal to obtain an initial sampling signal; performing clock error detection on the initial sampling signal to obtain a clock error signal; performing first digital filtering processing on the clock error signal to obtain a first clock control signal; acquiring a clock jitter estimated value output by a digital filter in the injection-locked oscillator, injecting the clock jitter estimated value into the clock error signal, then performing second digital filtering processing, and performing calculation based on the clock signal subjected to the second digital filtering processing to obtain a second clock control signal; a phase of the sampled clock signal is adjusted based on the first clock control signal and the second clock control signal. The invention further provides a device for implementing the method. The clock data recovery method provided by the invention has strong tracking capability on clock jitter and low noise, and can be applied to the next-generation communication technology.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock data processing, and in particular to a clock data recovery method based on injection locking and an apparatus implementing the method. BACKGROUND

[0002] With the development of mobile Internet, cloud computing, big data, artificial intelligence and other technologies, the demand for bandwidth, power consumption, connection density and other requirements of high-speed data center communication in related industries has grown significantly. In order to meet the demand for significant growth of communication bandwidth, the single-channel rate of high-speed serial communication is constantly increasing. At present, the single-channel 100Gbps system has matured and has been widely used, and the next generation of single-channel 200Gbps related standards have been basically completed. Compared with the single-channel 100Gbps system, the symbol rate of the single-channel 200Gbps system is doubled, and more stringent requirements are put forward for the clock jitter of the system. In the high-speed serial communication system, the clock data recovery (CDR) technology is an important means to track and eliminate clock jitter. Therefore, in order to ensure the signal quality of the single-channel 200Gbps system, a better clock data recovery method is needed to eliminate clock jitter.

[0003] At present, high-speed serial communication systems widely use digital signal processors (DSP) based on analog-to-digital converters to implement clock data recovery at the receiving end. In order to reduce the complexity and delay of the digital signal processor, a 1x oversampling scheme is usually used, that is, the sampling rate of the analog-to-digital converter is the same as the symbol rate. Under the 1x oversampling scheme, the digital controlled oscillator at the receiving end provides the sampling clock of the analog-to-digital converter. Clock data recovery will feed back the control of the digital controlled oscillator according to the signal collected by the analog-to-digital converter, so as to ensure that the analog-to-digital converter can complete the collection of the signal at the best sampling time.

[0004] In the above process, the digital signal processor uses a clock data recovery algorithm to calculate the deviation of the actual sampling time of the signal from the best sampling time, and uses a digital filter to filter the deviation. The result of the filtering is used to fine-tune the frequency or phase of the digital controlled oscillator in a digital control manner. Among them, the technology of calculating the deviation of the collected signal from the best sampling time is called clock error detection technology or phase error detection technology. In the above technology, the digital filter is usually designed as a first-order or second-order digital low-pass filter, and the output of the digital low-pass filter is used to control the clock phase output by the digital controlled oscillator.

[0005] However, as the symbol rate increases, the signal is more sensitive to clock jitter, and thus a larger clock data recovery bandwidth is required. The traditional method can only increase the bandwidth of clock data recovery by adjusting the coefficients of the PI controller, which will make the noise in the clock data recovery loop larger, and even cause the loop to become unstable. Therefore, the traditional clock data recovery cannot provide sufficient bandwidth, which is not conducive to the high-quality transmission of 200Gbps or even higher speed signals.

[0006] A clock and data recovery circuit in the prior art uses an injection-locked oscillator, but the injection-locked oscillator used is implemented based on an analog circuit, a large number of complex circuits are required to process the analog signal, and the clock generated needs to be additionally phase-adjusted, resulting in complex clock data recovery calculation. Purely using an injection-locked oscillator for clock data recovery calculation cannot meet the requirements of 200Gbps or even higher speed signal transmission quality. SUMMARY

[0007] The first object of the present application is to provide an injection-locked clock data recovery method with strong clock jitter tracking ability and low noise.

[0008] The second object of the present application is to provide an injection-locked clock data recovery device based on the injection-locked clock data recovery method described above.

[0009] To achieve the first object of the present application, the injection-locked clock data recovery method provided by the present application includes sampling an analog clock signal to obtain an initial sampling signal; clock error detection is performed on the initial sampling signal to obtain a clock error signal; the clock error signal is subjected to first digital filtering processing to obtain a first clock control signal; the clock jitter estimation value output by the digital filter in the injection-locked oscillator is obtained, and the clock jitter estimation value is injected into the clock error signal and subjected to second digital filtering processing, and a second clock control signal is calculated based on the clock signal subjected to the second digital filtering processing; and the phase of the sampling clock signal is adjusted based on the first clock control signal and the second clock control signal.

[0010] As can be seen from the above scheme, after calculating and obtaining the clock error signal, the present invention processes the clock error signal in two ways: one is a first digital filtering process performed by a first digital filter, and the other is a second digital filtering process performed by injecting a clock jitter estimate into the clock error signal through an injection-locked oscillator. Finally, the phase of the sampling clock signal is adjusted based on the first and second clock control signals obtained from the two processing paths. Because the clock jitter estimate generated by the injection-locked oscillator only contains the frequency components of the actual clock jitter, it has high clock jitter tracking accuracy and a wide jitter frequency tracking range, resulting in more accurate phase of the generated sampling clock signal and more effective clock jitter elimination.

[0011] In addition, the injection-locked oscillator can be a fully digital injection-locked oscillator based entirely on digital signal calculations and does not design analog signal processing. This approach can avoid the circuit complexity problems brought by sampling analog circuits and can also improve the accuracy of the phase calculation of the sampling clock signal.

[0012] A preferred solution is to perform a second digital filtering process on the clock error signal injected with the clock jitter estimation value, and then perform a gain adjustment, and obtain the second clock control signal by calculation based on the gain-adjusted clock jitter estimation value.

[0013] It can be seen that the gain adjustment of the clock jitter estimation value after the second digital filtering process makes the amplitude of the second clock control signal more matched with the amplitude of the first clock control signal, making the sampling clock signal finally calculated more accurate.

[0014] A preferred solution is to adaptively adjust the tap coefficients of the digital filter based on the clock jitter estimation value; and / or adaptively adjust the gain coefficient based on the clock jitter estimation value.

[0015] It can be seen that by adaptively adjusting the tap coefficient and gain coefficient of the digital filter, the tap coefficient and gain coefficient of the digital filter are made more reasonable, which can avoid interference with the clock data recovery calculation.

[0016] A further solution is that adaptively adjusting the tap coefficients of the digital filter based on the clock jitter estimate includes: determining whether the clock jitter estimate is greater than a first threshold; if so, reducing the tap coefficients; otherwise, updating the tap coefficients according to the clock error signal.

[0017] Therefore, by adaptively adjusting the tap coefficients of the digital filter, the filtering effect can be adjusted according to the frequency characteristics of the real clock jitter, the bandwidth of the clock digital recovery loop can be ensured, and the signal-to-noise ratio of the clock jitter estimation value can be improved. For example, the frequency of the real clock jitter is within 1 MHz. In an ideal case, the digital filter will be adaptively adjusted to a low-pass filter with a bandwidth slightly higher than 1 MHz, which can ensure tracking of 1 MHz clock jitter and filter out noise components above 1 MHz in the clock error signal.

[0018] Further, adaptively adjusting the gain coefficient based on the clock jitter estimation value comprises: judging whether the clock jitter estimation value is greater than a second threshold, if yes, increasing the gain coefficient, otherwise, decreasing the gain coefficient.

[0019] Therefore, adaptively adjusting the gain coefficient can control the amplitude of the output clock control signal, and avoid the amplitude of the control signal exceeding the range that the circuit can tolerate. Moreover, in the case that the amplitude of the real clock jitter is very small or does not have the injection locking condition, the gain coefficient will automatically decrease to 0, avoiding the output of the injection locking oscillator interfering with the operation of the clock data recovery.

[0020] Further, adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal comprises: if the clock signal generation module generating the sampling clock signal is a frequency control type clock signal generation module, calculating the instantaneous frequency of the sampling clock signal based on the weighted values of the frequency of the first clock control signal, the frequency of the second clock control signal and the reference frequency, and calculating the target phase of the sampling clock signal based on the instantaneous frequency and the initial phase.

[0021] Therefore, for the frequency control type clock signal generation module, the present application first calculates the instantaneous frequency of the sampling clock signal, and then calculates the target phase of the sampling clock signal based on the instantaneous frequency and the initial phase, so as to accurately calculate the target phase of the sampling clock signal.

[0022] Optionally, adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal comprises: if the clock signal generation module generating the sampling clock signal is a phase control type clock signal generation module, calculating the target phase of the sampling clock signal based on the weighted values of the phase of the first clock control signal, the phase of the second clock control signal and the initial phase.

[0023] Therefore, for the phase control type clock signal generation module, the target phase of the sampling clock signal is directly calculated in a weighted manner, and the initial phase of the sampling clock signal is also considered when calculating the target phase, so as to accurately calculate the target phase of the sampling clock signal.

[0024] Further, the initial sampling signal obtained by sampling is equalized before clock error detection.

[0025] Therefore, by equalizing the initial sampling signal, the quality of the signal input to the clock error detection module can be improved, thereby improving the quality of the sampling clock signal obtained by final calculation.

[0026] To achieve the above-mentioned second object, the application provides a clock data recovery device based on injection locking, comprising a sampling module for sampling an analog clock signal; a clock error detection module for detecting the clock error of the initial sampling signal obtained by sampling to obtain a clock error signal; a first digital filter for first digital filtering processing of the clock error signal to obtain a first clock control signal; an injection locking oscillator for obtaining a clock jitter estimation value, injecting the clock jitter estimation value into the clock error signal, and using a second digital filter for second digital filtering processing, and calculating a second clock control signal based on the clock signal after the second digital filtering processing; and a clock signal generation module for adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal.

[0027] From the above-mentioned scheme, the application sets an injection locking oscillator, injects the clock jitter estimation value into the clock error signal, and performs second digital filtering processing to obtain a second clock control signal, which is used as the basis for calculating the phase of the sampling clock signal together with the first clock error signal obtained by first digital filtering processing of the clock error signal. In this way, the phase of the sampling clock signal obtained by calculation is more accurate, the tracking ability of the clock jitter is stronger, and the clock jitter can be effectively eliminated.

[0028] A preferred scheme is that the injection locking oscillator further comprises an adaptive adjustment module for adaptively adjusting the tap coefficient of the second digital filter and / or the gain coefficient for gain adjustment of the clock jitter estimation value processed by the second digital filter based on the clock jitter estimation value.

[0029] Therefore, by adaptively adjusting the tap coefficient and the gain coefficient of the second digital filter of the injection locking oscillator, the bandwidth of the clock data recovery loop can be ensured, the signal-to-noise ratio of the clock jitter estimation value can be improved, and the amplitude of the control signal can be prevented from exceeding the range that can be tolerated by the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a structural block diagram of an embodiment of the clock data recovery device based on injection locking of the application.

[0031] Figure 2is a structural block diagram of an injection-locked oscillator in an embodiment of the injection-locked clock data recovery device of the present application.

[0032] Figure 3 is a flowchart of an embodiment of the injection-locked clock data recovery method of the present application.

[0033] The present application is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0034] The injection-locked clock data recovery device of the present application is used to adjust the phase of the sampling clock signal, thereby eliminating clock jitter. The present application improves the tracking accuracy of clock jitter and the tracking range of jitter frequency, so that the phase of the generated sampling clock signal is more accurate.

[0035] Referring to Figure 1 The injection-locked clock data recovery device of the present embodiment has a sampling module 11, an equalization module 12, a clock error detection module 13, a first digital filter 14, an injection-locked oscillator 20, and a clock signal generation module 15.

[0036] The sampling module 11 is used to collect an analog clock signal. The sampling module 11 needs to receive the sampling clock signal output by the clock signal generation module 15 and sample the analog clock signal based on the sampling clock signal. In the present embodiment, the clock signal generation module 15 is mainly used to adjust the phase of the sampling clock signal. Therefore, the sampling module 11 mainly dynamically adjusts the phase of the sampling based on the sampling clock signal output by the clock signal generation module 15, and obtains a discrete sampling signal. The initial sampling signal obtained by the sampling module 11 is denoted as S0.

[0037] The equalization module 12 is used to perform equalization processing on the initial sampling signal S0 obtained by the sampling module 11, for example, setting a sliding window of a certain width, and performing equalization processing on the discrete data based on the sliding window. By performing equalization processing on the initial sampling signal, the influence of intersymbol interference can be suppressed, thereby improving the quality of the initial sampling signal S0, which is beneficial to subsequent calculation and improves the phase accuracy of the sampling clock signal obtained by calculation. The initial sampling signal S0 forms an equalization signal S1 after being processed by the equalization module 12, and the equalization signal S1 is output to the clock error detection module 13.

[0038] The clock error detection module 13 is used to calculate the deviation between the actual sampling time of the clock signal and the ideal sampling time. The clock error detection module 13 can be implemented based on a 1x oversampling algorithm, such as a Mueller-Muller algorithm or a least mean square error algorithm. The clock error signal TE output by the clock error detection module 13 is divided into two paths, one of which is output to the first digital filter 14, and the other of which is output to the injection-locked oscillator 20. The clock error signal TE output to the first digital filter 14 and the injection-locked oscillator 20 is the same, i.e., the frequency and phase are the same.

[0039] The first digital filter 14 can be a first-order or second-order digital filter, or a filter of another order, which is used to perform digital filtering on the clock error signal TE and obtain a first clock control signal C1. The first clock control signal C1 is output to the clock signal generation module 15.

[0040] Referring to Figure 2 The injection-locked oscillator 20 is provided with a second digital filter 22, a gain module 23, a calculation module 24, and an adaptive adjustment module 25. After the clock error signal TE is input to the injection-locked oscillator 20, the clock error signal TE is injected with a clock jitter estimation value J. Preferably, in the initial state, the clock jitter estimation value J can be set to an initial value. The second digital filter 22 performs second digital filtering on the clock error signal TE injected with the clock jitter estimation value J. Preferably, the second digital filter 22 is a first-order or second-order filter, or a filter of another order. The second digital filter 22 outputs an updated clock jitter estimation value J and feeds it back to the input end of the injection-locked oscillator 20. In this way, the injection-locked oscillator 20 continuously injects the updated clock jitter estimation value J into the clock error signal TE.

[0041] The gain module 23 performs gain adjustment processing on the clock jitter estimation value J output by the second digital filter 22, such as increasing the amplitude of the clock jitter estimation value J. The clock jitter estimation value after the gain adjustment processing is output to the calculation module 24. The calculation module 24 calculates a second clock control signal C2 based on the clock jitter estimation value after the gain adjustment processing. The second clock control signal C2 is also output to the clock signal generation module 15.

[0042] The adaptive adjustment module 25 is used to dynamically adjust the tap coefficient of the second digital filter 22 and the gain coefficient of the gain module 23 according to the clock jitter estimation value J output by the second digital filter 22, so as to flexibly control the amplitude of the second clock control signal output by the injection-locked oscillator 20, and avoid interference of the output of the injection-locked oscillator 20 on the operation of the clock digital recovery.

[0043] The clock signal generation module 15 adjusts the phase of the sampling clock signal based on the first clock control signal C1 and the second clock control signal C2, and outputs the phase-adjusted clock signal to the sampling module 11, which samples the analog signal based on the updated clock sampling signal.

[0044] In this embodiment, the equalization module 12, the clock error detection module 13, the first digital filter 14, and the injection-locked oscillator 20 are all implemented on a digital signal processor (DSP), so the injection-locked oscillator 20 is a fully digital injection-locked oscillator, that is, the clock error signal TE received by the injection-locked oscillator 20 is a digital signal, and the injection-locked oscillator 20 processes the digital signal and outputs a clock jitter estimation value J that is also a digital signal, so the injection-locked oscillator 20 processes the received digital signal in a fully digital signal processing manner.

[0045] The working method of the clock data recovery device based on injection locking according to the present application will be described below in conjunction with Figure 3 The working method of the clock data recovery device based on injection locking according to the present application will be described below in conjunction with

[0046] Next, step S12 is performed, and the equalization module 12 performs equalization processing on the initial sampling signal S0 obtained by the sampling module 11, thereby suppressing the influence of intersymbol interference to improve the quality of the initial sampling signal S0, and obtains an equalized signal S1 after equalization processing, which is output to the clock error detection module 13.

[0047] Then, step S13 is performed, and the clock error detection module 13 obtains the equalized signal S1 and performs error detection on the equalized signal S1, that is, calculates the degree of deviation between the actual sampling time of the clock signal and the ideal sampling time, obtains a clock error signal TE, and outputs the clock error signal TE to the first digital filter 14 and the injection-locked oscillator 20, respectively.

[0048] Next, step S14 is performed, and the first digital filter 14 performs first digital filtering processing on the clock error signal TE to obtain a first clock control signal C1. The first digital filter 14 can be a first-order digital filter or a second-order digital filter, and the type of the digital filter is not limited in this embodiment.

[0049] Meanwhile, step S15 is also performed, and the clock error signal TE is also input to the injection locking oscillator 20, and a second clock control signal C2 is calculated by the injection locking oscillator 20. Specifically, the clock error signal TE is first added to the clock jitter estimation value J output by the second digital filter 22 inside the injection locking oscillator 20, so as to realize injection locking of the clock jitter estimation value J and the clock error signal TE. Then, the clock error signal TE to which the clock jitter estimation value J is injected is output to the second digital filter 22, and the second digital filter 22 performs second digital filtering processing on the received clock signal, so as to obtain a new clock jitter estimation value J. Moreover, the new clock jitter estimation value J is also fed back to the input end of the injection locking oscillator 20, and is used for injection locking with the value of the subsequent clock error signal TE.

[0050] Next, the clock jitter estimation value J output by the second digital filter 22 is input to the gain module 23, and the gain module 23 performs gain adjustment processing on the clock jitter estimation value J, such as increasing or decreasing the amplitude of the clock jitter estimation value J.

[0051] In order to more flexibly adjust the amplitude of the second clock control signal C2 output by the injection locking oscillator 20, the embodiment dynamically performs adaptive adjustment on the tap coefficient of the second digital filter 22 and the gain coefficient of the gain module 23 through the adaptive adjustment module 25. Specifically, when the tap coefficient of the second digital filter 22 is adaptively adjusted, the clock jitter estimation value J currently output by the second digital filter 22 is first obtained, and it is determined whether the clock jitter estimation value J is greater than a first threshold T1. If the clock jitter estimation value J is greater than the first threshold T1, the tap coefficient of the second digital filter 22 is decreased, otherwise, the tap coefficient is updated according to the clock error signal TE, for example, the corresponding tap coefficient h(n) is updated according to the nth clock error signal TE(n), and the update of the tap coefficient h(n) can be represented by the following formula: wherein i represents the ith tap coefficient, μ1 is a pre-set coefficient, and L is the total number of tap coefficients.

[0052] In addition, the adaptive adjustment module 25 also dynamically adjusts the gain coefficient of the gain module 23. Specifically, it is determined whether the clock jitter estimation value J is greater than a second threshold T2. If the clock jitter estimation value J is greater than the second threshold T2, the gain coefficient G is increased, for example, the gain coefficient G is updated to G + μ2; if the clock jitter estimation value J is not greater than the second threshold T2, the gain coefficient G is decreased, and the gain coefficient G is updated to G - μ3, wherein μ2 and μ3 are pre-set values, and are both positive numbers, and μ2 and μ3 can be equal or not equal.

[0053] Finally, the calculation module 24 needs to calculate the second clock control signal C2 according to the clock jitter estimation value J after the gain adjustment processing. There are two ways to calculate the second clock control signal C2, the first way is that the clock signal generation module 15 is a frequency control type clock signal generation module, when calculating the second clock control signal C2, the instantaneous frequency fclk of the sampling clock signal is directly controlled, therefore, the second clock control signal C2 can be directly calculated by the difference between the nth clock jitter estimation value J(n) and the last clock jitter estimation value J(n-1), that is, C2(n) = J(n) - J(n-1). The second way is that the clock signal generation module 15 is a phase control type clock signal generation module, when calculating the second clock control signal C2, the phase of the sampling clock signal is directly controlled, therefore, the second clock control signal directly uses the nth clock jitter estimation value J(n), that is, C2(n) = J(n).

[0054] The embodiment can control the amplitude of the output second clock control signal C2, avoid the amplitude of the second clock control signal C2 exceeding the range that the circuit can tolerate, and automatically reduce the gain coefficient G to 0 if the amplitude of the real clock jitter is very small or does not have the condition of injection locking, at this time, the output of the injection locking oscillator 20 is also 0, which can avoid the output of the injection locking oscillator 20 interfering with the normal operation of the clock data recovery operation.

[0055] In addition, the tap coefficient of the second digital filter 22 is also adaptively adjusted, which can adaptively adjust the filtering effect according to the frequency characteristics of the real clock jitter, which can not only ensure the bandwidth of the clock data recovery loop, but also improve the signal-to-noise ratio of the clock jitter estimation value J. For example, the frequency of the real clock jitter is within 1MHz, and in the ideal case, the second digital filter 22 will be adaptively adjusted to a low-pass filter with a bandwidth slightly higher than 1MHz, which can not only ensure the tracking of 1MHz clock jitter, but also filter out noise components above 1MHz in the clock error signal.

[0056] After the first clock control signal C1 and the second clock control signal C2 are obtained, the last step S16 is performed, and the clock signal generation module 15 adjusts the phase of the sampling clock signal based on the first clock control signal C1 and the second clock control signal C2. Specifically, if the clock signal generation module 15 is a frequency control type clock signal generation module, the instantaneous frequency fclk of the sampling clock signal is calculated based on the first clock control signal C1 and the second clock control signal C2, for example, the frequency of the first clock control signal C1, the frequency of the second clock control signal C2 and the reference frequency f0 of the sampling clock signal are weighted to calculate the instantaneous frequency fclk of the sampling clock signal, that is, the instantaneous frequency fclk(t) of the sampling clock signal is calculated based on the frequency of the first clock control signal C1, the frequency of the second clock control signal C2 and the weighted value of the reference frequency f0, and the specific calculation formula is as follows: fclk(t) = k1(C1(t) + C2(t)) + f0, where t is time, and k1 is a pre-set proportional coefficient related to the circuit design of the clock generation module. After calculating the instantaneous frequency fclk of the sampling clock signal, the final target phase pclk of the sampling clock signal is calculated according to the initial phase p0 of the sampling clock signal, and the specific calculation formula is as follows: where t is time.

[0057] If the clock signal generation module 15 is a phase control type clock signal generation module, the target phase pclk of the sampling clock signal is directly calculated based on the first clock control signal C1 and the second clock control signal C2, and the specific calculation formula is as follows: where t is time, k2 is a pre-set proportional coefficient, and p0 is the initial phase of the sampling clock signal. Therefore, in this case, the target phase pclk of the sampling clock signal is calculated based on the phase of the first clock control signal C1, the phase of the second clock control signal C2 and the weighted value of the initial phase p0 of the sampling clock signal.

[0058] After the target phase pclk and the instantaneous frequency fclk of the sampling clock signal are calculated, the waveform of the sampling clock signal can be determined, that is, the data output by the sampling clock signal is determined, and finally the sampling clock signal is fed back to the sampling module 11. The sampling module 11 samples the analog signal based on the updated sampling clock signal, and starts the processing process of the clock signal in the next cycle.

[0059] In the above embodiment, the first digital filter 14 and the injection locking oscillator 20 work independently and do not affect each other. Moreover, the injection locking oscillator 20 can be turned off independently, for example, the gain coefficient of the gain module 23 of the injection locking oscillator 20 is set to 0, and the second clock control signal C2 output by the injection locking oscillator 20 is also 0, which is equivalent to turning off the injection locking oscillator 20.

[0060] The present application does not limit the type and implementation of the first digital filter 14 and the second digital filter 22, as long as the clock error signal TE can be filtered. In addition, the injection-locked oscillator 20 can also not be provided with the adaptive adjustment module 25, and the tap coefficients of the second digital filter 22 and the gain coefficients of the gain module 23 of the injection-locked oscillator 20 can be manually set, which does not affect the calculation of the second clock control signal C2 in this way.

[0061] In addition, in other embodiments, the equalization module can not be provided, and after the sampling module samples the initial sampling signal, it can be directly output to the clock error detection module. Alternatively, before the analog clock signal is sampled, the analog clock signal in the front stage is equalized, so that the initial sampling signal sampled by the sampling module is the equalized clock signal, and no equalization is required after sampling.

[0062] The present application uses an injection-locked method in the processing of clock data recovery, that is, the clock jitter estimation value is injected into the clock error signal. Since the clock jitter estimation value generated by the injection-locked oscillator only contains the frequency component of the real clock jitter, the method of the present application has high clock jitter tracking accuracy and high jitter frequency tracking range, and can be applied to the next generation of high-speed serial communication systems.

[0063] In addition, the injection-locked oscillator and the first digital filter proposed by the present application are both implemented based on a digital signal processor, so that they work independently of each other and can be individually turned off to save power consumption, and almost no delay is added. In addition, the tap coefficients of the second digital filter and the gain coefficients of the gain module in the injection-locked oscillator can be adjusted, and can be adaptively adjusted or manually adjusted. If the adaptive adjustment method is used, the configuration parameters can be automatically adjusted to the optimal performance according to the current clock data recovery working state, thereby improving the phase accuracy of the generated sampling clock signal and effectively avoiding clock jitter.

[0064] Finally, it should be emphasized that the above is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various changes and modifications, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method of clock data recovery based on injection locking, characterized in that, The method comprises: sampling an analog clock signal to obtain an initial sampling signal; detecting clock error of the initial sampling signal to obtain a clock error signal; performing first digital filtering on the clock error signal to obtain a first clock control signal; obtaining a clock jitter estimation value of a digital filter output in an injection-locked oscillator, performing second digital filtering on the clock error signal after injecting the clock jitter estimation value into the clock error signal, and calculating a second clock control signal based on the clock signal after the second digital filtering; adjusting a phase of a sampling clock signal based on the first clock control signal and the second clock control signal.

2. The injection-locked clock data recovery method according to claim 1, wherein: after performing the second digital filtering on the clock error signal to which the clock jitter estimation value is injected to obtain a new clock jitter estimation value, gain adjustment is further performed, and the second clock control signal is calculated based on the gain-adjusted clock jitter estimation value.

3. The injection-locked clock data recovery method according to claim 2, characterized in that, The method further comprises: performing adaptive adjustment on tap coefficients of the digital filter based on the clock jitter estimation value; and / or performing adaptive adjustment on gain coefficients based on the clock jitter estimation value.

4. The injection-locked clock data recovery method according to claim 3, wherein: performing adaptive adjustment on tap coefficients of the digital filter based on the clock jitter estimation value comprises: determining whether the clock jitter estimation value is greater than a first threshold value, and if yes, decreasing the tap coefficients, otherwise, updating the tap coefficients according to the clock error signal.

5. The injection-locked clock data recovery method according to claim 3, wherein: performing adaptive adjustment on gain coefficients based on the clock jitter estimation value comprises: determining whether the clock jitter estimation value is greater than a second threshold value, and if yes, increasing the gain coefficients, otherwise, decreasing the gain coefficients.

6. The injection-locked clock data recovery method according to any one of claims 1 to 5, wherein: adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal comprises: if a clock signal generation module generating the sampling clock signal is a frequency control type clock signal generation module, calculating an instantaneous frequency of the sampling clock signal based on a weighted value of a frequency of the first clock control signal, a frequency of the second clock control signal and a reference frequency, and calculating a target phase of the sampling clock signal based on the instantaneous frequency and an initial phase.

7. The injection-locked clock data recovery method according to any one of claims 1 to 5, wherein: adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal comprises: if a clock signal generation module generating the sampling clock signal is a phase control type clock signal generation module, calculating a target phase of the sampling clock signal based on a weighted value of a phase of the first clock control signal, a phase of the second clock control signal and an initial phase. ​ 8. The method of claim 1 to 5, wherein: Before the clock error detection on the initial sampling signal, the initial sampling signal is equalized.

9. A clock data recovery apparatus based on injection locking, characterized by Comprises: a sampling module for sampling an analog clock signal; a clock error detection module for detecting clock error on the initial sampling signal obtained by sampling, to obtain a clock error signal; a first digital filter for first digital filtering processing on the clock error signal, to obtain a first clock control signal; an injection locked oscillator for obtaining a clock jitter estimation value, injecting the clock jitter estimation value into the clock error signal, and using a second digital filter for second digital filtering processing, to obtain a second clock control signal based on the clock signal after the second digital filtering processing; a clock signal generation module for adjusting the phase of the sampling clock signal based on the first clock control signal and the second clock control signal.

10. The apparatus of claim 9, wherein: the injection locked oscillator further comprises an adaptive adjustment module for adaptively adjusting the tap coefficients of the second digital filter and / or the gain coefficients for gain adjustment on the clock jitter estimation value after the second digital filtering processing, based on the clock jitter estimation value.

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