Band-gap reference circuit without operational amplifier

Abstract

The invention provides a band-gap reference circuit without an operational amplifier, and the circuit comprises a positive temperature coefficient generation module which generates negative feedback current with a positive temperature coefficient through a cross coupling structure composed of four transistors; the reference voltage generation module copies the output of the positive temperature coefficient generation module through a mirror image so as to generate a positive temperature coefficient voltage on an internal resistor and superposes a negative temperature coefficient voltage so as to obtain a band-gap reference voltage with a zero temperature coefficient; the starting module is connected with the output of the positive temperature coefficient generation module and injects current into the reference voltage generation module at the initial stage of establishing the band-gap reference voltage; and the current output module copies the output of the positive temperature coefficient generation module through a mirror image so as to generate zero temperature coefficient output current. An operational amplifier does not need to be introduced, so that extra device noise is not introduced, and the circuit can be widely applied to circuits sensitive to noise, such as phase-locked loops and oscillators.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converters, and more particularly to a bandgap reference circuit without operational amplifiers. Background Art

[0002] Traditional bandgap reference circuits use operational amplifiers to clamp the voltage, which not only results in a large area but also introduces operational amplifier noise into the output, greatly limiting their application in noise-sensitive circuits such as phase-locked loops and oscillators. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention proposes a bandgap reference circuit without operational amplifiers, which mainly solves the problem of the performance of audio devices caused by noise introduced by operational amplifiers.

[0004] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0005] This application provides a bandgap reference circuit without operational amplifiers, the circuit comprising:

[0006] A positive temperature coefficient generation module generates a negative feedback current with a positive temperature coefficient through a cross-coupled structure composed of four transistors.

[0007] The reference voltage generation module generates a positive temperature coefficient voltage on an internal resistor by mirroring the output of the positive temperature coefficient generation module, and superimposes a negative temperature coefficient voltage to obtain a bandgap reference voltage with zero temperature coefficient.

[0008] The startup module is connected to the output of the positive temperature coefficient generation module. It injects current into the reference voltage generation module during the initial stage of bandgap reference voltage establishment, thereby accelerating the startup of the reference voltage generation module, and shuts down after startup is completed.

[0009] The current output module generates a zero-temperature coefficient output current by mirroring the output of the positive temperature coefficient generation module.

[0010] In one embodiment of this application, the current output module includes: a first enable branch, a first branch, a second branch, and a current output branch. The enable branch receives a first enable signal to provide a first bias voltage to the first branch. The first branch proportionally replicates the output of the positive temperature coefficient generation module to generate a negative temperature coefficient voltage. The second branch proportionally replicates the output of the positive temperature coefficient generation module to generate a positive temperature coefficient voltage and superimposes it with the negative temperature coefficient voltage, so that the current of the first branch has a zero temperature coefficient. The current output branch mirrors and proportionally replicates the current of the first branch as the zero temperature coefficient output current for output.

[0011] In one embodiment of this application, the positive temperature coefficient generating module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor;

[0012] The gate of the second transistor is connected to a second enable signal, its source is grounded, and its drain is connected to one end of the first resistor. The drain of the first transistor is connected to the other end of the first resistor, its source is connected to the power supply voltage, and its gate is connected to the gate of the third transistor and also to the gate of the fourth transistor. The source of the third transistor is connected to the power supply voltage, and its drain is connected to the collector of the first transistor. The gate of the fourth transistor serves as the first output terminal, its source is connected to the drain of the fifth transistor, and its drain is connected to the gate of the fifth transistor as the second output terminal. The source of the fifth transistor is connected to the power supply voltage. Voltage; the base and collector of the first transistor are shorted and connected to the collector of the second transistor, and the emitter is connected to the collector of the third transistor; the collector of the second transistor is connected to the drain of the fourth transistor, and the emitter is connected to the collector of the fourth transistor; the collector of the third transistor is connected to the base of the fourth transistor, the base is connected to the collector of the fourth transistor, and the emitter is grounded; the emitter of the fourth transistor is grounded through the second resistor; wherein the first transistor, the second transistor, the third transistor, and the fourth transistor form the cross-coupled structure.

[0013] In one embodiment of this application, the startup module includes: a first transmission gate, a second transmission gate, and multiple parallel startup branches composed of current mirror units. The two transistors in each current mirror unit are respectively started by the first transmission gate and the second transmission gate to make the corresponding current mirror unit proportionally replicate the negative feedback current and merge it into the output node of the bandgap reference voltage. The first transmission gate and the second transmission gate are both started by the differential enable signal.

[0014] In one embodiment of this application, the reference voltage generating module includes: an eighth transistor, a ninth transistor, a twelfth transistor, a fifth transistor, a third resistor, and a seventh resistor;

[0015] The gate of the eighth transistor is connected to the second output terminal, the source is connected to the drain of the ninth transistor, and the drain is connected to the collector of the fifth transistor as the output node; the gate of the ninth transistor is connected to the first output terminal, and the source is connected to the power supply voltage; the base and collector of the fifth transistor are shorted, and the emitter is connected to one end of the third resistor and one end of the seventh resistor, respectively; the other end of the third resistor is grounded; the other end of the seventh resistor is connected to the drain of the twelfth transistor; the source of the twelfth transistor is grounded, and the gate is connected to the third enable signal.

[0016] In one embodiment of this application, the current output module includes an eleventh transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, and a seventh transistor.

[0017] The gate and drain of the eleventh transistor are shorted together and connected to the drain of the nineteenth transistor through the fourth resistor; the source is connected to the power supply voltage. The gate of the nineteenth transistor is connected to the first enable signal, and the source is grounded. The gate of the thirteenth transistor is connected to the gate of the eleventh transistor and the gate of the eighteenth transistor, respectively; the source is connected to the drain of the fourteenth transistor, and the drain is connected to the collector of the sixth transistor. The source of the fourteenth transistor is connected to the power supply voltage, and the gate is connected to the drain of the thirteenth transistor and the gate of the seventeenth transistor, respectively. The gate of the fifteenth transistor is connected to the second enable signal. The source of the transistor is connected to the power supply voltage, and the drain is connected to the source of the sixteenth transistor. The gate of the sixteenth transistor is connected to the first output terminal. The drain is connected to the base of the sixth transistor and the collector of the seventh transistor. The emitter of the sixth transistor is connected to one end of the fifth resistor and the base of the seventh transistor. The emitter of the seventh transistor is grounded through the sixth resistor. The other end of the fifth resistor is grounded. The source of the seventeenth transistor is connected to the power supply voltage, and the drain is connected to the source of the eighteenth transistor. The drain of the eighteenth transistor serves as the output terminal of the zero-temperature coefficient output current.

[0018] The nineteenth transistor, the fourth resistor, and the eleventh transistor form the first enable branch; the thirteenth transistor, the fourteenth transistor, the sixth transistor, and the fifth resistor form the first branch; the fifteenth transistor, the sixteenth transistor, the seventh transistor, and the sixth resistor form the second branch; and the seventeenth transistor and the eighteenth transistor form the current output branch.

[0019] In one embodiment of this application, the circuit further includes an enable signal generation circuit, which includes a first inverter, a second inverter, a third inverter, a capacitor, and a differential output buffer; the input terminal of the first inverter is connected to the first enable signal, and the output terminal is connected to the input terminal of the second inverter and the first input terminal of the third inverter respectively; the output terminal of the second inverter serves as the output node of the second enable signal and is connected to the second input terminal of the third inverter; the output terminal of the third inverter is connected to one end of the capacitor and the input terminal of the differential output buffer respectively; the other end of the capacitor is grounded; and the differential output buffer outputs the differential enable signal.

[0020] As described above, the op-amp-free bandgap reference circuit provided in this application has the following beneficial effects.

[0021] This application has a simple structure and does not require the introduction of operational amplifiers, thus avoiding the introduction of additional device noise. The overall noise performance is significantly improved, and it can be widely used in noise-sensitive circuits such as phase-locked loops and oscillators. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a bandgap reference circuit without operational amplifiers in one embodiment of this application.

[0023] Figure 2 This is a schematic diagram of an enable signal generation circuit in one embodiment of this application.

[0024] Figure 3 This is a simulation diagram of the temperature characteristic curve of the bandgap reference voltage in one embodiment of this application.

[0025] Figure 4 This is a simulation diagram of the temperature characteristic curve of a zero temperature coefficient current in one embodiment of this application.

[0026] Figure 5 The PSRR characteristic of a bandgap reference circuit in one embodiment of this application is shown. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0028] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] Please see Figure 1 , Figure 1 This is a schematic diagram of the circuit architecture of an op-amp-free bandgap reference circuit according to one embodiment of this application. The op-amp-free bandgap reference circuit provided in this application includes: a positive temperature coefficient (PTC) generation module, which generates a negative feedback current with a positive temperature coefficient through a cross-coupled structure composed of four transistors; a reference voltage generation module, which generates a positive temperature coefficient voltage across an internal resistor by mirroring the output of the PTC generation module, and superimposes a negative temperature coefficient voltage to obtain a bandgap reference voltage with zero temperature coefficient; a startup module, which is connected to the output of the PTC generation module, injects current into the reference voltage generation module during the initial stage of bandgap reference voltage establishment, thereby accelerating the startup of the reference voltage generation module, and shuts down after startup is completed; and a current output module, which generates a zero temperature coefficient output current by mirroring the output of the PTC generation module.

[0030] In one embodiment, the positive temperature coefficient generating module includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a first resistor R1, a second resistor R2, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4;

[0031] The gate of the second transistor M2 is connected to the second enable signal EN, its source is grounded, and its drain is connected to one end of the first resistor R1. The drain of the first transistor M1 is connected to the other end of the first resistor R1, its source is connected to the power supply voltage VDD, and its gate is connected to the gate of the third transistor M3 and also to the gate of the fourth transistor M4. The source of the third transistor M3 is connected to the power supply voltage VDD, and its drain is connected to the collector of the first transistor M3. The gate of the fourth transistor M4 serves as the first output terminal, its source is connected to the drain of the fifth transistor M5, and its drain is connected to the gate of the fifth transistor M5 as the second output terminal. The source of the fifth transistor M5 is connected to the power supply voltage VDD. The base and collector of the first transistor Q1 are short-circuited and connected to the collector of the second transistor Q2, while its emitter is connected to the collector of the third transistor Q3. The collector of the second transistor Q2 is connected to the drain of the fourth transistor M4, and its emitter is connected to the collector of the fourth transistor Q4. The collector of the third transistor Q3 is connected to the base of the fourth transistor Q4, and its base is connected to the collector of the fourth transistor Q4. Its emitter is grounded to GND. The emitter of the fourth transistor Q4 is grounded to GND through the second resistor R2. The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 form the quad cross-coupled structure. This structure can effectively save circuit area.

[0032] In one embodiment, the startup module includes: a first transmission gate, a second transmission gate, and multiple parallel startup branches composed of current mirror units. The two transistors (M6 and M7) in each current mirror unit are respectively started by the first transmission gate and the second transmission gate to proportionally replicate the negative feedback current I. PTAT It is then fed into the output node of the bandgap reference voltage, which outputs the bandgap reference voltage V. BGThe first and second transmission gates are both activated by the differential enable signals (EN1 and EN2). Specifically, each transmission gate can consist of a PMOS transistor and an NMOS transistor. The source of the NMOS transistor is connected to the drain of the PMOS transistor as the output of the transmission gate, and the drain of the NMOS transistor is connected to the source of the PMOS transistor as the input of the corresponding transmission gate. The gate of the NMOS transistor is connected to the enable signal EN2, and the gate of the PMOS transistor is connected to the enable signal EN1. EN1 and EN2 constitute the differential enable signals. In the startup circuit, the gates of the two transistors of the current mirror power supply are connected to the outputs of the two transmission gates, respectively. Each startup branch replicates the output current of the positive temperature coefficient generator module proportionally and superimposes it at the output node of the bandgap reference voltage to generate a bandgap reference voltage that meets the requirements. The specific replication ratio can be set and adjusted according to specific application requirements and is not limited here.

[0033] In one embodiment, the reference voltage generation module includes: an eighth transistor M8, a ninth transistor M9, a twelfth transistor M12, a fifth transistor Q5, a third resistor R3, and a seventh resistor R7;

[0034] The gate of the eighth transistor M8 is connected to the second output terminal, and its source is connected to the drain of the ninth transistor M9. The drain is connected to the collector of the fifth transistor Q5 as the output node. The gate of the ninth transistor M9 is connected to the first output terminal, and its source is connected to the power supply voltage VDD. The base and collector of the fifth transistor Q5 are shorted, and its emitter is connected to one end of the third resistor R3 and one end of the seventh resistor R7, respectively. The other end of the third resistor R3 is grounded to GND. The other end of the seventh resistor R7 is connected to the drain of the twelfth transistor M12. The source of the twelfth transistor M12 is grounded to GND, and its gate is connected to the third enable signal EN1 (i.e., one of the differential enable signals).

[0035] In one embodiment, the current output module includes: a first enable branch, a first branch, a second branch, and a current output branch. The enable branch receives a first enable signal ENN to provide a first bias voltage to the first branch. The first branch proportionally replicates the output of the positive temperature coefficient generation module to generate a negative temperature coefficient voltage. The second branch proportionally replicates the output of the positive temperature coefficient generation module to generate a positive temperature coefficient voltage and superimposes it with the negative temperature coefficient voltage, so that the current I2 of the first branch has a zero temperature coefficient. The current output branch mirrors and proportionally replicates the current of the first branch as the zero temperature coefficient output current for output. This output is connected to an external circuit via a corresponding node PIBO.

[0036] In one embodiment, the current output module includes an eleventh transistor M11, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a sixth transistor Q6, and a seventh transistor Q7.

[0037] The gate and drain of the eleventh transistor M11 are shorted, and connected to the drain of the nineteenth transistor M19 through the fourth resistor R4. The source is connected to the power supply voltage VDD. The gate of the nineteenth transistor M19 is connected to the first enable signal ENN, and the source is grounded to GND. The gate of the thirteenth transistor M13 is connected to the gate of the eleventh transistor M11 and the gate of the eighteenth transistor M18. The source is connected to the drain of the fourteenth transistor M14, and the drain is connected to the collector of the sixth transistor Q6. The source of the fourteenth transistor M14 is connected to the power supply voltage VDD, and the gate is connected to the drain of the thirteenth transistor M13 and the gate of the seventeenth transistor M17. The gate of the fifteenth transistor M15 is connected to... The second output terminal has its source connected to the power supply voltage VDD, and its drain connected to the source of the sixteenth transistor M16. The gate of the sixteenth transistor M16 is connected to the first output terminal. The drain is connected to the base of the sixth transistor Q6 and the collector of the seventh transistor Q7. The emitter of the sixth transistor Q6 is connected to one end of the fifth resistor R5 and the base of the seventh transistor Q7. The emitter of the seventh transistor Q7 is grounded through the sixth resistor R6. The other end of the fifth resistor R5 is grounded. The source of the seventeenth transistor M17 is connected to the power supply voltage VDD, and its drain is connected to the source of the eighteenth transistor M18. The drain of the eighteenth transistor M18 serves as the output terminal PIBO of the zero temperature coefficient output current.

[0038] The nineteenth transistor M19, the fourth resistor R4, and the eleventh transistor M11 form the first enable branch; the thirteenth transistor M13, the fourteenth transistor M14, the sixth transistor Q6, and the fifth resistor R5 form the first branch; the fifteenth transistor M15, the sixteenth transistor M16, the seventh transistor Q7, and the sixth resistor R6 form the second branch; and the seventeenth transistor M18 and the eighteenth transistor M18 form the current output branch.

[0039] Please see Figure 2 , Figure 2This is a circuit diagram of an enable signal generation circuit according to one embodiment of this application. In one embodiment, the circuit further includes an enable signal generation circuit, which includes a first inverter, a second inverter INV1, a third inverter INV2, a capacitor C, and a differential output buffer. The input terminal of the first inverter is connected to the first enable signal ENN, and its output terminal is connected to the input terminal of the second inverter INV1 and the first input terminal A of the third inverter INV2, respectively. The output terminal of the second inverter INV1 serves as the output node of the second enable signal EN and is connected to the second input terminal AN of the third inverter. The output terminal ZN of the third inverter INV2 is connected to one end of the capacitor C and the input terminal of the differential output buffer, respectively. The other end of the capacitor C is grounded, and the differential output buffer outputs the differential enable signal.

[0040] Specifically, Q1-Q4 and R2 form two feedback loops. Loop 1, from the base of Q3 to the emitter of Q1, then to the base of Q2, and finally to the base of Q3, constitutes negative feedback. Loop 2, from the base of Q3 to the base of Q4, and finally to the base of Q3, constitutes positive feedback. For the loops to be stable, the negative feedback must be greater than the positive feedback, ensuring that the loop of the positive temperature coefficient generating module is negative feedback.

[0041] The working principle of the positive temperature coefficient generation module is as follows:

[0042] The current mirror formed by transistors Q1 and Q2 forces the base voltages of Q1 and Q2 to be equal, therefore...

[0043] V BE1 +V BE4 +R2·I1=V BE3 +V BE2 (1)

[0044] Where VBE1, VBE2, VBE3, and VBE4 are the base-emitter voltages of transistors Q1, Q2, Q3, and Q4, respectively; R2 is the resistance of resistor R2; and I1 is the current flowing through resistor R2. Transforming the above equation yields:

[0045] R2·I1=[(V BE2 -V BE1 )+(V BE3 -V BE4 (2)

[0046] Right now:

[0047] R2·I1=V T ·[lnm+lnn]=V T ·ln(mn) (3)

[0048] Therefore, the expression for the PTAT current is:

[0049]

[0050] Among them, such as Figure 1 As shown, m is the area ratio of Q1 to Q2, n is the area ratio of Q4 to Q3, and V T This is thermal voltage.

[0051] The principle of generating the bandgap reference voltage is as follows:

[0052] Current mirrors M8-M9 proportionally replicate the PTAT current, which flows through resistor R3 to form the PTAT voltage. Therefore, the bandgap reference voltage output by the reference voltage generation module is:

[0053]

[0054] In the formula, VBG is the bandgap output voltage, VBE5 is the base-emitter voltage of transistor Q5, R3 is the resistance value of resistor R3, and V T denoted as thermal voltage, and 'a' is the ratio of the width-to-length ratio of current mirrors M8-M9 to that of current mirrors M4-M5.

[0055] The principle of PIBO zero temperature coefficient current generation is as follows:

[0056] Current mirrors M15-M16 proportionally replicate the PTAT current, which flows through resistor R6 to form the PTAT voltage. Therefore, the voltage across R5 is a negative temperature coefficient voltage plus a positive temperature coefficient voltage. When the positive and negative temperature coefficient voltages are superimposed in an appropriate ratio, a zero temperature coefficient voltage can be generated. Therefore, the current I2 flowing through current mirrors M13-M14 is a zero temperature coefficient current, and its value is:

[0057]

[0058] Substituting the IPTAT current expression into the above equation, we get:

[0059]

[0060] In the formula, b is the ratio of the width to length of current mirrors M13-M14 and M4-M5. From the above formula, it can be seen that by setting appropriate resistance values ​​for R6 and R5, a zero-temperature coefficient current I2 can be obtained. The output current I_BIAS of PIBO copies the current I2 of current mirrors M13-M14; therefore, PIBO is a zero-temperature coefficient current.

[0061] Based on the technical solutions of the embodiments of this application above, the Quad Cross Coupled structure can save area well, has a simple structure, does not require the introduction of operational amplifiers, and therefore does not introduce additional device noise. The overall noise performance is better and can be widely used in noise-sensitive circuits such as phase-locked loops and oscillators.

[0062] To further verify the above-mentioned advantages of the present invention, with m=2, n=6, a=2.5, and b=1, and using 3.3V as the power supply voltage, the bandgap reference circuit proposed in the embodiments of this application was implemented. The circuit was constructed and simulated. Figure 3 and Figure 4 These are the temperature characteristic curves of the bandgap reference voltage and the zero-temperature coefficient current, respectively. Figure 5 This refers to the PSRR characteristic of a bandgap reference circuit.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bandgap reference circuit without operational amplifiers, characterized in that, The circuit includes: A positive temperature coefficient generation module generates a negative feedback current with a positive temperature coefficient through a cross-coupled structure composed of four transistors. The reference voltage generation module generates a positive temperature coefficient voltage on an internal resistor by mirroring the output of the positive temperature coefficient generation module, and superimposes a negative temperature coefficient voltage to obtain a bandgap reference voltage with zero temperature coefficient. The startup module is connected to the output of the positive temperature coefficient generation module. It injects current into the reference voltage generation module during the initial stage of bandgap reference voltage establishment, thereby accelerating the startup of the reference voltage generation module, and shuts down after startup is completed. The current output module generates a zero-temperature coefficient output current by mirroring the output of the positive temperature coefficient generation module.

2. The op-amp-free bandgap reference circuit according to claim 1, characterized in that, The current output module includes: a first enable branch, a first branch, a second branch, and a current output branch. The enable branch receives a first enable signal to provide a first bias voltage to the first branch. The first branch proportionally replicates the output of the positive temperature coefficient generation module to generate a negative temperature coefficient voltage. The second branch proportionally replicates the output of the positive temperature coefficient generation module to generate a positive temperature coefficient voltage and superimposes it with the negative temperature coefficient voltage, so that the current of the first branch has a zero temperature coefficient. The current output branch mirrors and proportionally replicates the current of the first branch as the zero temperature coefficient output current for output.

3. The op-amp-free bandgap reference circuit according to claim 2, characterized in that, The positive temperature coefficient generating module includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first resistor, a second resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor; The gate of the second transistor is connected to a second enable signal, its source is grounded, and its drain is connected to one end of the first resistor. The drain of the first transistor is connected to the other end of the first resistor, its source is connected to the power supply voltage, and its gate is connected to the gate of the third transistor and also to the gate of the fourth transistor. The source of the third transistor is connected to the power supply voltage, and its drain is connected to the collector of the first transistor. The gate of the fourth transistor serves as the first output terminal, its source is connected to the drain of the fifth transistor, and its drain is connected to the gate of the fifth transistor as the second output terminal. The source of the fifth transistor is connected to the power supply voltage. Voltage; the base and collector of the first transistor are shorted and connected to the collector of the second transistor, and the emitter is connected to the collector of the third transistor; the collector of the second transistor is connected to the drain of the fourth transistor, and the emitter is connected to the collector of the fourth transistor; the collector of the third transistor is connected to the base of the fourth transistor, the base is connected to the collector of the fourth transistor, and the emitter is grounded; the emitter of the fourth transistor is grounded through the second resistor; wherein the first transistor, the second transistor, the third transistor, and the fourth transistor form the cross-coupled structure.

4. The op-amp-free bandgap reference circuit according to claim 3, characterized in that, The startup module includes a first transmission gate, a second transmission gate, and multiple parallel startup branches composed of current mirror units. The two transistors in each current mirror unit are started by the first transmission gate and the second transmission gate, respectively, so that the corresponding current mirror unit replicates the negative feedback current proportionally and merges it into the output node of the bandgap reference voltage. The first transmission gate and the second transmission gate are both started by the differential enable signal.

5. The op-amp-free bandgap reference circuit according to claim 4, characterized in that, The reference voltage generation module includes: an eighth transistor, a ninth transistor, a twelfth transistor, a fifth transistor, a third resistor, and a seventh resistor; The gate of the eighth transistor is connected to the second output terminal, the source is connected to the drain of the ninth transistor, and the drain is connected to the collector of the fifth transistor as the output node; the gate of the ninth transistor is connected to the first output terminal, and the source is connected to the power supply voltage; the base and collector of the fifth transistor are shorted, and the emitter is connected to one end of the third resistor and one end of the seventh resistor, respectively; the other end of the third resistor is grounded; the other end of the seventh resistor is connected to the drain of the twelfth transistor; the source of the twelfth transistor is grounded, and the gate is connected to the third enable signal.

6. The op-amp-free bandgap reference circuit according to claim 4, characterized in that, The current output module includes an eleventh transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, and a seventh transistor; The gate and drain of the eleventh transistor are shorted together and connected to the drain of the nineteenth transistor through the fourth resistor; the source is connected to the power supply voltage. The gate of the nineteenth transistor is connected to the first enable signal, and the source is grounded. The gate of the thirteenth transistor is connected to the gate of the eleventh transistor and the gate of the eighteenth transistor, respectively; the source is connected to the drain of the fourteenth transistor, and the drain is connected to the collector of the sixth transistor. The source of the fourteenth transistor is connected to the power supply voltage, and the gate is connected to the drain of the thirteenth transistor and the gate of the seventeenth transistor, respectively. The gate of the fifteenth transistor is connected to the second enable signal. The source of the transistor is connected to the power supply voltage, and the drain is connected to the source of the sixteenth transistor. The gate of the sixteenth transistor is connected to the first output terminal. The drain is connected to the base of the sixth transistor and the collector of the seventh transistor. The emitter of the sixth transistor is connected to one end of the fifth resistor and the base of the seventh transistor. The emitter of the seventh transistor is grounded through the sixth resistor. The other end of the fifth resistor is grounded. The source of the seventeenth transistor is connected to the power supply voltage, and the drain is connected to the source of the eighteenth transistor. The drain of the eighteenth transistor serves as the output terminal of the zero-temperature coefficient output current. The nineteenth transistor, the fourth resistor, and the eleventh transistor form the first enable branch; the thirteenth transistor, the fourteenth transistor, the sixth transistor, and the fifth resistor form the first branch; and the fifteenth transistor, the sixteenth transistor, the seventh transistor, and the sixth resistor form the second branch. The seventeenth transistor and the eighteenth transistor constitute the current output branch.

7. The op-amp-free bandgap reference circuit according to claim 6, characterized in that, The circuit further includes an enable signal generation circuit, which includes a first inverter, a second inverter, a third inverter, a capacitor, and a differential output buffer. The input terminal of the first inverter is connected to the first enable signal, and its output terminal is connected to the input terminal of the second inverter and the first input terminal of the third inverter. The output terminal of the second inverter serves as the output node of the second enable signal and is connected to the second input terminal of the third inverter. The output terminal of the third inverter is connected to one end of the capacitor and the input terminal of the differential output buffer. The other end of the capacitor is grounded, and the differential output buffer outputs the differential enable signal.

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