Band-gap reference voltage source

Abstract

The invention relates to the technical field of integrated circuits, in particular to a band-gap reference voltage source, which comprises a high-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit, a low-order compensation circuit and a low-order reference circuit, the band-gap reference circuit is used for generating a positive temperature coefficient voltage and a negative temperature coefficient voltage, performing first-order temperature compensation on the negative temperature coefficient voltage by using the positive temperature coefficient voltage, performing high-order curvature compensation on the negative temperature coefficient voltage based on the target compensation current, determining the compensated voltage as a reference voltage and outputting the reference voltage; according to the band-gap reference voltage source, high-order compensation is introduced through the sub-threshold MOS tube, the negative temperature coefficient voltage can be well reduced, the reference voltage with the temperature coefficient approximate to zero is obtained, and practicability is high.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a bandgap reference voltage source. Background Technology

[0002] The bandgap reference voltage source (BGR) is a key module in analog integrated circuits and is widely used in power management chips, data converters, and sensor interfaces. Its core function is to provide a stable reference voltage that is independent of power supply voltage, process deviations, and temperature changes.

[0003] However, existing bandgap reference voltage sources still face many challenges in practical applications, such as: excessively high temperature coefficient, making it difficult to meet the requirements of high-precision systems (such as medical electronics and precision sensors), and insufficient power supply rejection ratio (PSRR), resulting in weak immunity to power supply interference. Summary of the Invention

[0004] This invention provides a bandgap reference voltage source to solve the problem of excessively high temperature coefficient in existing bandgap reference voltage sources.

[0005] The present invention provides a bandgap reference voltage source, the method comprising: a high-order compensation circuit, which utilizes a MOS transistor operating in subthreshold mode to generate a target compensation current that has a high-order nonlinear relationship with temperature, and outputs the target compensation current to the bandgap reference circuit;

[0006] A bandgap reference circuit generates a positive temperature coefficient voltage and a negative temperature coefficient voltage. The positive temperature coefficient voltage is used to perform first-order temperature compensation on the negative temperature coefficient voltage, and based on the target compensation current, higher-order curvature compensation is performed on the negative temperature coefficient voltage. The compensated voltage is then determined as the reference voltage and output.

[0007] In one embodiment of the present invention, the bandgap reference circuit includes:

[0008] A differential pair module generates a positive temperature coefficient voltage through the current density difference of a proportional device and a negative temperature coefficient voltage based on the on-state voltage of one of the bipolar transistors in the proportional device, the proportional device comprising at least one pair of bipolar transistors of proportional size.

[0009] The first operational amplifier negative feedback module has its inverting input connected to the collector of a bipolar transistor of a first size in the proportional device, its non-inverting input connected to the collector of a bipolar transistor of a second size in the proportional device, and its output connected to the input of the differential pair module. The output of the first operational amplifier negative feedback module is used to output the reference voltage, and the first size and the second size are proportional.

[0010] In one embodiment of the present invention, the differential pair module includes: a first resistor, a second resistor, a first bipolar transistor, a second bipolar transistor, a third bipolar transistor, a fourth bipolar transistor, and a third resistor. The resistance values ​​of the first resistor and the second resistor are equal. The first bipolar transistor and the second bipolar transistor have a preset emitter area ratio. The third bipolar transistor and the fourth bipolar transistor have the same emitter area ratio. The first operational amplifier negative feedback module includes a first operational amplifier and a first MOS transistor, wherein the first MOS transistor is an NMOS transistor.

[0011] The inverting input of the first operational amplifier is connected to the collector of the first bipolar transistor. The non-inverting input of the first operational amplifier is connected to the collector of the second bipolar transistor and the base of the third bipolar transistor. The collector of the first operational amplifier is connected to its base. The output of the first operational amplifier is connected to the gate of the first MOS transistor. The drain of the first MOS transistor is connected to the target voltage. The source of the first MOS transistor, the first resistor, the collector and emitter of the first bipolar transistor, the collector and emitter of the third bipolar transistor, and the third resistor are sequentially connected to ground. The source of the first MOS transistor, the second resistor, the collector and emitter of the second bipolar transistor, the collector and emitter of the fourth bipolar transistor, and the third resistor are sequentially connected to ground. The collector of the second bipolar transistor is connected to its base. The connection point between the source of the first MOS transistor and the first resistor is the output of the bandgap reference circuit. The base of the fourth bipolar transistor is connected to the output of the bandgap reference circuit.

[0012] In one embodiment of the present invention, the bandgap reference circuit further includes a fourth resistor and a fifth resistor. The source of the first MOS transistor, the fourth resistor, the fifth resistor, and the first resistor are connected in sequence. The connection point between the fourth resistor and the fifth resistor is the output terminal of the bandgap reference circuit.

[0013] In one embodiment of the present invention, the higher-order compensation circuit includes:

[0014] An initial compensation current generation module is used to connect to the target voltage and generate an initial compensation current;

[0015] A current mirror module is used to copy the initial compensation current to the first compensation current generation module and the second compensation current generation module;

[0016] The second operational amplifier negative feedback module has its non-inverting input terminal connected to the output terminal of the bandgap reference circuit, and its inverting input terminal connected to the voltage divider module.

[0017] The voltage divider module is used to perform voltage division and control the conduction state of the first compensation current generation module and the second compensation current generation module based on the voltage after voltage division.

[0018] The first compensation current generation module determines the conduction state based on the current output by the voltage divider module, and generates the first compensation current from the initial compensation current through a MOS transistor operating in subthreshold mode.

[0019] The second compensation current generation module determines the conduction state based on the current output by the voltage divider module, and generates a second compensation current from the initial compensation current through a MOS transistor operating in subthreshold mode. The sum of the first compensation current and the second compensation current is the target compensation current.

[0020] In one embodiment of the present invention, the initial compensation current generation module includes a fifth bipolar transistor and a sixth resistor; the current mirror module includes a second MOSFET, a third MOSFET, and a fourth MOSFET; the second operational amplifier negative feedback module includes a second operational amplifier and a fifth MOSFET, wherein the fifth MOSFET is an NMOS transistor; the voltage divider module includes a seventh resistor, an eighth resistor, and a ninth resistor; the first compensation current generation module includes a sixth MOSFET and a seventh MOSFET; the second compensation current generation module includes an eighth MOSFET and a ninth MOSFET; and the second MOSFET, the third MOSFET, the fourth MOSFET, the sixth MOSFET, the seventh MOSFET, the eighth MOSFET, and the ninth MOSFET are all PMOS transistors.

[0021] The source of the second MOSFET is connected to the target voltage and is connected to the source of the third MOSFET, the source of the fourth MOSFET, and the drain of the fifth MOSFET. The gate of the second MOSFET is connected to the gate of the third MOSFET and the gate of the fourth MOSFET. The drain of the second MOSFET, the collector and emitter of the fifth bipolar transistor, and the first terminal of the sixth resistor are connected in sequence. The second terminal of the sixth resistor is connected to the drain of the seventh MOSFET and the drain of the ninth MOSFET. The second terminal of the sixth resistor is also connected to the ninth resistor, the eighth resistor, the seventh resistor, and the source of the fifth MOSFET in sequence. The non-inverting input of the second operational amplifier is connected to the output of the bandgap reference circuit, its inverting input is connected to the source of the fifth MOSFET, and its output is connected to the gate of the fifth MOSFET. The drain of the third MOSFET is connected to the... The source of the sixth MOSFET is connected to the source of the seventh MOSFET. The drain of the fourth MOSFET is connected to the source of the eighth MOSFET and the source of the ninth MOSFET. The connection point between the seventh resistor and the eighth resistor is the first node, and the connection point between the eighth resistor and the ninth resistor is the second node. The first node is connected to the gate of the eighth MOSFET, and the second node is connected to the gate of the seventh MOSFET. The gate of the sixth MOSFET is connected to the gate of the ninth MOSFET. The end of the third resistor connected to the third bipolar transistor is its first terminal. The drain of the eighth MOSFET and the drain of the sixth MOSFET are connected to the second terminal of the third resistor. The emitters of the third bipolar transistor and the fourth bipolar transistor are connected to the gate of the sixth MOSFET. The base of the fourth bipolar transistor is connected to the base of the fifth bipolar transistor.

[0022] In one embodiment of the present invention, the bandgap reference voltage source further includes a trimming circuit;

[0023] The third resistor is connected to ground through the adjustment circuit. The adjustment circuit controls its own resistance value based on the input digital signal to adjust the positive temperature coefficient current, thereby completing the adjustment of the positive temperature coefficient voltage.

[0024] In one embodiment of the present invention, the adjustment circuit includes a plurality of adjustment modules connected in parallel. Each adjustment module includes a switching unit and a target resistor. The input terminal of the switching unit is the input terminal of the adjustment module. The switching unit and the target resistor are connected to ground. The switching unit is turned on when it receives a high-level digital signal and turned off when it receives a low-level digital signal. The resistance values ​​of the target resistors in the plurality of adjustment modules show an increasing trend.

[0025] The switching unit includes a first target PMOS transistor and a second target PMOS transistor. The source of the first target PMOS transistor and the source of the second target PMOS transistor are respectively connected to the third resistor. The gate of the first target PMOS transistor and the gate of the second target PMOS transistor are both used to receive the digital signal. The drain of the first target PMOS transistor and the drain of the second target PMOS transistor are respectively connected to the corresponding target resistor.

[0026] Alternatively, the switching unit includes a third target PMOS transistor, the source of which is connected to the third resistor, the gate of which is used to receive the digital signal, and the drain of which is connected to the corresponding target resistor.

[0027] Alternatively, the switching unit includes a fourth target PMOS transistor and a fifth target PMOS transistor. The source of the fourth target PMOS transistor is connected to the third resistor, the gate of the fourth target PMOS transistor is connected to the source of the fifth target PMOS transistor, the gate of the fifth target PMOS transistor is used to receive the digital signal, and the drains of the fourth target PMOS transistor and the fifth target PMOS transistor are respectively connected to the corresponding target resistors.

[0028] In one embodiment of the present invention, the bandgap reference voltage source further includes a low-pass filter circuit, the low-pass filter circuit includes a first low-pass filter module and a second low-pass filter module, the first low-pass filter module includes a tenth resistor, a first capacitor, and a tenth MOS transistor, the tenth MOS transistor being an NMOS transistor, and the second low-pass filter module includes an eleventh resistor and a second capacitor.

[0029] The first end of the tenth resistor is connected to a preset power supply voltage, the second end of the tenth resistor and the first capacitor are connected to ground, the second end of the tenth resistor is connected to the gate of the tenth MOS transistor, the drain of the tenth MOS transistor is connected to the power supply voltage, and the source of the tenth MOS transistor is connected to the drain of the first MOS transistor, so as to output the target voltage after low-pass filtering to the first MOS transistor.

[0030] The first end of the eleventh resistor is connected to the output end of the bandgap reference circuit, and the second end of the eleventh resistor, the second capacitor, and the gate of the fourth bipolar transistor are connected in sequence.

[0031] In one embodiment of the present invention, the bandgap reference voltage source further includes:

[0032] The starting circuit is connected to the power supply voltage to power on the circuit. During the power-on phase, the circuit is forced to leave the zero-current degeneracy state.

[0033] A bias circuit, whose input is connected to the startup circuit, is used to provide a bias current independent of the power supply voltage. The bias current is replicated by a current mirror and output to the bandgap reference circuit and the higher-order compensation circuit respectively, so that the bandgap reference circuit and the higher-order compensation circuit start working.

[0034] The beneficial effects of this invention are as follows: The bandgap reference voltage source provided by this invention incorporates a high-order compensation circuit. This high-order compensation circuit utilizes a MOS transistor operating in subthreshold mode to generate a target compensation current that exhibits a high-order nonlinear relationship with temperature, and outputs the target compensation current to the bandgap reference circuit. Furthermore, the bandgap reference circuit generates a positive temperature coefficient voltage and a negative temperature coefficient voltage. The positive temperature coefficient voltage is used to perform first-order temperature compensation on the negative temperature coefficient voltage, and based on the target compensation current, high-order curvature compensation is performed on the negative temperature coefficient voltage. The compensated voltage is then determined as the reference voltage and output. This bandgap reference voltage source, by introducing high-order compensation using a subthreshold MOS transistor, can effectively reduce the negative temperature coefficient voltage, obtaining a reference voltage with a temperature coefficient approximately zero, and is highly feasible. Attached Figure Description

[0035] Figure 1 A schematic diagram of the structure of a bandgap reference voltage source provided in an embodiment of the present invention. Figure 1 ;

[0036] Figure 2 This is a schematic diagram of the adjustment circuit in a bandgap reference voltage source provided in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of the structure of a bandgap reference voltage source provided in an embodiment of the present invention. Figure 2 ;

[0038] Figure 4 This is a simulation diagram illustrating the relationship between the reference voltage output by a bandgap reference voltage source and temperature, provided in an embodiment of the present invention.

[0039] Figure 5 This is a simulation diagram of the PSRR (Power Supply Rejection Ratio) of a bandgap reference voltage source under full PVT (Process, Voltage, Temperature) according to an embodiment of the present invention. Detailed Implementation

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0041] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0043] The following combination Figures 1 to 5 The bandgap reference voltage source provided by this invention will be explained and described.

[0044] Please refer to Figure 1 , Figure 1 A schematic diagram of the structure of a bandgap reference voltage source provided in an embodiment of the present invention. Figure 1 ,like Figure 1 As shown, the bandgap reference voltage source includes:

[0045] The high-order compensation circuit utilizes a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) operating in subthreshold mode to generate a target compensation current that has a high-order nonlinear relationship with temperature, and outputs the target compensation current to the bandgap reference circuit.

[0046] A bandgap reference circuit generates a positive temperature coefficient voltage and a negative temperature coefficient voltage. The positive temperature coefficient voltage is used to perform first-order temperature compensation on the negative temperature coefficient voltage, and based on the target compensation current, higher-order curvature compensation is performed on the negative temperature coefficient voltage. The compensated voltage is then determined as the reference voltage VREF and output.

[0047] It should be noted that first-order temperature compensation may include: multiplying the positive temperature coefficient voltage by a preset proportional coefficient to obtain a proportional voltage value; and superimposing the proportional voltage value with the negative temperature coefficient voltage to obtain a superimposed voltage value, thereby completing the first-order temperature compensation.

[0048] It should also be noted that higher-order curvature compensation may include: multiplying the target compensation current by a preset resistance value to obtain a target compensation voltage; adding the target compensation voltage to the voltage value obtained by superposition of the first-order temperature compensation to obtain the voltage after higher-order curvature compensation; and determining the voltage as the reference voltage VREF.

[0049] Understandably, by setting up the above-mentioned high-order circuit, it is possible to introduce high-order compensation through a MOSFET operating in subthreshold mode, thereby effectively reducing the negative temperature coefficient voltage and obtaining a reference voltage VREF with a temperature coefficient of approximately zero. This approach is highly feasible and has a low cost.

[0050] In some embodiments, the bandgap reference circuit includes:

[0051] A differential pair module generates a positive temperature coefficient voltage through the current density difference of a proportional device and a negative temperature coefficient voltage based on the on-state voltage of one of the bipolar transistors in the proportional device, the proportional device comprising at least one pair of bipolar transistors of proportional size.

[0052] The first operational amplifier negative feedback module has its inverting input connected to the collector of a bipolar transistor of a first size in the proportional device, its non-inverting input connected to the collector of a bipolar transistor of a second size in the proportional device, and its output connected to the input of the differential pair module. The output of the first operational amplifier negative feedback module is used to output the reference voltage VREF, and the first size and the second size are proportional.

[0053] It should be noted that the above settings can effectively achieve the output of the reference voltage VREF, which has a temperature coefficient of approximately zero.

[0054] In some embodiments, the differential pair module includes: a first resistor R1, a second resistor R2, a first bipolar transistor Q1, a second bipolar transistor Q2, a third bipolar transistor Q3, a fourth bipolar transistor Q4, and a third resistor R3. The first resistor R1 and the second resistor R2 have equal resistance values. The first bipolar transistor Q1 and the second bipolar transistor Q2 have a preset emitter area ratio. The third bipolar transistor Q3 and the fourth bipolar transistor Q4 have the same emitter area ratio. The first operational amplifier negative feedback module includes a first operational amplifier AMP1 and a first MOS transistor M1, wherein the first MOS transistor M1 is an NMOS transistor.

[0055] The inverting input of the first operational amplifier AMP1 is connected to the collector of the first bipolar transistor Q1. The non-inverting input of the first operational amplifier AMP1 is connected to the collector of the second bipolar transistor Q2 and the base of the third bipolar transistor Q3. The collector of the first operational amplifier AMP1 is connected to its base. The output of the first operational amplifier AMP1 is connected to the gate of the first MOSFET M1. The drain of the first MOSFET M1 is connected to the target voltage VDD1. The source of the first MOSFET M1, the first resistor R1, the collector of the first bipolar transistor Q1, and the output of the first MOSFET M1 are connected to the gate of the first MOSFET M1. The emitter, collector, emitter of the third bipolar transistor Q3, and the third resistor R3 are sequentially connected to ground. The source of the first MOS transistor M1, the second resistor R2, the collector, emitter of the second bipolar transistor Q2, the collector, emitter of the fourth bipolar transistor Q4, and the third resistor R3 are sequentially connected to ground. The collector of the second bipolar transistor Q2 is connected to its base. The connection point between the source of the first MOS transistor M1 and the first resistor R1 is the output terminal of the bandgap reference circuit. The base of the fourth bipolar transistor Q4 is connected to the output terminal of the bandgap reference circuit.

[0056] It should be noted that the first bipolar transistor Q1 and the second bipolar transistor Q2 are the same type of transistor and have a preset size ratio (this size ratio can be the emitter area ratio, such as 8:1, etc.). The third bipolar transistor Q3 and the fourth bipolar transistor Q4 are also the same type of transistor and have a preset size ratio. Because the first operational amplifier AMP1 has virtual short and virtual open characteristics, the voltage at the non-inverting input terminal and the voltage at the inverting input terminal of the first operational amplifier AMP1 are clamped to approximately equal voltages. A base-emitter voltage difference ΔV exists between the first bipolar transistor Q1 and the second bipolar transistor Q2. BE The third bipolar transistor Q3 and the fourth bipolar transistor Q4 also have a base-emitter voltage difference ΔV. BE The sum of the two voltage differences is 2ΔV BE The 2ΔV BE The current is applied across the second resistor R2. Since the resistances of the first resistor R1 and the second resistor R2 are equal, the current flowing through the two branches (the branch containing the first resistor R1 and the branch containing the second resistor R2) is equal (I1 = I2 = 2V). T ln N / R2), where I1 represents the current flowing through the first resistor R1, I2 represents the current flowing through the second resistor R2, and V TLet N represent the thermal voltage, and let N represent the emitter area ratio, which can be 8, etc. ln represents the natural logarithm. I1 and I2 flow through the third resistor R3, the fifth resistor, etc., thus generating a positive temperature coefficient voltage. This positive temperature coefficient voltage, combined with the negative temperature coefficient voltage, achieves first-order temperature compensation for the bandgap reference voltage source.

[0057] Understandably, by setting up the above-mentioned devices, the output of the reference voltage VREF can be achieved relatively well.

[0058] In some embodiments, the bandgap reference circuit further includes a fourth resistor and a fifth resistor, wherein the source of the first MOS transistor M1, the fourth resistor, the fifth resistor, and the first resistor R1 are connected in sequence, and the connection point between the fourth resistor and the fifth resistor is the output terminal of the bandgap reference circuit.

[0059] It should be noted that the connection point between the fourth and fifth resistors is used to output the reference voltage VREF. By setting the fourth and fifth resistors, the voltage output by the first MOSFET M1 can be divided, thereby outputting a highly controllable reference voltage VREF. It can be understood that by adjusting the resistance values ​​of the fourth and / or fifth resistors, the voltage at their connection point can be adjusted, resulting in an output reference voltage VREF with an approximately zero temperature coefficient.

[0060] In some embodiments, the higher-order compensation circuit includes:

[0061] An initial compensation current generation module is used to connect to the target voltage VDD1 and generate an initial compensation current;

[0062] A current mirror module is used to copy the initial compensation current to the first compensation current generation module and the second compensation current generation module;

[0063] The second operational amplifier negative feedback module has its non-inverting input terminal connected to the output terminal of the bandgap reference circuit, and its inverting input terminal connected to the voltage divider module.

[0064] The voltage divider module is used to perform voltage division and control the conduction state of the first compensation current generation module and the second compensation current generation module based on the voltage after voltage division.

[0065] The first compensation current generation module determines the conduction state based on the current output by the voltage divider module, and generates the first compensation current from the initial compensation current through a MOS transistor operating in subthreshold mode.

[0066] The second compensation current generation module determines the conduction state based on the current output by the voltage divider module, and generates a second compensation current from the initial compensation current through a MOS transistor operating in subthreshold mode. The sum of the first compensation current and the second compensation current is the target compensation current.

[0067] Understandably, by setting the above modules in the high-order compensation circuit, it is easy to realize high-order curvature compensation.

[0068] In some embodiments, the initial compensation current generation module includes a fifth bipolar transistor Q5 and a sixth resistor R6; the current mirror module includes a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4; the second operational amplifier negative feedback module includes a second operational amplifier AMP2 and a fifth MOSFET M5, wherein the fifth MOSFET M5 is an NMOS transistor; the voltage divider module includes a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; the first compensation current generation module includes a sixth MOSFET M6 and a seventh MOSFET M7; the second compensation current generation module includes an eighth MOSFET M8 and a ninth MOSFET M9; and the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 are all PMOS transistors.

[0069] The source of the second MOSFET M2 is connected to the target voltage VDD1 and is connected to the source of the third MOSFET M3, the source of the fourth MOSFET M4, and the drain of the fifth MOSFET M5. The gate of the second MOSFET M2 is connected to the gate of the third MOSFET M3 and the gate of the fourth MOSFET M4. The drain of the second MOSFET M2, the collector and emitter of the fifth bipolar transistor Q5, and the first terminal of the sixth resistor R6 are connected in sequence. The second terminal of the sixth resistor R6 is connected to the drain of the seventh MOSFET M7 and the drain of the ninth MOSFET M9. The second terminal of the sixth resistor R6 is also connected in sequence to the ninth resistor R9, the eighth resistor R8, the seventh resistor R7, and the source of the fifth MOSFET M5. The non-inverting input of the second operational amplifier AMP2 is connected to the output of the bandgap reference circuit, its inverting input is connected to the source of the fifth MOSFET M5, and its output is connected to the gate of the fifth MOSFET M5. The drain of the third MOSFET M3 is connected to the source of the fourth MOSFET M4 and the drain of the fifth MOSFET M5. The source of the sixth MOSFET M6 is connected to the source of the seventh MOSFET M7. The drain of the fourth MOSFET M4 is connected to the source of the eighth MOSFET M8 and the source of the ninth MOSFET M9, respectively. The connection point between the seventh resistor R7 and the eighth resistor R8 is the first node, and the connection point between the eighth resistor R8 and the ninth resistor R9 is the second node. The first node is connected to the gate of the eighth MOSFET M8, and the second node is connected to the gate of the seventh MOSFET M7. The gate of the sixth MOSFET M6 is connected to the gate of the ninth MOSFET M9. The end of the third resistor R3 connected to the third bipolar transistor Q3 is its first terminal. The drain of the eighth MOSFET M8 and the drain of the sixth MOSFET M6 are respectively connected to the second terminal of the third resistor R3. The emitters of the third bipolar transistor Q3 and the fourth bipolar transistor Q4 are respectively connected to the gate of the sixth MOSFET M6. The base of the fourth bipolar transistor Q4 is connected to the base of the fifth bipolar transistor Q5.

[0070] It should be noted that the fifth bipolar transistor Q5 and the sixth resistor R6 are used to generate the initial compensation current I3. The second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 form a current mirror structure to replicate the initial compensation current I3 to the third MOSFET M3 and the fourth MOSFET M4. That is, the current flowing through the third MOSFET M3 and the fourth MOSFET M4 is equal. Therefore:

[0071] I A =I B =I3=I D8 +I D9 =I D6 +I D7

[0072] Among them, I A I represents the current flowing through the third MOSFET M3. BI represents the current flowing through the fourth MOSFET M4. D8 I represents the drain current of the eighth MOSFET M8. D9 I represents the drain current of the ninth MOSFET M9. D6 I represents the drain current of the sixth MOSFET M6. D7 This represents the drain current of the seventh MOSFET M7.

[0073] The second operational amplifier AMP2 and the fifth MOS transistor M5 form a negative feedback structure. Based on the virtual short and virtual open characteristics of the second operational amplifier AMP2, it can be known that the voltage at the non-inverting input terminal of the second operational amplifier AMP2 is equal to the voltage at the inverting input terminal. Figure 1 The voltages at points D and E can be obtained by dividing the voltage at point C, as shown in the expression:

[0074]

[0075] Among them, V D This represents the voltage at point D, in V. C This represents the voltage at point C, V. E This represents the voltage at point E.

[0076] By adjusting the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9, the voltage V can be controlled. D and V E The adjustment causes the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 to operate in subthreshold mode. It should be noted that the aspect ratios of the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 are equal.

[0077] Understandably, when a MOSFET is operating in subthreshold mode, its leakage current I... D The expression for the relationship with temperature is:

[0078]

[0079] Among them, I D I represents the actual drain current of the MOSFET. D0 V represents the drain current of the MOSFET at temperature T0, W represents the channel width of the MOSFET, L represents the channel length of the MOSFET, exp represents the exponential function operation, and V GS This represents the gate-source voltage of the MOSFET, |·| indicates the absolute value calculation, V TH This represents the actual threshold voltage of the MOSFET, and n represents the subthreshold slope factor (a process-dependent constant).

[0080] Actual threshold voltage V TH The relationship with temperature is as follows:

[0081] V TH =V TH0 -δ(T-T0)

[0082] Among them, V TG0 This represents the threshold voltage of the MOSFET at temperature T0, where T represents the current temperature and δ is a preset positive positive constant.

[0083] And because I D0 =μ(T)C ox (n-1)V T 2 Where μ(T) represents the carrier mobility at the current temperature T, and its temperature-dependent expression is:

[0084]

[0085] Where μ0 represents the carrier mobility at temperature T0, and γ is a preset positive positive constant.

[0086] Based on the above expressions, the drain current expressions for the sixth MOSFET M6 and the seventh MOSFET M7 can be derived as follows:

[0087]

[0088] Among them, V A express Figure 1 The voltage at point A, V F express Figure 1 The voltage at point F in the middle.

[0089] Joint I D6 and I D7 The expression yields:

[0090]

[0091] And because:

[0092] I3 = I D6 +I D7

[0093] We can obtain:

[0094]

[0095] Similarly, the drain currents of the eighth MOSFET M8 and the ninth MOSFET M9 can be derived as follows:

[0096]

[0097] Among them, V B express Figure 1The voltage at point B, V D express Figure 1 The voltage at point D.

[0098] Joint I D8 and I D9 The expression yields:

[0099]

[0100] Among them, I D6 and I D8 (The I D6 and I D8 That is, both the first compensation current and the second compensation current in the above embodiments have a nonlinear relationship with temperature, which can be used for high-order curvature compensation. The expression for the target compensation current is:

[0101] I comp =I D6 +I D8

[0102] Among them, I comp This indicates the target compensation current.

[0103] In some embodiments, the bandgap reference voltage source further includes a trimming circuit;

[0104] The third resistor R3 is connected to ground through the adjustment circuit. The adjustment circuit controls its own resistance value based on the input digital signal to adjust the positive temperature coefficient current, thereby completing the adjustment of the positive temperature coefficient voltage.

[0105] Understandably, by adding a trimming circuit, the positive temperature coefficient current can be trimmed by adjusting the resistance, thereby optimizing the stability of the temperature coefficient.

[0106] It is worth mentioning that, Figure 1 To facilitate identification, the high-order compensation circuit and the bandgap reference circuit are roughly divided by a vertical dashed line. Figure 1 The circuit is divided into two parts. The components to the left of the dashed line belong to high-order compensation circuits. The components to the right of the dashed line, such as the first resistor R1, the second resistor R2, the first bipolar transistor Q1, the second bipolar transistor Q2, the third bipolar transistor Q3, the fourth bipolar transistor Q4, the third resistor R3, the first operational amplifier AMP1, and the first MOSFET M1, all belong to bandgap reference circuits. The second MOSFET M2, the fifth bipolar transistor Q5, and the sixth resistor R6 belong to high-order compensation circuits. (To avoid excessive overlap in the circuit diagram...) Figure 1(These components are placed to the right of the dashed line). The tenth resistor R10, the first capacitor C1, the tenth MOSFET M10, the eleventh resistor R11, and the second capacitor C2 all belong to the low-pass filter circuit (to avoid too many intersections in the circuit diagram, ...). Figure 1 (This part of the components is placed to the right of the dashed line). In addition, for ease of demonstration, the adjustment circuit is also placed to the right of the dashed line.

[0107] Please refer to Figure 2 In some embodiments, the adjustment circuit includes multiple adjustment modules connected in parallel. Each adjustment module includes a switching unit and a target resistor. The input terminal of the switching unit is the input terminal of the adjustment module. The switching unit and the target resistor are connected to ground. The switching unit is turned on when it receives a high-level digital signal and turned off when it receives a low-level digital signal. The resistance values ​​of the target resistors in the multiple adjustment modules show an increasing trend.

[0108] The switching unit includes a first target PMOS transistor and a second target PMOS transistor. The source of the first target PMOS transistor and the source of the second target PMOS transistor are respectively connected to the third resistor R3. The gate of the first target PMOS transistor and the gate of the second target PMOS transistor are both used to receive the digital signal. The drain of the first target PMOS transistor and the drain of the second target PMOS transistor are respectively connected to the corresponding target resistor.

[0109] Alternatively, the switching unit includes a third target PMOS transistor, the source of which is connected to the third resistor R3, the gate of which is used to receive the digital signal, and the drain of which is connected to the corresponding target resistor.

[0110] Alternatively, the switching unit includes a fourth target PMOS transistor and a fifth target PMOS transistor. The source of the fourth target PMOS transistor is connected to the third resistor R3, the gate of the fourth target PMOS transistor is connected to the source of the fifth target PMOS transistor, the gate of the fifth target PMOS transistor is used to receive the digital signal, and the drains of the fourth target PMOS transistor and the fifth target PMOS transistor are respectively connected to the corresponding target resistors.

[0111] It should be noted that there is a corresponding relationship between the switching units and the target resistors in the adjustment module. The resistance value of the target resistor corresponding to each switching unit can be the same or different. In this embodiment, the resistance values ​​of the target resistors corresponding to multiple switching units show an increasing trend. Furthermore, the resistance values ​​of the target resistors corresponding to multiple switching units show an increasing trend with binary weights, such as R / 8, R / 4, R / 2, R (preset standard resistance value), 2R (R+R), 4R (3R+R), 8R (7R+R), 16R (15R+R), 32R (31R+R), 64R (63R+R), etc. Figure 2 In this context, ADJN<9:0> represents the digital signals input to different switching units, including: ADJN <9> ADJN <8> ......ADJN <0> .

[0112] Understandably, by setting up the above-mentioned adjustment circuit, a high degree of flexibility in resistor adjustment can be achieved. That is, by connecting a high-level or low-level digital signal, the target resistor in multiple adjustment modules can be connected or disconnected, thereby optimizing the stability of the temperature coefficient.

[0113] In some embodiments, the bandgap reference voltage source further includes a low-pass filter circuit, which includes a first low-pass filter module and a second low-pass filter module. The first low-pass filter module includes a tenth resistor R10, a first capacitor C1, and a tenth MOS transistor M10, wherein the tenth MOS transistor M10 is an NMOS transistor. The second low-pass filter module includes an eleventh resistor R11 and a second capacitor C2.

[0114] The first terminal of the tenth resistor R10 is connected to a preset power supply voltage VDD. The second terminal of the tenth resistor R10 and the first capacitor C1 are connected to ground. The second terminal of the tenth resistor R10 is connected to the gate of the tenth MOSFET M10. The drain of the tenth MOSFET M10 is connected to the power supply voltage VDD. The source of the tenth MOSFET M10 is connected to the drain of the first MOSFET M1, so as to output the target voltage VDD1 after low-pass filtering to the first MOSFET M1.

[0115] The first end of the eleventh resistor R11 is connected to the output end of the bandgap reference circuit, and the second end of the eleventh resistor R11, the second capacitor C2, and the gate of the fourth bipolar transistor Q4 are connected in sequence.

[0116] Understandably, by setting up the above low-pass filter circuit, high-frequency noise can be effectively suppressed, and the power supply rejection capability across the entire frequency band can be optimized.

[0117] In some embodiments, the mathematical expression of the reference voltage VREF output by the bandgap reference voltage source is:

[0118]

[0119] Among them, V BE2 R represents the negative temperature coefficient voltage. o The resistance of the tuning circuit is represented by k, Boltzmann constant is represented by q, and the amount of electron charge is represented by q.

[0120] Please refer to Figure 3 In some embodiments, the bandgap reference voltage source further includes:

[0121] The startup circuit is connected to the power supply voltage VDD to power on the circuit. During the power-on phase, the circuit is forced to leave the zero-current degeneracy state.

[0122] The bias circuit, whose input is connected to the startup circuit, is used to provide a bias current independent of the power supply voltage VDD. The bias current is replicated by a current mirror and output to the bandgap reference circuit and the higher-order compensation circuit respectively, so that the bandgap reference circuit and the higher-order compensation circuit start working.

[0123] Understandably, by setting up the aforementioned startup circuit, the circuit can be moved away from its degeneracy point. By setting up the aforementioned bias circuit, bias current can be provided for the higher-order compensation circuit and the bandgap reference circuit, preventing fluctuations in the power supply voltage VDD from affecting the operating state of the higher-order compensation circuit and the bandgap reference circuit.

[0124] In some embodiments, the startup circuit includes: a twelfth resistor R12, an eleventh MOSFET M11, and a twelfth MOSFET M12; both the eleventh MOSFET M11 and the twelfth MOSFET M12 are NMOS transistors;

[0125] The first terminal of the twelfth resistor R12 is connected to the power supply voltage VDD. The second terminal of the twelfth resistor R12, the gate of the eleventh MOSFET M11, and the drain of the twelfth MOSFET M12 are connected to ground in sequence. The gate of the eleventh MOSFET M11 is connected to the drain of the eleventh MOSFET M11, and the gate of the twelfth MOSFET M12 is connected to the drain of the twelfth MOSFET M12. The source of the eleventh MOSFET M11 is the output terminal of the startup circuit.

[0126] It should be noted that when the power supply voltage VDD is applied, the twelfth resistor R12 and the twelfth MOSFET M12 form a voltage divider. The gate voltage of the eleventh MOSFET M11 is determined by the aspect ratio of the twelfth MOSFET M12, that is, the gate voltage of the eleventh MOSFET M11 is equal to the gate-source voltage of the twelfth MOSFET M12. The gate voltage of the eleventh MOSFET M11 gradually rises to its threshold voltage, thus turning it on.

[0127] In some embodiments, the bias circuit includes: a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, a twentieth MOSFET M20, and a thirteenth resistor R13; the thirteenth MOSFET M13, the fourteenth MOSFET M14, and the fifteenth MOSFET M15 are all PMOS transistors, and the sixteenth MOSFET M16, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, and the twentieth MOSFET M20 are all NMOS transistors;

[0128] The sources of the thirteenth MOSFET M13, the fourteenth MOSFET M14, and the fifteenth MOSFET M15 are connected to the power supply voltage VDD. The gates of the thirteenth MOSFET M13, the fourteenth MOSFET M14, and the fifteenth MOSFET M15 are connected sequentially. The gate of the fourteenth MOSFET M14 is connected to its drain. The drain of the thirteenth MOSFET M13 is connected to the drain of the seventeenth MOSFET M17. The source of the seventeenth MOSFET M17 is grounded. The drain of the fourteenth MOSFET M14 is connected to the drain of the sixteenth MOSFET M16. The gate of the sixteenth MOSFET M16 is connected to the drains of both the thirteenth MOSFET M13 and the seventeenth MOSFET M17. The connection point S between the drains of the thirteenth MOSFET M13 and the seventeenth MOSFET M17 is the input terminal of the bias circuit. The source of the sixteenth MOSFET M16 is connected to the seventeenth MOSFET M15. The gate of MOSFET M17 is connected to the first terminal of the thirteenth resistor R13, and the second terminal of the thirteenth resistor R13 is grounded. The drain of the fifteenth MOSFET M15 is connected to the drain of the eighteenth MOSFET M18. The source of the eighteenth MOSFET M18 is grounded. The gate of the eighteenth MOSFET M18 is connected to the drain of the eighteenth MOSFET M18. The gates of the eighteenth MOSFET M18, the nineteenth MOSFET M19, and the twentieth MOSFET M20 are connected in sequence. The sources of the eighteenth MOSFET M18, the nineteenth MOSFET M19, and the twentieth MOSFET M20 are all grounded. The drain of the nineteenth MOSFET M19 is used to output the first bias current IBIAS1 to power the first operational amplifier AMP1 of the bandgap reference circuit. The drain of the twentieth MOSFET M20 is used to output the second bias current IBIAS2 to power the second operational amplifier AMP2 of the high-order compensation circuit.

[0129] It should be noted that when the eleventh MOSFET M11 in the startup circuit is turned on, due to the parasitic capacitance on the gate-source of the sixteenth MOSFET M16, current flows through point S, charging this parasitic capacitance and causing the voltage at point S to rise. Subsequently, the sixteenth MOSFET M16, seventeenth MOSFET M17, thirteenth MOSFET M13, and fourteenth MOSFET M14 are turned on, causing the bias circuit to deviate from the degeneracy point. The bias current determined by the seventeenth MOSFET M17 and the thirteenth resistor R13 is replicated to the nineteenth MOSFET M19 and the twentieth MOSFET M20 through the fifteenth MOSFET M15 and the eighteenth MOSFET M18. The drain of the nineteenth MOSFET M19 outputs a first bias current IBIAS1, which powers the first operational amplifier AMP1 of the bandgap reference circuit. The drain of the twentieth MOSFET M20 outputs a second bias current IBIAS2, which powers the second operational amplifier AMP2 of the high-order compensation circuit.

[0130] When the bias circuit is working normally, the voltage at point S is V. GS16 (Gate-source voltage of the sixteenth MOSFET M16) +V GS17 (Gate-source voltage of the seventeenth MOSFET M17) This voltage is higher than the gate voltage of the eleventh MOSFET M11, causing the eleventh MOSFET M11 to be turned off, and the startup circuit to be shut down.

[0131] It should also be noted that the branch current I flowing through the thirteenth MOSFET M13 13 and the branch current I of the fourteenth MOSFET M14 14 Since the gate-source voltage of the seventeenth MOSFET M17 is applied across the thirteenth resistor R13, the gate-source voltage V of the seventeenth MOSFET M17 is equal. GS17 The expression is:

[0132]

[0133] Among them, V TH17 C represents the threshold voltage of the seventeenth MOSFET M17. OX W represents the gate oxide capacitance per unit area, μ represents the carrier mobility, and W represents the capacitance per unit area. 17 L represents the channel width of the seventeenth MOSFET M17. 17 This indicates the channel length of the seventeenth MOSFET, M17.

[0134] Then, the branch current I of the fourteenth MOSFET M14 14 The expression is:

[0135]

[0136] Based on this, the expression for the bias current is obtained as follows:

[0137]

[0138] As shown in the above equation, IBIAS1 and IBIAS2 are independent of the power supply voltage VDD, meaning they do not change with variations in VDD. This design effectively eliminates the impact of fluctuations in the power supply voltage VDD.

[0139] To further verify the advantages of the bandgap reference voltage source in the above embodiments, circuit simulation was performed, and a simulation diagram showing the relationship between the reference voltage VREF output by the bandgap reference voltage source and temperature was obtained. Please refer to [the relevant documentation]. Figure 4 , Figure 4 The reference voltage VREF is 2.50312V, and the temperature drift can reach 4.19973ppm. Figure 4 The horizontal axis represents temperature (temp), and the vertical axis represents the reference voltage value (V).

[0140] Figure 5 This is a simulation diagram of PSRR under full PVT for a bandgap reference voltage source according to an embodiment of the present invention. Please refer to... Figure 5 Under full PVT, the PSRR is approximately -95 dB, which is a good suppressor of power supply noise. Figure 5 The left side shows the legend, representing different PVTs, and the right side shows the relationship between the reference voltage and frequency. The horizontal axis represents the frequency (freq (Hz)) and the vertical axis represents the PSRR.

[0141] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A bandgap reference voltage source, characterized in that, include: A high-order compensation circuit utilizes a MOS transistor operating in subthreshold mode to generate a target compensation current that exhibits a high-order nonlinear relationship with temperature, and outputs the target compensation current to a bandgap reference circuit. A bandgap reference circuit generates a positive temperature coefficient voltage and a negative temperature coefficient voltage. The positive temperature coefficient voltage is used to perform first-order temperature compensation on the negative temperature coefficient voltage, and based on the target compensation current, higher-order curvature compensation is performed on the negative temperature coefficient voltage. The compensated voltage is then determined as the reference voltage and output.

2. The bandgap reference voltage source according to claim 1, characterized in that, The bandgap reference circuit includes: A differential pair module generates a positive temperature coefficient voltage through the current density difference of a proportional device and a negative temperature coefficient voltage based on the on-state voltage of one of the bipolar transistors in the proportional device, the proportional device comprising at least one pair of bipolar transistors of proportional size. The first operational amplifier negative feedback module has its inverting input connected to the collector of a bipolar transistor of a first size in the proportional device, its non-inverting input connected to the collector of a bipolar transistor of a second size in the proportional device, and its output connected to the input of the differential pair module. The output of the first operational amplifier negative feedback module is used to output the reference voltage, and the first size and the second size are proportional.

3. The bandgap reference voltage source according to claim 2, characterized in that, The differential pair module includes: a first resistor, a second resistor, a first bipolar transistor, a second bipolar transistor, a third bipolar transistor, a fourth bipolar transistor, and a third resistor. The resistance values ​​of the first resistor and the second resistor are equal. The first bipolar transistor and the second bipolar transistor have a preset emitter area ratio. The third bipolar transistor and the fourth bipolar transistor have the preset emitter area ratio. The first operational amplifier negative feedback module includes a first operational amplifier and a first MOS transistor. The first MOS transistor is an NMOS transistor. The inverting input of the first operational amplifier is connected to the collector of the first bipolar transistor. The non-inverting input of the first operational amplifier is connected to the collector of the second bipolar transistor and the base of the third bipolar transistor. The collector of the first operational amplifier is connected to its base. The output of the first operational amplifier is connected to the gate of the first MOS transistor. The drain of the first MOS transistor is connected to the target voltage. The source of the first MOS transistor, the first resistor, the collector and emitter of the first bipolar transistor, the collector and emitter of the third bipolar transistor, and the third resistor are sequentially connected to ground. The source of the first MOS transistor, the second resistor, the collector and emitter of the second bipolar transistor, the collector and emitter of the fourth bipolar transistor, and the third resistor are sequentially connected to ground. The collector of the second bipolar transistor is connected to its base. The connection point between the source of the first MOS transistor and the first resistor is the output of the bandgap reference circuit. The base of the fourth bipolar transistor is connected to the output of the bandgap reference circuit.

4. The bandgap reference voltage source according to claim 3, characterized in that, The bandgap reference circuit further includes a fourth resistor and a fifth resistor. The source of the first MOS transistor, the fourth resistor, the fifth resistor, and the first resistor are connected in sequence. The connection point between the fourth resistor and the fifth resistor is the output terminal of the bandgap reference circuit.

5. The bandgap reference voltage source according to claim 3, characterized in that, The higher-order compensation circuit includes: An initial compensation current generation module is used to connect to the target voltage and generate an initial compensation current; A current mirror module is used to copy the initial compensation current to the first compensation current generation module and the second compensation current generation module; The second operational amplifier negative feedback module has its non-inverting input terminal connected to the output terminal of the bandgap reference circuit, and its inverting input terminal connected to the voltage divider module. The voltage divider module is used to perform voltage division and control the conduction state of the first compensation current generation module and the second compensation current generation module based on the voltage after voltage division. The first compensation current generation module determines the conduction state based on the current output by the voltage divider module, and generates the first compensation current from the initial compensation current through a MOS transistor operating in subthreshold mode. The second compensation current generation module determines the conduction state based on the current output by the voltage divider module, and generates a second compensation current from the initial compensation current through a MOS transistor operating in subthreshold mode. The sum of the first compensation current and the second compensation current is the target compensation current.

6. The bandgap reference voltage source according to claim 5, characterized in that, The initial compensation current generation module includes a fifth bipolar transistor and a sixth resistor; the current mirror module includes a second MOSFET, a third MOSFET, and a fourth MOSFET; the second operational amplifier negative feedback module includes a second operational amplifier and a fifth MOSFET, the fifth MOSFET being an NMOS transistor; the voltage divider module includes a seventh resistor, an eighth resistor, and a ninth resistor; the first compensation current generation module includes a sixth MOSFET and a seventh MOSFET; the second compensation current generation module includes an eighth MOSFET and a ninth MOSFET; and the second, third, fourth, sixth, seventh, eighth, and ninth MOSFETs are all PMOS transistors. The source of the second MOSFET is connected to the target voltage and is connected to the source of the third MOSFET, the source of the fourth MOSFET, and the drain of the fifth MOSFET. The gate of the second MOSFET is connected to the gate of the third MOSFET and the gate of the fourth MOSFET. The drain of the second MOSFET, the collector and emitter of the fifth bipolar transistor, and the first terminal of the sixth resistor are connected in sequence. The second terminal of the sixth resistor is connected to the drain of the seventh MOSFET and the drain of the ninth MOSFET. The second terminal of the sixth resistor is also connected to the ninth resistor, the eighth resistor, the seventh resistor, and the source of the fifth MOSFET in sequence. The non-inverting input of the second operational amplifier is connected to the output of the bandgap reference circuit, its inverting input is connected to the source of the fifth MOSFET, and its output is connected to the gate of the fifth MOSFET. The drain of the third MOSFET is connected to the... The source of the sixth MOSFET is connected to the source of the seventh MOSFET. The drain of the fourth MOSFET is connected to the source of the eighth MOSFET and the source of the ninth MOSFET. The connection point between the seventh resistor and the eighth resistor is the first node, and the connection point between the eighth resistor and the ninth resistor is the second node. The first node is connected to the gate of the eighth MOSFET, and the second node is connected to the gate of the seventh MOSFET. The gate of the sixth MOSFET is connected to the gate of the ninth MOSFET. The end of the third resistor connected to the third bipolar transistor is its first terminal. The drain of the eighth MOSFET and the drain of the sixth MOSFET are connected to the second terminal of the third resistor. The emitters of the third bipolar transistor and the fourth bipolar transistor are connected to the gate of the sixth MOSFET. The base of the fourth bipolar transistor is connected to the base of the fifth bipolar transistor.

7. The bandgap reference voltage source according to claim 3, characterized in that, The bandgap reference voltage source also includes a trimming circuit; The third resistor is connected to ground through the adjustment circuit. The adjustment circuit controls its own resistance value based on the input digital signal to adjust the positive temperature coefficient current, thereby completing the adjustment of the positive temperature coefficient voltage.

8. The bandgap reference voltage source according to claim 7, characterized in that, The adjustment circuit includes multiple adjustment modules connected in parallel. Each adjustment module includes a switching unit and a target resistor. The input terminal of the switching unit is the input terminal of the adjustment module. The switching unit and the target resistor are connected to ground. The switching unit is turned on when it receives a high-level digital signal and turned off when it receives a low-level digital signal. The resistance values ​​of the target resistors in the multiple adjustment modules show an increasing trend. The switching unit includes a first target PMOS transistor and a second target PMOS transistor. The source of the first target PMOS transistor and the source of the second target PMOS transistor are respectively connected to the third resistor. The gate of the first target PMOS transistor and the gate of the second target PMOS transistor are both used to receive the digital signal. The drain of the first target PMOS transistor and the drain of the second target PMOS transistor are respectively connected to the corresponding target resistor. Alternatively, the switching unit includes a third target PMOS transistor, the source of which is connected to the third resistor, the gate of which is used to receive the digital signal, and the drain of which is connected to the corresponding target resistor. Alternatively, the switching unit includes a fourth target PMOS transistor and a fifth target PMOS transistor. The source of the fourth target PMOS transistor is connected to the third resistor, the gate of the fourth target PMOS transistor is connected to the source of the fifth target PMOS transistor, the gate of the fifth target PMOS transistor is used to receive the digital signal, and the drains of the fourth target PMOS transistor and the fifth target PMOS transistor are respectively connected to the corresponding target resistors.

9. The bandgap reference voltage source according to claim 3, characterized in that, The bandgap reference voltage source further includes a low-pass filter circuit, which includes a first low-pass filter module and a second low-pass filter module. The first low-pass filter module includes a tenth resistor, a first capacitor, and a tenth MOS transistor, which is an NMOS transistor. The second low-pass filter module includes an eleventh resistor and a second capacitor. The first end of the tenth resistor is connected to a preset power supply voltage, the second end of the tenth resistor and the first capacitor are connected to ground, the second end of the tenth resistor is connected to the gate of the tenth MOS transistor, the drain of the tenth MOS transistor is connected to the power supply voltage, and the source of the tenth MOS transistor is connected to the drain of the first MOS transistor, so as to output the target voltage after low-pass filtering to the first MOS transistor. The first end of the eleventh resistor is connected to the output end of the bandgap reference circuit, and the second end of the eleventh resistor, the second capacitor, and the gate of the fourth bipolar transistor are connected in sequence.

10. The bandgap reference voltage source according to claim 1, characterized in that, The bandgap reference voltage source also includes: The starting circuit is connected to the power supply voltage to power on the circuit. During the power-on phase, the circuit is forced to leave the zero-current degeneracy state. A bias circuit, whose input is connected to the startup circuit, is used to provide a bias current independent of the power supply voltage. The bias current is replicated by a current mirror and output to the bandgap reference circuit and the higher-order compensation circuit respectively, so that the bandgap reference circuit and the higher-order compensation circuit start working.

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