Global clock network multiplier multiplexing method for digital decimation filter in Sigma-Delta ADC

Abstract

The invention discloses a global clock network multiplier multiplexing method for a digital decimation filter in a Sigma-Delta ADC (Analog to Digital Converter). A data input and buffer module, a symmetric addition module, a multiplier time division multiplexing module, an additive operation and output module and a state machine control module are included. A large number of multiplier units need to be deployed for achieving high-order filtering response through a traditional FIR filter, high-proportion DSP resources are occupied in an FPGA, the logic resource utilization rate exceeds the limit, and the multi-channel integration capacity is remarkably restricted. According to the basic principle of the method, the characteristics of coefficient symmetry and multiple extraction of an FIR filter are utilized, and a time division multiplexing multiplication unit is provided to reduce the use of logic resources. According to the method provided by the invention, the problem of overlarge occupied hardware resources caused by a high-order filter is effectively solved, and the hardware resources used in the filter design are greatly reduced.

Description

Technical Field

[0001] This invention relates to the fields of Sigma-Delta ADC technology and low-power integrated circuits, and in particular to a method for achieving low hardware resource consumption digital decimation filters through multiplier multiplexing. Background Technology

[0002] Sigma-Delta ADCs (∑-Δ analog-to-digital converters) are high-precision analog-to-digital converters widely used in modern electronic systems, such as audio processing, communication systems, and instrumentation. They convert input analog signals into digital signals through oversampling and noise shaping techniques. The circuit structure of a Sigma-Delta ADC mainly consists of two parts: an analog modulator and a digital decimation filter. The digital section employs a three-stage decimation filter. The digital decimation filter plays a crucial role in the system; it reduces the data rate while filtering out out-of-band noise, improving the effective resolution of the signal, thus providing a high-quality data foundation for subsequent digital signal processing.

[0003] Traditional digital decimation filters require significant hardware resources, such as multipliers, during implementation. Since multiplication is frequently used in filtering algorithms, a large number of multipliers not only increases chip area and cost but also leads to higher power consumption. This resource-intensive design is particularly problematic in cost- and power-sensitive applications, such as portable devices and IoT nodes, where it struggles to meet practical needs. Furthermore, with the continuous development of integrated circuit technology, increased chip area may lead to higher heat dissipation requirements and reliability issues.

[0004] To address the issue of multiplier resource consumption, several multiplier multiplexing techniques have been proposed. However, these existing techniques often have limitations. Some techniques are only effective for specific types of filter structures or algorithms, lacking versatility and unable to be widely applied to Sigma-Delta ADC digital decimation filters across different architectures. Other techniques introduce complex control logic during multiplexing, leading to difficulties in system timing convergence, increasing design and debugging complexity, and reducing system stability and reliability. Furthermore, existing multiplexing techniques lack effective global planning for clock network management, making it difficult to achieve efficient utilization of multiplier resources while ensuring filtering performance.

[0005] Therefore, designing an efficient global clock network multiplier multiplexing method in the digital decimation filter of a Sigma-Delta ADC, which can effectively reduce the use of multiplier resources, lower chip cost and power consumption, while ensuring system stability, reliability and good filtering performance, has become an urgent technical problem to be solved. This invention addresses these problems by providing an innovative method to meet the demands of modern electronic systems for high-performance, low-power digital decimation filters. Summary of the Invention

[0006] This invention proposes a low-resource-consumption data processing scheme suitable for high-order digital filters. Specifically, for a 19th-order compensated filter with 2x decimation characteristics, a time-optimized pipeline architecture and a multiplier multiplexing mechanism are designed. The specific technical solution is as follows:

[0007] Input data timing processing: The raw data output by the CIC module is timing the data in two registers (generating i_data_d0 and i_data_d1). By increasing the pipeline stage, the timing convergence is improved, ensuring that the establishment of high-speed signal paths maintains a time margin.

[0008] Fixed-length data grouping and caching mechanism: A counter `data_cnt` is used to periodically count the data after pacing, automatically resetting to zero when it accumulates to 19 data points, thus achieving fixed-length grouping of the input data stream. Each group of data is cached through a 19-level register group (`data_r0-data_r18`), providing a synchronous data window for subsequent multiplication and accumulation operations with filter coefficients.

[0009] Parity grouping mechanism: Based on the polyphase decomposition principle of the filter, parity grouping can be adopted: when jo_flag = 1 (odd group), only the 1st, 3rd, 5th, 7th, 9th, 11th, 13th, 15th, 17th, and 19th data points participate in the multiplication operation; when jo_flag = 0 (even group), only the 2nd, 4th, 6th, 8th, 10th, 12th, 14th, 16th, and 18th data points participate in the multiplication operation. This flag bit is strictly synchronized with the data grouping to ensure that the operation logic accurately matches the extraction rules.

[0010] Utilizing coefficient symmetry: Taking advantage of the even symmetry property of the compensation filter coefficients (h(n) = h(18-n)), the 19th-order coefficients are divided into 9 pairs of symmetric coefficient groups (such as h0 and h18, h1 and h17) and one central coefficient h9. Correspondingly, the 19 buffered input data are symmetrically added end-to-end to generate 10 addition results:

[0011] add0 = data_r0 + data_r18 (corresponding to the coefficient pair h0 / h18),

[0012] add1 = data_r1 + data_r17 (corresponding coefficient pair h1 / h17);

[0013] ...

[0014] add8 = data_r8 + data_r10 (corresponding coefficient pair h8 / h10);

[0015] add9 = data_r9 (corresponding to the central coefficient h9).

[0016] Through the above operations, the original 19 multiplication operations are compressed into 10 multiplication operations, reducing the number of multipliers by 47%.

[0017] Pipeline multiplier multiplexing architecture: A multiplier multiplexing flag `mult_reuse_flag` is introduced. When this signal goes high, a 10-stage pipelined multiplication process is initiated. The multiplication input is dynamically switched using a counter `mult_reuse_cnt` (a cyclic counter from 0 to 9): when `cnt = 0`, `add0` and the amplification factor `h0` are input to calculate the first product; when `cnt = 1`, `add1` and the amplification factor `h1` are input to calculate the second product; and so on, until `cnt = 9` completes all 10 operations. The result of each multiplication is buffered in real time through a register set (`mult_result_r0` - `mult_result_r9`) to ensure that data is not lost at any stage of the pipeline.

[0018] The addition and multiplication multiplexing process adopts a 15-stage pipeline design: in the first 10 clock cycles, a single multiplier completes 10 time-division multiplexed calculations; in the last 5 clock cycles, the addition result is stored, the division operation is performed, and multiple stages of timing are completed to ensure the timing balance of each stage of operation.

[0019] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0020] 1. The global clock network multiplier multiplexing method provided by the present invention reduces the number of multipliers from 19 to 1 through coefficient symmetry compression and single multiplier multiplexing.

[0021] 2. The global clock network multiplier multiplexing method provided by this invention has a pipelined architecture suitable for higher-order symmetric filter designs. The logic of this solution can be reused simply by adjusting the group length and the number of multiplexing operations. Attached Figure Description

[0022] Figure 1 This is a block diagram of the overall module.

[0023] Figure 2 This is a block diagram of a digital filter structure.

[0024] Figure 3 Here is a block diagram of the CIC filter structure;

[0025] Figure 4 Block diagram of time-division multiplexing of compensation filter; Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Examples of the embodiments are shown in the accompanying drawings. The specific embodiments described in the following embodiments of the present invention are merely illustrative examples of specific implementations of the present invention and are intended to explain the present invention, but are not intended to limit the present invention. The implementation method includes the following steps:

[0027] Step 1: The data output from the CIC filter, i.e., the input data "fir_in" of the compensation filter, is first downsampled by a factor of 2. The compensation filter designed in this invention is of order 19. Based on this, an order 19 delay operation needs to be performed on the downsampled data to meet the filter calculation requirements.

[0028] Step 2: Given the symmetry of the coefficients of the compensation filter, a specific strategy is employed to reduce the number of multipliers during filter data calculation. Specifically, the data of the 19th-order compensation filter are added together end-to-end, for example, adding the 0th and 18th orders, the 1st and 17th orders, etc., resulting in 10 sets of data. These 10 sums are then multiplied by the filter coefficients "h0-h9". This operation optimizes the calculation, which originally required 19 multipliers, to only 10 multipliers.

[0029] Step 3: The downsampling factor of the CIC filter is 64 times, and the downsampling factor of the compensation filter is 2 times. Therefore, in the entire data processing flow, filter multiplication calculations only occur every 128 data points. Based on this characteristic, this invention further optimizes the multiplication calculation process by using only one multiplier to perform 10 multiplication calculations sequentially between 128 data points. This replaces the traditional method of using 10 multipliers to calculate 10 data points separately, thus significantly reducing the number of multipliers.

[0030] Step 4: Count the downsampled data from the compensation filter, grouping it into sets of 19 data points. These groupings will be used as the selection criteria for the 10-to-1 multiplexer. The specific control logic is as follows:

[0031] When the count is 0, it indicates that the data order to be calculated is 0th and 18th. At this time, the control signal "sel" controlling the 0th and 1st 10-to-1 multiplexers multiplies the sum of the 0th and 18th order data with the coefficient "h0" of the compensation filter. After the multiplication operation is completed, the multiplication result "mult_result" is input to the 2nd 10-to-1 multiplexer and stored in registers "r0-r9". Storing the result in registers prevents the calculation result of the previous order from being overwritten during the next multiplication, effectively preventing data loss.

[0032] When the count is 1-9, the same control principle is followed to control the multiplexer to complete the data multiplication calculation of the corresponding order, ensuring that the data of each order can be calculated accurately.

[0033] Step 5: After completing the multiplication calculations of each order, sum the calculation results of each order and output the summed result to the half-band filter as the input data "half_in" for subsequent data processing calculations.

[0034] In filter architecture design, the number of multiplier units is directly related to the downsampling parameters of the cascaded filter module. Let the downsampling factor of the CIC filter be M, the downsampling factor of the compensation filter be N, and the filter order be J. In the baseline design without optimization techniques, the multiplier resource consumption is determined by the equation X = ceil(J / 2), where ceil represents rounding up. Using the proposed scheme, the minimum number of multipliers, Xmin, that can be used in the filter is: X = ceil(J / 2·M·N). A comparison shows that the proposed multiplier scheme can significantly reduce the number of multipliers.

Claims

1. A global clock network multiplier multiplexing method for digital decimation filters in Sigma-Delta ADCs, characterized by: It includes a data input and buffer module, a symmetric addition module, a multiplier time-division multiplexing module, an addition operation and output module, and a state machine control module. The compensation filter has an order of 19 and a decimation factor of 2. By utilizing the symmetric characteristics of the compensation filter coefficients, the number of multipliers can be reduced from 19 to 10. By utilizing the multiple decimation characteristics of the compensation filter, the number of multipliers can be reduced to 1.

2. The global clock network multiplier multiplexing method for digital decimation filters in Sigma-Delta ADCs according to claim 1, characterized in that, The digital decimation filter includes a CIC filter module, a compensation filter module, and a half-band filter module; Furthermore, the CIC filter module includes an integrator module, a decimation module, and a differentiator module; wherein, the decimation module achieves a downsampling rate of 64 times; the input of the integrator module is the input of the CIC filter, that is, the input of the digital decimation filter, and the output of the differentiator module is the output of the CIC module; Furthermore, the compensation filter module is used to compensate for the problems of excessive passband attenuation and insufficient stopband attenuation of the CIC filter. The order of this compensation filter is 19th and the decimation factor is 2. Furthermore, the half-band filter module is used to improve stopband suppression performance, with an order of 11 and a decimation factor of 2.

3. The data input and buffering module according to claim 1, characterized in that, The output data of the CIC filter is processed by a two-step delay register, that is, the data i_data is registered sequentially through two levels of registers. This data is used as the input of the compensation filter to ensure that no data is lost in subsequent processing and to improve timing convergence. This provides a stable data input for subsequent modules and avoids the impact of fluctuations in front-end data transmission on the overall filtering operation.

4. The symmetrical addition module according to claim 1, characterized in that, Since the coefficients of the compensation filter are symmetrical, the 19th-order data are added symmetrically from beginning to end to obtain the addition result add0-add9.

5. The time-division multiplexing module for multipliers according to claim 1, characterized in that, Based on the control signal `mult_reuse_flag` issued by the state machine control module, the multiplier resources are rationally allocated and scheduled. Within different time periods, the multiplier sequentially processes the summation data output by the symmetric addition module.

6. The addition operation and output module according to claim 1, characterized in that, The system receives the multiplication results from the time-division multiplexing module of the multiplier and performs addition operations on these results according to a predetermined addition operation. Multiple multiplication results are then gradually accumulated to obtain the final filtering result, fir_result.

7. The state machine control module according to claim 1 monitors the operating status of the entire digital decimation filter in real time, and generates control signals according to the rules set by the system and the characteristics of the current input data; these control signals are respectively sent to the data input and buffer module, the symmetric adder module, the multiplier time-division multiplexing module, and the adder operation and output module to coordinate the working timing and data flow between the modules, ensuring that the entire filter can operate in an orderly manner according to the predetermined logic, and achieve efficient and stable filtering function.

8. The half-band filter according to claim 2 has a multiplication multiplexing principle similar to that of a compensation filter, which will not be described in detail hereafter.

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