High-robustness pulse position modulation signal receiver
By introducing a self-calibrating current feedback circuit into the PPM signal receiver and dynamically adjusting the current output, the robustness and power consumption problems of existing PPM signal decoding methods are solved, achieving low-power, high-robust PPM signal demodulation.
Patent Information
- Application Number
- CN202510906087.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-02
- Publication Date
- 2025-10-31
AI Technical Summary
Existing PPM signal decoding methods suffer from problems such as poor robustness, high power consumption, complex structure, and design difficulties, making it difficult to achieve an ultra-low power consumption, simple structure, and robust demodulation pulse position modulation signal receiver.
A highly robust pulse position modulation signal receiver is adopted, including a PPM decoding circuit, a clock data recovery circuit, a current digital-to-analog converter, and a self-calibrating current feedback circuit. The self-calibrating current feedback circuit dynamically adjusts the current output to improve the robustness of the decoding process.
It achieves PPM signal data demodulation with simple structure, low power consumption and strong robustness, and can maintain stability under different process, voltage and temperature conditions, thus improving the reliability of signal demodulation.
Smart Images
Figure CN120880402A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of radio frequency receiver technology and relates to a highly robust pulse position modulation signal receiver. Background Technology
[0002] Due to the narrow pulse width and difficulty in clock synchronization, robust and easy decoding of PPM signals is one of the challenges that needs to be addressed in RF receiver design. Common PPM signal decoding methods include: 1. using delay lines and peak detection to estimate pulse position; 2. using phase-locked loops (PLLs) for assisted capture. Method 1 suffers from poor robustness, low speed, complex structure, and high bit error rate due to its susceptibility to process technology, voltage, and temperature (PVT) variations. Method 2 suffers from complex circuit structure, design difficulties, and high power consumption. None of these methods can yield an ultra-low power, simple structure, and robust demodulation PPM signal receiver. Summary of the Invention
[0003] To address the aforementioned technical problems in the existing technology, this invention proposes a highly robust pulse position modulation signal receiver, the specific technical solution of which is as follows: A highly robust pulse position modulation signal receiver includes a PPM decoding circuit, a clock data recovery circuit, a current digital-to-analog converter, and a self-calibrating current feedback circuit. The clock data recovery circuit receives a PPM signal S containing data. PPM The rising edge of the PPM signal is captured and continuously divided to generate two clock signals, CLKB and CLK_JZ. The generated CLKB and CLK_JZ are input to the self-calibrating current feedback circuit. The PPM decoding circuit sends a feedback signal OUT_BACK to the self-calibrating current feedback circuit. The self-calibrating current feedback circuit is triggered by a reset signal RSTN to enter calibration mode. In calibration mode, CLK_JZ is selected as the working clock and its output is used as the input clock CLK_CP of the PPM decoding circuit. At the same time, the input feedback signal OUT_BACK is judged and the control word I_CTRL is output to the current digital-to-analog converter. After calibration is completed according to the judgment result, the output CLKB is selected as the input clock CLK_CP of the PPM decoding circuit. The current-to-analog converter receives the reference current I_BG from the bandgap reference and the control word I_CTRL from the self-calibrating current feedback circuit as input, outputs the current I_CP to the PPM decoding circuit, and finally outputs the demodulated data DATA from the PPM decoding circuit.
[0004] Furthermore, the clock data recovery circuit includes: A D flip-flop DFF2 has its CLK terminal connected to the PPM signal S. PPM The D terminal is self-connected to its QN terminal, and its Q terminal outputs the divided clock CLKB. A D flip-flop DFF3 has its CLK terminal connected to the Q terminal of a D flip-flop DFF2 and inputs a clock CLKB. The D terminal is self-connected to its QN terminal, and the Q terminal outputs a clock CLK_JZ.
[0005] Furthermore, the circuitry of the current-to-analog converter includes: A current mirror transistor MP1 has its gate input connected to current I_BG, its drain connected to the gate, and its source connected to VDD. Multiple IDAC units, each with I_BG and control word I_CTRL as input, and multiple IDAC units are combined to output I_CP.
[0006] Furthermore, each IDAC unit includes: An inverter INV <1> One end is connected to the control word I_CTRL, and the other end is connected to MP. <1> The gate; A pair of transmission gates, including switching transistors MN <1> With switching transistor MP <1> MP <1> The gate connection INV <1> MP <1> The source connection MN <1> The source and input I_BG, MP <1> Drain connection MN <1> Drain of MN; <1> Gate connection control word I_CTRL, MN <1> source connection MP <1> The source is then input into I_BG; A switching transistor MP <2> Its gate is connected to the control word I_CTRL, and its source is connected to MN. <1> The drain is connected to VDD; A current mirror tube MP <3> In multiple IDAC cells, the MOS transistor width W increases in a binary order, MP <3> The gate connection of the switching transistor MP <2> The source is connected to VDD, and the drain outputs I_CP.
[0007] Furthermore, the PPM decoding circuit includes: A charge pump, with input clock CLK_CP and current I_CP, and output clock pulse signal CP_OUT; A switching transistor MN_SW, with its source connected to GND and its drain connected to CP_OUT; An inverter INV1 is input with a reset signal RSTN, and its output is connected to the gate of the switch MN_SW; A capacitor C1 is connected to CP_OUT at one end and to GND at the other end. A pair of voltage divider resistors R1 and R2, one end of R1 is connected to VDD and the other end is connected to the reference voltage VREF1; one end of R2 is connected to the reference voltage VREF1 and the other end is connected to GND. A comparator 1 has its negative input connected to VREF1, its positive input connected to CP_OUT, and its output OUT_BACK; A D flip-flop DFF1, using a classic structure, consists of two SR latches connected end to end. Its D terminal outputs the signal OUT_BACK, its CLK terminal is connected to CLK_CP, its Q terminal outputs DATA, and its QN terminal is left floating.
[0008] Furthermore, the charge pump includes switching transistors MN1 and MP2. The gate of MN1 is connected to the gate of MP2 and CLK_CP, the source is connected to GND, and the drain is connected to the drain of MP2 and CP_OUT. The gate of MP2 is connected to the gate of MN1 and CLK_CP, the source is connected to VDD, and the drain is connected to the drain of MN1 and CP_OUT. The charge pump works in conjunction with capacitor C1. The current of I_CP controlled by the two switching transistors MP2 and MN1 charges and discharges capacitor C1 to complete the charge pump operation. When the clock signal CLK_CP is "1", then transistor MN1 is turned on, and capacitor C1 is discharged. When CLK_CP is "0", then transistor MP2 is turned on, and capacitor C1 is charged. During the charging and discharging process of the capacitor, the positive input terminal of comparator 1 will generate a high and low voltage that varies with the duty cycle of CLK_CP. Comparing this voltage with the reference voltage of VREF1 will output the demodulated signal.
[0009] Furthermore, the comparator 1 is used to complete signal digitization processing, and is connected to I1 as a current source I1. The comparator 1 includes switching transistors: MP3, MP4, MP5, MP6, MP7, MP8, MN2, MN3, MN4, MN5, MN6, and MN7. Among them, MP3 and MP4 form a current mirror. The source of MP3 is connected to VDD, the gate is connected to node VZ1, and the drain is connected to the gate and connected to I1. The source of MP4 is connected to VDD, the gate is connected to node VZ1, and the drain is connected to node VA. MP5 and MP6 form a current mirror. The source of MP5 is connected to VDD, the gate is connected to node VZ2, and the drain is connected to the gate and MN2. The source of MP6 is connected to VDD, and the gate is connected to node VZ2. MN2 and MN7 form an output pair. The source of MN2 is connected to GND, the gate is connected to node VX, and the drain is connected to node VZ2. The source of MN7 is connected to GND, the gate is connected to node VY, and the drain is connected to the drain of MP6. MP7 and MP8 form an input pair. The source of MP7 is connected to node VA, the gate is connected to VIN+, and the drain is connected to node VX. The source of MP8 is connected to node VA, the gate is connected to VIN-, and the drain is connected to node VY. MN3, MN4, MN5, and MN6 form the load transistors. The source of MN3 is connected to GND, the gate is connected to node VX, and the drain is connected to the gate and then to node VX. The source of MN6 is connected to GND, the gate is connected to node VY, and the drain is connected to the gate and then to node VY. The source of MN4 is connected to GND, the gate is connected to node VX, and the drain is connected to node VY. The source of MN5 is connected to GND, the gate is connected to node VY, and the drain is connected to node VX.
[0010] Furthermore, the self-calibrating current feedback circuit includes: A reset module sets the control word I_CTRL to 0 when the input reset signal RSTN is 0, and enters calibration mode when it is 1. A clock selection module, after RSTN is initialized to 0 and enters calibration mode, selects CLK_JZ as the CLK_CP output, and after calibration is completed, selects CLKB as the CLK_CP output; A calibration mode module takes the feedback signal OUT_BACK as input and the control word I_CTRL as output. After RSTN is initialized to 0, it enters calibration mode and uses the clock CLK_CP to judge OUT_BACK. If it is 1, I_CTRL is incremented by 1, and then it returns to judging OUT_BACK. If it is 0, the calibration ends.
[0011] Beneficial effects: Compared with traditional PPM signal demodulation schemes, the decoding circuit proposed in this invention has the advantages of simple structure, low power consumption, and strong robustness, and can more reliably achieve PPM signal data demodulation. Attached Figure Description
[0012] Figure 1 This is a general block diagram of the pulse position modulation signal receiver according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the PPM decoding circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the CDR circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the IDAC circuit according to an embodiment of the present invention; Figure 5 This is a flowchart of the self-calibration current feedback process according to an embodiment of the present invention; Figure 6 yes Figure 2 Circuit diagram of a charge pump; Figure 7 yes Figure 2 The circuit diagram of comparator 1; Figure 8a and Figure 8b yes Figure 6 Output waveforms under different PVT conditions. Detailed Implementation
[0013] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0014] like Figure 1 As shown, a highly robust pulse position modulation signal receiver of the present invention includes a PPM decoding circuit, a clock data recover (CDR) circuit, a current digital-to-analog converter (IDAC), and a self-calibrating current feedback circuit. The CDR circuit realizes self-clock recovery of the PPM signal, the PPM decoding circuit completes the demodulation and decoding of the signal, and the combination of the IDAC current digital-to-analog converter and the self-calibrating current feedback mechanism effectively improves the robustness of the decoding process.
[0015] Specifically, the clock data recovery circuit receives a reset signal RSTN and a PPM signal S as inputs. PPM Output clocks CLKB and CLK_JZ; The self-calibrating current feedback circuit receives the clock CLKB and CLK_JZ from the CDR circuit and the signal OUT_BACK from the PPM decoding circuit, as well as the reset signal RSTN, and outputs the clock CLK_CP and the control word I_CTRL. The current-to-analog converter has inputs from the reference current I_BG provided by the bandgap reference and the control word I_CTRL of the self-calibrating current feedback circuit, and outputs the current I_CP. The PPM decoding circuit takes CLK_CP of the self-calibrating current feedback circuit and I_CP of the IDAC circuit as inputs, as well as the reset signal RSTN, and outputs demodulated data DATA and the signal OUT_BACK fed back to the self-calibrating current feedback circuit. like Figure 3 As shown, the CDR clock data recovery circuit includes: A D flip-flop DFF2, using a classic structure, consists of two SR latches connected end-to-end, configured as a divide-by-2 mode, with its CLK terminal connected to the PPM signal S. PPM The D terminal is self-connected to its QN terminal, and its Q terminal outputs the divided clock CLKB. A D flip-flop DFF3, using a classic structure, consists of two SR latches connected end-to-end. These latches are connected in a divide-by-2 mode. Its CLK terminal is connected to the Q terminal of the D flip-flop DFF2 and inputs the clock CLKB. The D terminal is self-connected to its QN terminal, and the Q terminal outputs the clock CLK_JZ.
[0016] like Figure 4 As shown, the IDAC circuit includes: A current mirror transistor MP1 has its gate input connected to the control current I_BG, its drain connected to the gate, and its source connected to VDD. Multiple IDAC units, each with I_BG and control word I_CTRL as input, and multiple IDAC units are combined to output I_CP.
[0017] Each IDAC unit includes: An inverter INV <1> One end is connected to the control word I_CTRL, and the other end is connected to MP. <1> The gate; A pair of transmission gates, including switching transistors MN <1> With switching transistor MP <1> MP <1> The gate connection INV <1> MP <1> The source connection MN <1> The source and input I_BG, MP <1> Drain connection MN <1> Drain of MN; <1> Gate connection control word I_CTRL, MN <1> source connection MP <1> The source is then input into I_BG; A switching transistor MP <2> Its gate is connected to the control word I_CTRL, and its source is connected to MN. <1> The drain is connected to VDD; A current mirror tube MP <3> In multiple IDAC cells, the MOS transistor width W increases in a binary order, MP <3> The gate connection of the switching transistor MP <2> The source is connected to VDD, and the drain outputs I_CP.
[0018] like Figure 2 As shown, the PPM decoding circuit includes: A charge pump, with input clock CLK_CP and current I_CP, and output clock pulse signal CP_OUT; A switching transistor MN_SW, with its source connected to GND and its drain connected to CP_OUT; An inverter INV1 is input with a reset signal RSTN, and its output is connected to the gate of the switch MN_SW; A capacitor C1 is connected to CP_OUT at one end and to GND at the other end. A pair of voltage divider resistors R1 and R2, one end of R1 is connected to VDD and the other end is connected to the reference voltage VREF1; one end of R2 is connected to the reference voltage VREF1 and the other end is connected to GND. A comparator 1 has its negative input connected to VREF1, its positive input connected to CP_OUT, and its output connected to OUT_BACK; A D flip-flop DFF1, using a classic structure, consists of two SR latches connected end to end. Its D terminal outputs the signal OUT_BACK, its CLK terminal is connected to CLK_CP, its Q terminal outputs DATA, and its QN terminal is left floating.
[0019] The circuit of the charge pump is as follows: Figure 6 As shown in the diagram. The charge pump consists of two MOSFETs, MN1 and MP2. The gate of MN1 is connected to the gate of MP2 and then to CLK_CP, the source of MN1 is connected to GND, and the drain of MN1 is connected to the drain of MP2 and then to CP_OUT. The gate of MP2 is connected to the gate of MN1 and then to CLK_CP, the source of MP2 is connected to VDD, and the drain of MP2 is connected to the drain of MN1 and then to CP_OUT. The output waveform of the charge pump is shown in the diagram. Figure 8a and Figure 8b As shown, Figure 8a This is the output waveform of a charge pump without a self-calibrating current feedback circuit, and its waveform is also used as the positive input of comparator 1. Figure 8b It is the output waveform of a charge pump with a self-calibrating current feedback circuit. The waveform is the output voltage waveform after calibration.
[0020] The comparator 1 circuit is as follows: Figure 7 As shown. VZ1, VZ2, VX, VY, and VA are connection nodes. Comparator 1 is a classic comparator structure with an output stage and internal hysteresis, used to complete signal digitization processing. I1 is a current source, supplied by an external reference. MP3 and MP4 form a current mirror. The source of MP3 is connected to VDD, the gate is connected to node VZ1, and the drain is connected to the gate and connected to I1. The source of MP4 is connected to VDD, the gate is connected to node VZ1, and the drain is connected to node VA. MP5 and MP6 form a current mirror. The source of MP5 is connected to VDD, the gate is connected to node VZ2, and the drain is connected to the gate and MN2. The source of MP6 is connected to VDD, and the gate is connected to node VZ2. MN2 and MN7 form an output pair. The source of MN2 is connected to GND, the gate is connected to node VX, and the drain is connected to node VZ2. The source of MN7 is connected to GND, the gate is connected to node VY, and the drain is connected to the drain of MP6. MP7 and MP8 form an input pair. The source of MP7 is connected to node VA, the gate is connected to VIN+, and the drain is connected to node VX. The source of MP8 is connected to node VA, the gate is connected to VIN-, and the drain is connected to node VY. MN3, MN4, MN5, and MN6 form the load transistors. The source of MN3 is connected to GND, the gate is connected to node VX, and the drain is connected to the gate and then to node VX. The source of MN6 is connected to GND, the gate is connected to node VY, and the drain is connected to the gate and then to node VY. The source of MN4 is connected to GND, the gate is connected to node VX, and the drain is connected to node VY. The source of MN5 is connected to GND, the gate is connected to node VY, and the drain is connected to node VX.
[0021] like Figure 5 As shown, the self-calibrating current feedback circuit includes: A reset module sets the control word I_CTRL to 0 when the input RSTN is 0, and enters calibration mode when it is 1; A clock selection module, after RSTN is initialized to 0 and enters calibration mode, selects CLK_JZ as the CLK_CP output, and after calibration is completed, selects CLKB as the CLK_CP output; A calibration mode module takes the feedback signal OUT_BACK as input and the control word I_CTRL as output. After initializing RSTN to 0, it enters calibration mode and uses the clock CLK_CP to check OUT_BACK. If it is 1, I_CTRL is incremented by 1, and then the module returns to checking OUT_BACK. If it is 0, the calibration ends.
[0022] The working principle of the highly robust PPM signal decoding circuit proposed in this invention is as follows: PPM signal with data PPM The PPM signal is first received by the CDR circuit. Then, a divider consisting of D flip-flops is used to capture the rising edge of the PPM signal, and after two consecutive processing steps, two clock signals are generated: CLKB and CLK_JZ.
[0023] The generated CLKB and CLK_JZ are input to the self-calibration current feedback circuit. After system initialization is triggered by the RSTN signal, the system enters calibration mode. The circuit preferentially selects CLK_JZ as the operating clock of the self-calibration current feedback circuit and uses it as the input clock (CLK_CP) of the PPM decoding circuit. After the calibration process is completed, the system switches to using CLKB as the input clock (CLK_CP) of the PPM decoding circuit to achieve correct demodulation.
[0024] The core principle of the PPM decoding circuit lies in selecting a suitable CLK_CP clock input through a self-calibrating current feedback circuit, and using this clock to control the current source of the charge pump, causing capacitor C1 to alternately charge and discharge, thereby adjusting S. PPM The timing and amplitude of the signal. If S PPMThe positioning ratio between the three pulses in the signal is 7:3. The charging time of capacitor C1 is relatively long, and the output voltage will exceed the reference voltage VREF1. At this time, comparator 1 outputs demodulated data "0". Conversely, if the charging time is insufficient, the output voltage will be lower than VREF1, and comparator 1 will output demodulated data "1".
[0025] Because the charge pump is highly sensitive to changes in process, voltage, and temperature (PVT), its current output needs to be dynamically and automatically adjusted to improve system robustness. After system initialization, the self-calibrating current feedback circuit first sets the output current of the IDAC circuit to zero. At this point, the charge pump has no current input, resulting in insufficient charging of C1, and its output voltage is lower than VREF1, causing comparator 1 to output "1". The self-calibrating current feedback circuit samples this demodulation result. If it detects "1", it determines that the current is insufficient and then increases the control word to increase the output current of the IDAC circuit. The system then repeats the demodulation process and continuously monitors the demodulated data. When a demodulation result of "0" is detected, it indicates that the charge pump current has reached the required level, and calibration is complete. Afterward, the system switches to the CLKB clock and enters the normal PPM demodulation state, achieving stable signal demodulation.
[0026] The specific working process and working principle of the circuit in this example are as follows: After the charge pump is supplied with a certain current I_CP by the IDAC and a suitable CLK_CP clock signal by the self-calibrating current feedback circuit, the charge pump works in conjunction with capacitor C1. The current I_CP is controlled by two switching transistors, MP2 and MN1, to charge or discharge capacitor C1, thus completing the charge pump's operation. When CLK_CP is "1", transistor MN1 is turned on, and capacitor C1 is discharged; when CLK_CP is "0", transistor MP2 is turned on, and capacitor C1 is charged.
[0027] During the charging and discharging process of the capacitor, the positive input terminal of comparator 1 generates a high-low voltage that varies with the duty cycle of CLK_CP. Comparing this voltage with the reference voltage of VREF1 outputs the demodulated signal. Comparator 1 achieves its comparison function through internal positive feedback. This circuit has two feedback paths: the first is the series current (MN3 and MN6) through the common source node of transistors MP7 and MP8, which is negative feedback; the second is the parallel voltage feedback connecting the source and drain of MN4 and MN5, which is positive feedback. When the positive feedback coefficient is less than the negative feedback coefficient, the entire circuit will exhibit negative feedback and lose its hysteresis effect; when the positive feedback coefficient is greater than the negative feedback coefficient, the entire circuit will exhibit positive feedback, and hysteresis will appear in the voltage transfer curve. The output stage is constructed using MP5, MP6, MN2, and MN7, providing a reasonable output voltage swing and output resistance during the differential-to-single-stage conversion. MP3 and MP4 form a current mirror to provide circuit bias.
[0028] Continue to refer to Figure 8a As can be clearly observed from the waveform diagram, under different PVT conditions, the charge pump without the self-calibrating current feedback circuit described in this invention exhibits significant fluctuations in its output voltage. Meanwhile, the reference voltage VREF1 of comparator 1 remains constant, leading to potential bit errors during demodulation and thus reducing the robustness of the demodulation circuit.
[0029] In contrast, from Figure 8b As can be seen from the waveform diagram, under the same PVT variation conditions, the charge pump using the self-calibrating current feedback circuit described in this invention exhibits a significant reduction in output voltage fluctuation after the calibration process. This result verifies that the self-calibrating current feedback circuit proposed in this invention can effectively suppress the influence of PVT variations on the output voltage, thereby significantly improving the robustness of the PPM demodulation process.
[0030] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A highly robust pulse position modulation signal receiver, characterized in that, Includes PPM decoding circuit, clock data recovery circuit, current-to-analog converter and self-calibrating current feedback circuit; The clock data recovery circuit receives a PPM signal S containing data. PPM The rising edge of the PPM signal is captured and continuously divided to generate two clock signals, CLKB and CLK_JZ. The generated CLKB and CLK_JZ are input to the self-calibrating current feedback circuit. The PPM decoding circuit sends a feedback signal OUT_BACK to the self-calibrating current feedback circuit. The self-calibrating current feedback circuit is triggered by a reset signal RSTN to enter calibration mode. In calibration mode, CLK_JZ is selected as the working clock and its output is used as the input clock CLK_CP of the PPM decoding circuit. At the same time, the input feedback signal OUT_BACK is judged and the control word I_CTRL is output to the current digital-to-analog converter. After calibration is completed according to the judgment result, the output CLKB is selected as the input clock CLK_CP of the PPM decoding circuit. The current-to-analog converter receives the reference current I_BG from the bandgap reference and the control word I_CTRL from the self-calibrating current feedback circuit as input, outputs the current I_CP to the PPM decoding circuit, and finally outputs the demodulated data DATA from the PPM decoding circuit.
2. The pulse position modulation signal receiver as described in claim 1, characterized in that, The clock data recovery circuit includes: A D flip-flop DFF2 has its CLK terminal connected to the PPM signal S. PPM The D terminal is self-connected to its QN terminal, and its Q terminal outputs the divided clock CLKB. A D flip-flop DFF3 has its CLK terminal connected to the Q terminal of a D flip-flop DFF2 and inputs a clock CLKB. The D terminal is self-connected to its QN terminal, and the Q terminal outputs a clock CLK_JZ.
3. The pulse position modulation signal receiver as described in claim 1, characterized in that, The circuit of the current-to-analog converter includes: A current mirror transistor MP1 has its gate input connected to current I_BG, its drain connected to the gate, and its source connected to VDD. Multiple IDAC units, each with I_BG and control word I_CTRL as input, and multiple IDAC units are combined to output I_CP.
4. The pulse position modulation signal receiver as described in claim 3, characterized in that, Each IDAC unit includes: An inverter INV <1> One end is connected to the control word I_CTRL, and the other end is connected to MP. <1> The gate; A pair of transmission gates, including switching transistors MN <1> With switching transistor MP <1> MP <1> The gate connection INV <1> MP <1> The source connection MN <1> The source and input I_BG, MP <1> Drain connection MN <1> Drain of MN; <1> Gate connection control word I_CTRL, MN <1> source connection MP <1> The source is then input into I_BG; A switching transistor MP <2> Its gate is connected to the control word I_CTRL, and its source is connected to MN. <1> The drain is connected to VDD; A current mirror tube MP <3> In multiple IDAC cells, the MOS transistor width W increases in a binary order, MP <3> The gate connection of the switching transistor MP <2> The source is connected to VDD, and the drain outputs I_CP.
5. The pulse position modulation signal receiver as described in claim 1, characterized in that, The PPM decoding circuit includes: A charge pump, with input clock CLK_CP and current I_CP, and output clock pulse signal CP_OUT; A switching transistor MN_SW, with its source connected to GND and its drain connected to CP_OUT; An inverter INV1 is input with a reset signal RSTN, and its output is connected to the gate of the switch MN_SW; A capacitor C1 is connected to CP_OUT at one end and to GND at the other end. A pair of voltage divider resistors R1 and R2, one end of R1 is connected to VDD and the other end is connected to the reference voltage VREF1; one end of R2 is connected to the reference voltage VREF1 and the other end is connected to GND. A comparator 1 has its negative input connected to VREF1, its positive input connected to CP_OUT, and its output OUT_BACK; A D flip-flop DFF1 consists of two SR latches connected end to end. Its D terminal outputs the signal OUT_BACK, its CLK terminal is connected to CLK_CP, its Q terminal outputs DATA, and its QN terminal is left floating.
6. The pulse position modulation signal receiver as described in claim 5, characterized in that, The charge pump includes switching transistors MN1 and MP2. The gate of MN1 is connected to the gate of MP2 and connected to CLK_CP, the source is connected to GND, and the drain is connected to the drain of MP2 and connected to CP_OUT. The gate of MP2 is connected to the gate of MN1 and connected to CLK_CP, the source is connected to VDD, and the drain is connected to the drain of MN1 and connected to CP_OUT. The charge pump works in conjunction with capacitor C1. The current of I_CP is controlled by two switching transistors, MP2 and MN1, to charge and discharge capacitor C1, thus completing the charge pump operation. When the clock signal CLK_CP is "1", transistor MN1 is turned on, and capacitor C1 is discharged. When CLK_CP is "0", transistor MP2 is turned on, and capacitor C1 is charged. During the charging and discharging process of the capacitor, the positive input terminal of comparator 1 will generate a high voltage that varies with the duty cycle of CLK_CP. Comparing this voltage with the reference voltage of VREF1 will output the demodulated signal.
7. The pulse position modulation signal receiver as described in claim 5, characterized in that, The comparator 1 is used to complete the signal digitization processing. It is connected to I1 as a current source. The comparator 1 includes switching transistors: MP3, MP4, MP5, MP6, MP7, MP8, MN2, MN3, MN4, MN5, MN6, and MN7. Among them, MP3 and MP4 form a current mirror. The source of MP3 is connected to VDD, the gate is connected to node VZ1, and the drain is connected to the gate and connected to I1. The source of MP4 is connected to VDD, the gate is connected to node VZ1, and the drain is connected to node VA. MP5 and MP6 form a current mirror. The source of MP5 is connected to VDD, the gate is connected to node VZ2, and the drain is connected to the gate and MN2. The source of MP6 is connected to VDD, and the gate is connected to node VZ2. MN2 and MN7 form an output pair. The source of MN2 is connected to GND, the gate is connected to node VX, and the drain is connected to node VZ2. The source of MN7 is connected to GND, the gate is connected to node VY, and the drain is connected to the drain of MP6. MP7 and MP8 form an input pair. The source of MP7 is connected to node VA, the gate is connected to VIN+, and the drain is connected to node VX. The source of MP8 is connected to node VA, the gate is connected to VIN-, and the drain is connected to node VY. MN3, MN4, MN5, and MN6 form the load transistors. The source of MN3 is connected to GND, the gate is connected to node VX, and the drain is connected to the gate and then to node VX. The source of MN6 is connected to GND, the gate is connected to node VY, and the drain is connected to the gate and then to node VY. The source of MN4 is connected to GND, the gate is connected to node VX, and the drain is connected to node VY. The source of MN5 is connected to GND, the gate is connected to node VY, and the drain is connected to node VX.
8. The pulse position modulation signal receiver as described in claim 1, characterized in that, The self-calibrating current feedback circuit includes: A reset module sets the control word I_CTRL to 0 when the input reset signal RSTN is 0, and enters calibration mode when it is 1. A clock selection module, after RSTN is initialized to 0 and enters calibration mode, selects CLK_JZ as the CLK_CP output, and after calibration is completed, selects CLKB as the CLK_CP output; A calibration mode module takes the feedback signal OUT_BACK as input and the control word I_CTRL as output. After RSTN is initialized to 0, it enters calibration mode and uses the clock CLK_CP to judge OUT_BACK. If it is 1, I_CTRL is incremented by 1, and then it returns to judging OUT_BACK. If it is 0, the calibration ends.