Zero common mode modulation with digital feedback to prevent common mode resonance and suppress crossover distortion

Abstract

The present invention is in the field of underlying electronic circuits, in particular audio amplifiers, more particularly class D amplifiers, such as for digital audio converters and digital amplifier controllers, chips comprising said audio amplifiers, and devices comprising said audio amplifiers or said chips.

Description

Technical Field

[0001] This invention belongs to the field of basic electronic circuits, specifically audio amplifiers, more specifically Class D amplifiers, such as those for digital audio converters and digital amplifier controllers, chips including said audio amplifiers, and devices including said audio amplifiers or said chips. Related applications

[0002] This application claims priority to Dutch patent application NL2034708, filed on April 26, 2023, in the name of Akgen GmbH, Netherlands.

[0003] The entire contents of the foregoing application and all priority documents referenced in any existing or future application data sheets filed with this application are incorporated herein by reference for all purposes. Background Technology

[0004] An audio power amplifier comprises basic electronic circuitry that amplifies low-power audio signals entering the circuitry to a level high enough to drive speakers. Audio power amplifiers have a wide range of applications. They can be combined in chains of electronic components or circuits, each performing an individual task or participating in a collective one. Essentially, any audio signal can be supplied to a power amplifier, which is common practice. The output power of an audio amplifier can range from a few watts to tens or hundreds of watts, and sometimes even multiples thereof. Power amplifiers are typically integrated into (final) products or integrated circuits.

[0005] The design parameters of an audio power amplifier include frequency response, gain, noise, and distortion, which are often interdependent.

[0006] Class D amplifiers are commonly used in modern consumer electronics audio products, subwoofers, and sound reinforcement systems. Amplifiers can include filters, preamplifiers, power output stages, etc. Audio filters are typically frequency-dependent circuits. They are designed to operate within a specific audio frequency range. It should be noted that the human hearing range is generally considered to be from 20 Hz to 20,000 Hz. However, there is considerable individual variation, especially at higher frequencies. Furthermore, sensitivity to high frequencies typically decreases with age. Additionally, sensitivity to specific frequencies can vary with the frequency itself. Therefore, the audio frequency range commonly used in audio amplifiers is approximately 20 Hz to 20 kHz, and sometimes up to 40 kHz or even 80 kHz. Audio filters are designed to amplify, pass through, or attenuate a specific frequency range. Many types of filters exist, such as low-pass filters, high-pass filters, band-pass filters, and all-pass filters that affect the phase and amplitude of a given frequency component.

[0007] In battery-powered amplifiers, reducing power loss is key to extending battery life (and / or reducing battery costs). In Class D amplifiers with AD / BD modulation, losses at low output power typically consist primarily of switching losses and (conductive / magnetic) inductance ripple losses.

[0008] In DOI:10.1109 / JSSC.2017.2731812, Schinkel et al. introduced a 5×80W Class D audio power amplifier for automotive applications. The amplifier is implemented using a 140-nm bipolar CMOS DMOS SOI. Configurable digital loop filters compensate for a series of LC output filters, and their high loop gain (>50dB between 20Hz and 20kHz) suppresses non-ideal characteristics of the output filters and enables low-cost output filter components. A key component is an integrated low-latency ΔΣ analog-to-digital converter (ADC) that digitizes the output signal directly at the speaker load after the output filters. The ADC uses a filtered finite impulse response ADC in its feedback path to create an input-output transfer with a negative group delay at low frequencies. The ADC features a 116-dBA dynamic range and -108dB total harmonic distortion (THD). This bridged load amplifier supports polyphase pulse width modulation to reduce electromagnetic interference. Its operating voltage ranges from 6V to 25V, with a load as low as 1Ω, an no-load noise (Awtd) of 19-μV, and a THD+N of 0.004%. US 2019 / 081621 A1 discloses a programmable pulse width modulator (PWM) controller, a chip including the PWM controller, a device including the PWM controller or the chip, and uses thereof, the PWM controller including filters and mixers, such as for digital audio converters and digital amplifier controllers.

[0009] The purpose of this invention is to overcome the shortcomings of existing audio amplifiers without compromising their functionality and advantages. Summary of the Invention

[0010] A first aspect of the invention relates to a digital control loop (10) for a signal amplifier (such as an audio amplifier, specifically a Class D amplifier), comprising: at least one input (21, 31) configured to receive a digital electronic signal, specifically a single-ended input signal that will ultimately serve as a differential-mode output signal; the at least one input being configured to provide input to at least one first adder (41), wherein the at least one first adder is configured to provide input to at least one differential-mode loop filter (DMLF) (20), wherein the at least one DMLF is configured to provide input to at least one second adder (42) and at least one third adder (43), wherein the second adder is configured to provide input to at least one first pulse width modulator (PWM) (61), the first PWM being configured to provide an output; wherein the third adder is configured to provide input to at least one second pulse width modulator (PWM) (62), the second PWM being configured to provide an output. The circuit is configured to provide an output; at least one common-mode loop filter (CMLF) (30), wherein the CMLF is configured to provide inputs to at least one second adder and at least one third adder; and at least one low-delay analog-to-digital converter (LLADC) (70), wherein the at least one LLADC is configured to provide inputs to at least one first adder and to at least one fourth adder (44) and / or at least one CMLF, and is configured to receive inputs from at least one output filter, specifically receiving analog inputs; at least one differential limiting controller (DCC) (50), which is configured to receive inputs from at least one second adder (42) and at least one third adder (43), and to provide outputs to at least one first pulse width modulator (PWM) and at least one second pulse width modulator (PWM), wherein the digital control loop is configured to provide substantially zero common-mode modulation. Differential signaling generally refers to a technique that uses two complementary signals to transmit electrical information. This technique transmits the same electrical signals as a differential signal pair, each signal residing in its respective conductor. A conductor pair can be a twisted pair, ribbon cable, or trace on a printed circuit board. Electrically, these two conductors typically carry voltage signals of equal amplitude but opposite polarity. The receiving circuit responds to the difference between these two signals, producing a signal with twice the amplitude. Differential signals themselves do not typically balance the line, and noise suppression in balanced circuits does not require differential signals. A common-mode signal typically refers to the voltage shared by the two input terminals of an electrical device. In most circuits, the signal is transmitted through a differential voltage between two conductors. If the voltages on these conductors are U1 and U2, the common-mode signal is half the sum of these two voltages. When referenced to a local common terminal or ground, the common-mode signal appears on both lines of a two-wire cable, with the same phase and equal amplitude. Technically, the common-mode voltage is half the vector sum of the voltages from each conductor to local ground or common terminal in a balanced circuit.Such signals can originate from a variety of sources. Noise induced in or transmitted through cables often appears in common-mode form because the same signal tends to be picked up by both conductors in a two-wire cable. Similarly, RF noise transmitted through a cable tends to emanate from both conductors. Eliminating common-mode signals on cables entering or leaving electronic equipment is generally crucial for ensuring electromagnetic compatibility. The differential signals at the current differential-mode loop control output are typically two complementary signals; however, in an exemplary embodiment, one terminal is grounded while the other carries the signal. The current input is used to create the differential output. In this respect, for better understanding, differential electronic signals are always considered as signal pairs, i.e., positive and negative variants of the signal, used to reduce noise after transmission through the cable. BD modulation involves a modulation scheme developed to significantly reduce output filtering. This modulation scheme minimizes switching current. Zero common-mode modulation is considered a form of BD modulation where the common-mode component is (near) zero in the absence of the differential component and remains at a minimum in the presence of the differential component. This results in a very efficient switching scheme, specifically in Class D audio amplifiers, because only one half-bridge is switched at a time. The term "zero common-mode modulation" is used to indicate keeping the common-mode signal near or equal to zero in an idle mode and modulating it when providing the output (see also the figure). Therefore, more accurately, it refers to near-zero low common-mode modulation, as well as energy-efficient PWM, zero-idle common-mode modulation, etc. The prior art problem with this modulation scheme is that the common-mode offset is large when the signal frequency doubles, which can cause LC filter resonance. This resonance results in additional losses and interferes with the differential-mode audio signal. This invention provides a (digital) common-mode loop that, for example, suppresses such resonances without the use of additional (lossy) analog components. In addition to this common-mode loop, a (digital) differential-mode loop is provided that allows for high loop gain, for example, in a high bandwidth (covering the entire audio frequency band from 0Hz to 20kHz). This higher-order differential-mode loop can be used to suppress crossover distortion, which can occur when one half-bridge takes over the other. At, for example, the zero-crossing point of a sine wave, the power stage may need to generate very small pulses. These small pulses often become distorted (longer / shorter / lower than expected) due to typical imperfect switching. This can lead to distortion at these zero-crossing points. The current DM loop suppresses this distortion. Using the current zero common-mode modulation configuration, inductor current ripple is reduced to near zero and is therefore considered negligible, specifically in idle mode. Furthermore, switching losses are reduced because only one half-bridge switches at a time. This is considered particularly relevant to non-zero signals. However, it typically doubles the switching frequency at the effective decision point, thus negating this. Pulse skipping in idle mode helps reduce switching losses. The power consumption of the audio amplifier is also reduced, specifically at lower output power.Furthermore, by using the current CMLF, the common-mode LC resonance in the Class D audio amplifier employing zero common-mode modulation is also reduced. And, by using the current DMLF, crossover distortion caused by zero common-mode modulation is also reduced. Crossover distortion is reduced by approximately 60 dB, and / or the amplitude is reduced by approximately 1000 times. Common-mode ringing is reduced by approximately 20 dB, and / or the amplitude is reduced by approximately 10 times. The low latency of the LLADC is preferably one clock cycle, and therefore typically within 50 nanoseconds. This provides the audio processor with ample time to process the signal. Typically, the processor can provide feedback within 20 ADC clock cycles, and preferably within 10 ADC clock cycles, such as within 5 clock cycles. This is considered quite complex.

[0011] A second aspect of the invention relates to an audio amplifier, specifically a Class D amplifier, including at least one digital control loop according to the invention.

[0012] A third aspect of the invention relates to an integrated circuit comprising an audio amplifier or at least one digital control loop according to the invention.

[0013] A fourth aspect of the invention relates to a product comprising at least one digital control loop according to the invention or an audio amplifier according to the invention, specifically, wherein the product is an audio product, more specifically, wherein the product is selected from portable speakers, battery-powered speakers, AC-powered heatsinkless amplifiers (specifically high-power heatsinkless amplifiers), electric motors, and AC-powered heatsinkless active speakers (specifically high-power heatsinkless active speakers).

[0014] Various applications of the present invention can be considered. For example, portable speakers, battery-powered speakers, AC-powered (high-power) heatsinkless amplifiers, and AC-powered (high-power) heatsinkless active speakers.

[0015] Therefore, the present invention provides a solution to one or more of the above-mentioned problems.

[0016] The advantages described herein are explained in detail throughout this specification. Detailed Implementation

[0017] The first aspect of the invention relates to a digital control loop (10) for an audio amplifier (specifically a Class D amplifier).

[0018] In an exemplary embodiment of the current digital control loop, at least one LLADC is configured to receive input from at least two terminals of the audio output filter (92).

[0019] In an exemplary embodiment of the current digital control loop, at least one first adder is configured to subtract the LLADC input.

[0020] In an exemplary embodiment of the current digital control loop, at least one second adder is configured to add the DMLF input and the CMLF input.

[0021] In an exemplary embodiment of the current digital control loop, at least one third adder is configured to add the CMLF input and subtract the DMLF input.

[0022] In an exemplary embodiment of the present digital control loop, the digital control loop is configured to operate at an output power stage operating voltage of -100 to +100V (specifically -50 to +50V), and / or wherein the digital control loop is configured to operate at a voltage of 0.5 to 5V (such as 1 to 2V), and is configured to control the power stage at the voltage of said 0.5 to 5V.

[0023] The current digital control loop is configured to provide basic zero common-mode modulation.

[0024] In an exemplary embodiment of the current digital control loop, at least one LLADC is configured to include at least two resistors electrically contacting a respective input of the at least one LLADC, or wherein the at least one LLADC is configured to receive input from at least two resistors electrically contacting a respective input of the at least one LLADC, specifically wherein each of the at least two resistors is a voltage-to-current conversion resistor. This provides the advantage of scaling output power and noise while maintaining optimal dynamic range of the LLADC. Lower required output power implies lower resistance values, and therefore lower noise.

[0025] In an exemplary embodiment of the current digital control loop, at least two resistors each independently have a resistance value of 100kΩ to 50kΩ, specifically 1kΩ to 30kΩ, more specifically 2kΩ to 15kΩ, such as 3kΩ to 7kΩ.

[0026] In an exemplary embodiment of the current digital control loop, at least one LLADC is configured to operate at a current of 1-100mA, specifically 2-50mA, and more specifically 3-10mA.

[0027] In an exemplary embodiment of the current digital control loop, at least one LLADC is independently configured to provide input to at least one fourth adder (44), wherein the at least one fourth adder is configured to add the LLADC output to at least one second input (31) (specifically a common-mode input) and provide input to at least one CMLF. This suppresses common-mode LC resonance to prevent over-resonance of the LC resonant circuit, which would lead to instability in the differential-mode loop and increased losses in the LC output filter. Furthermore, the input can be 0V or its digital equivalent.

[0028] In an exemplary embodiment of the current digital control loop, at least one of a first PWM and at least one second PWM is independently configured to be connected to a power stage (91), and wherein the power stage is configured to increase the output voltage, specifically by increasing the output voltage by 1-2 times relative to the output voltage of the at least one PWM. 7 Times. Figures 3 and 4 provide examples.

[0029] In an exemplary embodiment, the current digital control loop includes: at least one digital input of a DMLF (21) configured to provide input to at least one first adder (41); and at least one digital input of a CMLF (31) configured to provide input to at least one fourth adder (44), the at least one fourth adder being configured to provide input to at least one CMLF. For example, the common-mode input is configured to provide zero as input, or is configured to provide the absolute value of the differential-mode signal as input, or provides the square of the differential-mode signal as input, representing the envelope of the differential-mode signal.

[0030] The current digital control loop includes at least one differential limit controller DCC (50), which is configured to receive inputs from at least one second adder (42) and at least one third adder (43) and to provide outputs to at least one first pulse width modulator (PWM) and at least one second pulse width modulator (PWM).

[0031] In an exemplary embodiment of the current digital control loop, the DCC includes: at least one first DCC limiter (52) and at least one second DCC limiter (53), wherein each limiter is individually configured to receive inputs from at least one second adder and at least one third adder (43), respectively; and at least four DCC adders (54a, 54b, 54c, 54d), wherein the first DCC adder (54a) is configured to receive inputs from at least one second adder (42) and the first DCC limiter (52), and subtract the output of the first DCC limiter (52) from the output of at least one second adder (42), and provide the output to the fourth DCC adder (54d), and wherein the second DCC adder (54b) is configured to receive inputs from the first DCC limiter (52) and the third DCC adder (54c), and subtract the output of the first DCC limiter (52) from the output of the first DCC limiter (53), and provide the output to the fourth DCC adder (54d), and wherein the second DCC adder (54b) is configured to receive inputs from the first DCC limiter (52) and the third DCC adder (54c), and subtract the output of the first DCC limiter (53) from the output of the first DCC limiter (54d), and provide the output to the fourth DCC adder (54d), and wherein the second DCC adder (54b) is configured to receive inputs from the first DCC limiter (52) and the third DCC adder (54c), and subtract the output of the first DCC limiter (54d) from the output of the first DCC limiter (54c), and provide the output to the fourth DCC adder (54d), and wherein the second DCC adder (54b) is configured to receive inputs from the first DCC limiter (52) and the third DCC adder (54c), and subtract the output of the first DCC limiter (54d The input of a third DCC adder (54c) is subtracted from the output of the amplifier (52), and the output is provided to at least one first PWM (61). The third DCC adder (54c) is configured to receive inputs from at least one third adder (43) and a second DCC limiter (53), and to subtract the output of at least one second DCC limiter (53) from the output of the at least one third adder (43), and to provide the output to a second DCC adder (54b). A fourth DCC adder (52d) is configured to receive inputs from the second DCC limiter (53) and the first DCC adder (54a), and to subtract the output of the first DCC adder (54a) from the output of the second DCC limiter (53), and to provide the output to at least one second PWM (62). Specifically, when either limiter limits the signal, the DCC is configured to retain the differential signal. An example of this is given in Figure 3.

[0032] In an exemplary embodiment, the current audio amplifier further includes at least one power stage configured to receive inputs from at least one first PWM and at least one second PWM.

[0033] In an exemplary embodiment, the current audio amplifier further includes an output stage comprising an output filter configured to receive input from at least one power stage, configured to provide an output to a speaker, and configured to provide an input to an LLADC.

[0034] Although the invention has been described in a detailed illustrative context, it can be better understood in conjunction with the accompanying examples and drawings. Figure Summary

[0035] Figures 1-2 , Figures 3a-3d , Figures 4a-d , Figures 5a-d , Figures 6a-d , Figures 7a-d , Figure 8 a- Figure 8 f、 Figures 9-12 and Figure 13a , Figure 13b Examples of the present invention are provided. Detailed description of the attached figures

[0036] These figures are exemplary. The elements in the figures can be combined.

[0037] In the attached diagram:

[0038] 10 digital control loops

[0039] 20 Differential Mode Loop Filter (DMLF)

[0040] 21 Digital Inputs for DMLF

[0041] 30 Common Mode Loop Filter (CMLF)

[0042] 31 Digital Inputs for CMLF

[0043] 41 First Adder

[0044] 42 Second Adder

[0045] 43 Third Adder

[0046] 44 Fourth Adder

[0047] 50 Differential Limiter Controller

[0048] 52 First DCC Limiter

[0049] 53 Second DCC Limiter

[0050] 54a First DCC Adder

[0051] 54b Second DCC Adder

[0052] 54c Third DCC Adder

[0053] 54d Fourth DCC Adder

[0054] 61 First Pulse Width Modulator (PWM)

[0055] 62 Second Pulse Width Modulator (PWM)

[0056] 70 Low-Latency Analog-to-Digital Converter [Details]

[0057] 71 common-mode LLADC output

[0058] 72 Differential Mode LLADC Output

[0059] 80V / C / D voltage to current conversion resistor

[0060] 91 power level

[0061] 92 Output Filter

[0062] 93 (speaker) load

[0063] Figure 1 The different components of the system are described. The system consists of a digital differential-mode loop and a common-mode loop.

[0064] Figure 2 A possible implementation of differential limiting control is shown. This implementation prioritizes the differential signal to ensure that the differential signal is preserved even when either input signal is limited.

[0065] Figure 3 illustrates the PWM carriers of the first and second PWM, the inputs and outputs of the differential limiting control, and the PWM waveforms generated by the first and second PWM. These PWM waveforms are derived by comparing the PWM carrier of the first PWM with the first output of the DCC, and the PWM carrier of the second PWM with the second output of the DCC. These PWM waveforms are the outputs of the first and second PWM and are amplified by the power stage. This example uses a 20kHz sine wave as the input signal and the PWM carrier frequency is 1024kHz.

[0066] Figure 4 shows the amplified and filtered PWM waveforms (Figures 4a and 4b), and the resulting differential-mode output (Figure 4c) and common-mode output (Figure 4d). This example uses the same 20kHz sine wave as the input signal, and the PWM carrier frequency is 1024kHz. In this example, the power stage supply voltage is 50V. The output filter inductor used in this example is 10µH, the output filter capacitor is 1µF, and the differential (speaker) load is 4.5Ohm.

[0067] Figure 5 illustrates the same situation, but with an input signal of 1 kHz instead of 20 kHz. This clearly shows that only one half-bridge is switching at any given time. This also demonstrates the drawback of this modulation scheme; at the zero-crossing point of the sine wave, one half-bridge takes over from the other. At this point, the power stage needs to emit very small pulses to accurately track the input signal. Even a tiny deviation in pulse width will cause distortion in the output signal.

[0068] Figure 6 shows the same signal as Figures 4 and 5, but in an idle state (no differential input / output signal). This demonstrates the advantage over typical BD modulation (switching at 50% duty cycle during idle (Figure 7)). This results in ripple current in the inductor, causing losses. Zero common-mode modulation produces only very small pulses, meaning the inductor current ripple is almost zero. This reduces the losses associated with ripple current in the inductor and power stage to almost zero. Furthermore, only one half-bridge switches at a time, reducing the effective switching frequency of each half-bridge by a factor of 2. This reduces all losses associated with power stage switching by a factor of 2. This also shows that both the differential and common-mode outputs are essentially zero in the idle state.

[0069] Figure 7, at least in part, relates to a prior art embodiment, illustrating the same situation as Figure 6, but specifically for BD modulation. This shows both half-bridges switching simultaneously with a 50% duty cycle in the idle state. In this example, the differential output is zero, but the common-mode output is 25V (50% of the power stage's supply voltage). This results in significant ripple current in the output filter inductor and associated losses in the inductor and output stage.

[0070] Figure 8 a- Figure 8 c: BD modulation output waveform; Figure 8 d- Figure 8 f: Zero common-mode modulation waveform. For example... Figure 1 As shown, V+ is one side of the speaker load, and V- is the other side of the speaker load.

[0071] Figure 9 The transfer function of an example differential-mode loop filter is shown, which has high gain in the 0–20 kHz frequency band to suppress any distortion introduced in the DCC, power stage, and LC output filters.

[0072] Figure 10 The transfer function of an example common-mode loop filter is shown. The combined effect of LC transfer and LLADC transfer produces a damped common-mode response.

[0073] Figure 11 The common-mode transfer function from the PWM to the (speaker) output is shown. The dashed line indicates the case without a common-mode loop. The solid line indicates the case with the common-mode loop enabled. This illustrates common-mode loop suppression of common-mode resonance. The advantage of this suppression is that harmonics at the input frequency are not amplified by the high peaks in the CM transmission. Figure 13 further illustrates this.

[0074] Figure 12 The differential-mode spectrum measured at the loudspeaker load under zero common-mode modulation is shown. This demonstrates the advantages of a high-order digital control loop, which has, for example... Figure 9The loop filter transfer function is shown. The spectrum illustrates a low-noise and low-distortion input signal at 20 kHz.

[0075] Figures 13a-13b The common-mode and differential-mode spectra measured on the loudspeaker load under zero common-mode modulation are shown. Figure 13a The spectrum is shown when the common-mode loop is disabled. Figure 13b The spectrum is shown when the common-mode loop is enabled. This demonstrates that when the common-mode loop is disabled, the 4th harmonic of the 12.25kHz sine wave is amplified by the common-mode response of the LC filter. This causes differential-mode overload, thus increasing noise at the speaker load. When the common-mode loop is enabled, the 4th harmonic is not amplified, and the differential-mode loop is not overloaded, thus keeping the noise at the speaker load at a low level.

[0076] Throughout this specification, detailed drawings and advantages of the embodiments disclosed herein are provided.

Claims

1. A digital control loop (10) for a signal amplifier, specifically an audio amplifier, more specifically a Class D amplifier, said digital control loop comprising: - At least one input (21, 31) is configured to receive a digital electronic signal, said at least one input being configured to provide input to one of the following: - At least one first adder (41), wherein the at least one first adder is configured to provide input to one of the following: - At least one differential-mode loop filter DMLF (20), wherein the at least one DMLF is configured to provide inputs to the following two items: - At least one second adder (42) and at least one third adder (43). The second adder is configured to provide input to one of the following: - At least one first pulse width modulator (PWM) (61), the first PWM being configured to provide an output. The third adder is configured to provide input to one of the following: - At least one second pulse width modulator (PWM) (62), the second PWM being configured to provide an output. At least one common-mode loop filter (CMLF) (30), wherein the CMLF is configured to provide input to the at least one second adder and the at least one third adder. At least one low-latency analog-to-digital converter (LLADC) (70), wherein the at least one LLADC is configured to provide input to the at least one first adder and to the at least one CMLF, and is configured to receive input from at least one output filter, specifically receiving analog input, and At least one differential limiting controller DCC (50), the at least one DCC being configured to receive inputs from the at least one second adder (42) and the at least one third adder (43), and to provide outputs to the at least one first pulse width modulator (PWM) and the at least one second pulse width modulator (PWM). The digital control loop is configured to provide basic zero common-mode modulation.

2. The digital control loop for an audio amplifier according to claim 1, wherein, The at least one LLADC is configured to receive input from at least two terminals of the audio output filter (92).

3. The digital control loop for an audio amplifier according to any one of claims 1-2, wherein, The at least one first adder is configured to subtract the LLADC input.

4. The digital control loop for an audio amplifier according to any one of claims 1-3, wherein, The at least one second adder is configured to add the DMLF input and the CMLF input.

5. The digital control loop for an audio amplifier according to any one of claims 1-4, wherein, The at least one third adder is configured to add the CMLF input and subtract the DMLF input.

6. The digital control loop for an audio amplifier according to any one of claims 1-5, wherein, The digital control loop is configured to operate at an output power stage operating voltage of -100V to +100V, specifically -50V to +50V, and / or where... The digital control loop is configured to operate at a voltage of 0.5V to 5V, such as 1V to 2V.

7. The digital control loop for an audio amplifier according to any one of claims 1-6, wherein, The at least one LLADC is configured to include at least two resistors that are electrically in contact with a corresponding input of the at least one LLADC, or wherein the at least one LLADC is configured to receive input from at least two resistors that are electrically in contact with a corresponding input of the at least one LLADC, specifically wherein each of the at least two resistors is a voltage-to-current conversion resistor.

8. The digital control loop for an audio amplifier according to claim 7, wherein, The at least two resistors each have an independent resistance value of 100kΩ to 50kΩ, particularly 1kΩ to 30kΩ, and more specifically 2kΩ to 15kΩ.

9. The digital control loop for an audio amplifier according to any one of claims 1 to 8, wherein, The at least one LLADC is configured to operate at a current of 1mA to 100mA, specifically 2mA to 50mA, and more specifically 3mA to 10mA.

10. The digital control loop for an audio amplifier according to any one of claims 1-9, wherein, Each of the at least one LLADC is independently configured to provide input to at least one fourth adder (44), wherein the at least one fourth adder is configured to subtract the LLADC output from at least one second input (31) and provide input to the at least one CMLF, wherein the at least one second input (31) is specifically a common-mode input.

11. The digital control loop for an audio amplifier according to any one of claims 1-10, wherein, At least one of the at least one first PWM and at least one second PWM is independently configured to be connected to a power stage (91), and wherein the power stage is configured to increase the output voltage, specifically by increasing the output voltage by 1 to 2 times relative to the output voltage of the at least one PWM. 7 times.

12. The digital control loop for an audio amplifier according to any one of claims 1-11, comprising: At least one digital input for the DMLF is configured to provide input to the at least one first adder (41); And at least one digital input for CMLF, configured to provide input to at least one fourth adder (44), the at least one fourth adder being configured to provide input to the at least one CMLF.

13. The digital control loop for an audio amplifier according to any one of claims 1-12, wherein, The DCC includes: -At least one first limiter (52), and - At least one second limiter (53), wherein each limiter is independently configured to receive inputs from the at least one second adder (42) and the at least one third adder (43), respectively, and - At least four DCC adders (54a, 54b, 54c, 54d). - Wherein, the first DCC adder (54a) is configured to receive inputs from the at least one second adder and from the first DCC limiter, subtract the output of the first DCC limiter from the outputs of the at least one second adder, and provide an output to the fourth DCC adder (54d), and - Wherein, the second DCC adder (54b) is configured to receive inputs from the first DCC limiter and from the third DCC adder, subtract the output of the third DCC adder from the output of the first DCC limiter, and provide an output to the at least one first PWM (61). - Wherein, the third DCC adder (54c) is configured to receive inputs from the at least one third adder and from the second DCC limiter, subtract the output of the second DCC limiter from the output of the at least one third adder, and provide an output to the second DCC adder (54b), and - Wherein, the fourth DCC adder (52d) is configured to receive inputs from the second DCC limiter and from the first DCC adder, subtract the output of the first DCC adder from the output of the second DCC limiter, and provide an output to the at least one second PWM (62). Specifically, the DCC is configured to retain the differential signal when any of the limiter signals in the limiter are limited.

14. An audio amplifier, specifically a Class D amplifier, comprising at least one digital control loop according to any one of claims 1-13.

15. The audio amplifier of claim 14, further comprising at least one power stage configured to receive inputs from the at least one first PWM and from the at least one second PWM.

16. The audio amplifier of any one of claims 14-15, further comprising an output stage including an output filter configured to receive an input from the at least one power stage, the output stage being configured to provide an output to a speaker and to provide an input to the at least one LLADC.

17. An integrated circuit comprising at least one digital control loop according to any one of claims 1-13, or an audio amplifier according to any one of claims 16-18.

18. A product comprising at least one digital control loop according to any one of claims 1-13, or an audio amplifier according to any one of claims 16-18, specifically, wherein, The product is an audio product, and more specifically, the product is selected from portable speakers, battery-powered speakers, AC-powered heatsinkless amplifiers, motors, and AC-powered heatsinkless active speakers, wherein the AC-powered heatsinkless amplifier is specifically a high-power heatsinkless amplifier, and the AC-powered heatsinkless active speaker is specifically a high-power heatsinkless active speaker.

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