System memory peak bandwidth measurement method and electronic device

Abstract

The application discloses a system memory peak bandwidth measurement method and electronic equipment, and relates to the technical field of bandwidth measurement. The application optimizes a memory bandwidth measurement process by cooperating with a dynamically selected maximum width vector instruction, forced non-cache access and NUMA awareness binding. The application improves single operation data throughput to 512 bits or even higher by using the vector processing capability of a CPU. The application bypasses a cache level by cooperating a non-temporal instruction with a memory barrier instruction, eliminates the interference of cache hits or jitter on measurement results, ensures that measurement results truly reflect the performance of a memory system itself, avoids delay and congestion caused by cross-node access through an automatic NUMA binding mechanism, and improves the accuracy, stability and repeatability of test results.

Description

Technical Field

[0001] This application relates to the field of bandwidth measurement technology, and in particular to a method and electronic device for measuring peak bandwidth of system memory. Background Technology

[0002] In computationally intensive scenarios such as servers, high-performance computing, and artificial intelligence training, the memory wall has become one of the most prominent system performance bottlenecks due to the increasing number of processor cores and the widespread adoption of high-bandwidth memory. Therefore, accurate measurement of the system's peak memory bandwidth is crucial for hardware selection, system capacity planning, and the quantification and billing of cloud service level agreements. Currently, related technologies use open-source tools such as lmbench (a micro-benchmarking tool) for memory bandwidth benchmarking. However, current computing architectures generally adopt non-uniform memory access designs, multi-level CPU (Central Processing Unit) caches, and wide-vector instruction sets. Based on this, related technologies suffer from problems such as insufficient instruction width, lack of affinity for non-uniform memory access, cache hierarchy interference, and limited architectural support. Therefore, how to accurately and stably measure memory bandwidth close to the theoretical peak under complex hardware architectures is an urgent problem to be solved. Summary of the Invention

[0003] This application provides a method and electronic device for measuring peak memory bandwidth in a system, in order to at least solve the problem in related technologies that it is impossible to accurately and stably measure memory bandwidth close to the theoretical peak under complex hardware architectures.

[0004] This application provides a method for measuring peak bandwidth of system memory, including:

[0005] In response to receiving a system memory peak bandwidth measurement request, the instruction set support flag of the CPU in the system is obtained. Based on the instruction set support flag, the vector instructions with the target data width supported by the CPU are determined. The system memory peak bandwidth measurement request includes the number of iterations.

[0006] Configure corresponding non-cached access instructions and memory barrier instructions based on the vector instructions of the target data width;

[0007] Obtain the topology information of the non-uniform memory access architecture, create the target test thread and the memory buffer accessed by the target test thread based on the topology information, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0008] In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task execution corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0009] Based on the number of iterations, the memory buffer access operation and the memory barrier instruction insertion operation are repeatedly executed. In response to the completion of the iteration operation, the time consumed to access the memory buffer is obtained in order to calculate and determine the peak memory bandwidth of the system.

[0010] This application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the following steps of the system memory peak bandwidth measurement method when executing the computer program:

[0011] In response to receiving a system memory peak bandwidth measurement request, the instruction set support flag of the CPU in the system is obtained. Based on the instruction set support flag, the vector instructions with the target data width supported by the CPU are determined. The system memory peak bandwidth measurement request includes the number of iterations.

[0012] Configure corresponding non-cached access instructions and memory barrier instructions based on the vector instructions of the target data width;

[0013] Obtain the topology information of the non-uniform memory access architecture, create the target test thread and the memory buffer accessed by the target test thread based on the topology information, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0014] In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task execution corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0015] Based on the number of iterations, the memory buffer access operation and the memory barrier instruction insertion operation are repeatedly executed. In response to the completion of the iteration operation, the time consumed to access the memory buffer is obtained in order to calculate and determine the peak memory bandwidth of the system.

[0016] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the following steps of a system memory peak bandwidth measurement method:

[0017] In response to receiving a system memory peak bandwidth measurement request, the instruction set support flag of the CPU in the system is obtained. Based on the instruction set support flag, the vector instructions with the target data width supported by the CPU are determined. The system memory peak bandwidth measurement request includes the number of iterations.

[0018] Configure corresponding non-cached access instructions and memory barrier instructions based on the vector instructions of the target data width;

[0019] Obtain the topology information of the non-uniform memory access architecture, create the target test thread and the memory buffer accessed by the target test thread based on the topology information, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0020] In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task execution corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0021] Based on the number of iterations, the memory buffer access operation and the memory barrier instruction insertion operation are repeatedly executed. In response to the completion of the iteration operation, the time consumed to access the memory buffer is obtained in order to calculate and determine the peak memory bandwidth of the system.

[0022] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the following steps of a method for measuring peak bandwidth of system memory:

[0023] In response to receiving a system memory peak bandwidth measurement request, the instruction set support flag of the CPU in the system is obtained. Based on the instruction set support flag, the vector instructions with the target data width supported by the CPU are determined. The system memory peak bandwidth measurement request includes the number of iterations.

[0024] Configure corresponding non-cached access instructions and memory barrier instructions based on the vector instructions of the target data width;

[0025] Obtain the topology information of the non-uniform memory access architecture, create the target test thread and the memory buffer accessed by the target test thread based on the topology information, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0026] In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task execution corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0027] Based on the number of iterations, the memory buffer access operation and the memory barrier instruction insertion operation are repeatedly executed. In response to the completion of the iteration operation, the time consumed to access the memory buffer is obtained in order to calculate and determine the peak memory bandwidth of the system.

[0028] This application optimizes the memory bandwidth measurement process by coordinating dynamic selection of maximum width vector instructions, forced uncached access, and NUMA-aware binding. By leveraging the CPU's vector processing capabilities, the data throughput of a single operation is increased to 512 bits or even higher. Through the combination of non-temporary instructions and memory barrier instructions, the cache hierarchy is bypassed, eliminating the interference of cache hits or thrashing on the measurement results, ensuring that the measurement results truly reflect the performance of the memory system itself. The automatic NUMA binding mechanism avoids the latency and congestion caused by cross-node access, improving the accuracy, stability, and repeatability of the test results. Attached Figure Description

[0029] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This application provides an application environment diagram for a system memory peak bandwidth measurement method according to an embodiment of the present application;

[0031] Figure 2 This application provides an overall flowchart of a method for measuring peak bandwidth of system memory.

[0032] Figure 3 This application provides another overall flowchart illustrating a method for measuring peak bandwidth of system memory.

[0033] Figure 4 This is a diagram of the internal structure of an electronic device in one embodiment. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0035] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0036] It should be noted that the terms "S1," "S2," etc., are used only for descriptive purposes and do not specifically refer to the order or sequence, nor are they intended to limit this application. They are merely for the convenience of describing the method of this application and should not be construed as indicating the sequential order of the steps. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0037] As the background technology indicates, in computationally intensive scenarios such as servers, high-performance computing (HPC), and artificial intelligence training, with the increasing number of processor cores and the widespread adoption of high-bandwidth memory such as DDR4, DDR5, and HBM, the memory wall has become one of the most prominent system performance bottlenecks. Therefore, accurate measurement of system memory peak bandwidth is crucial for hardware selection, system capacity planning, and the quantification and billing of cloud service level agreements (SLAs). Currently, related technologies use open-source tools such as bw_mem or STREAM in lmbench for memory bandwidth benchmarking. The basic principle of these tools is to allocate a contiguous memory buffer in user space, generate memory flow by repeatedly executing scalar load / store instructions, and use a timer to count the amount of data moved per unit time to calculate bandwidth. However, current computing architectures generally adopt non-uniform memory access (NUMA) designs, multi-level CPU caches (L1 / L2 / L3 / LLC), and wide vector instruction sets (such as AVX2 and AVX-512). Based on this, the relevant measurement methods have the following problems:

[0038] (1) Insufficient instruction width: Most related tools use 64-bit or 128-bit scalar instructions, which cannot make full use of the wide vector processing units of modern CPUs (such as 512-bit), resulting in the memory pressure generated by a single core being far lower than the theoretical transmission capacity of the memory controller. The actual bandwidth is limited by the instruction issuance efficiency of the CPU.

[0039] (2) Cache level interference: The default cache access mode causes test data to flow through all CPU cache levels. The test results are easily affected by cache hit, replacement strategy and write-back mechanism, resulting in either inflated results due to cache hit or understated results due to cache jitter, which cannot truly reflect the performance of the memory subsystem itself.

[0040] (3) Lack of NUMA affinity: The lack of automatic NUMA topology awareness and thread-memory binding mechanism makes it easy to generate cross-node memory access during testing, introducing additional latency and bus congestion, resulting in large fluctuations and poor repeatability of test results;

[0041] (4) Single architecture support: Related tools lack a unified framework to adapt to heterogeneous environments with different instruction set architectures such as x86, ARM, and RISC-V.

[0042] This application provides a method and electronic device for measuring peak memory bandwidth in a system to solve the following technical problems: fully utilizing the transmission capacity of the memory controller and physical channels by maximizing the effective data path width; eliminating the amplification or dilution effect of cache levels on bandwidth figures by using non-cached access paths; eliminating cross-node noise by using automatic NUMA topology awareness and thread-memory binding; constructing a unified cross-architecture testing framework, implementing single instruction multiple data (SIMD) access through the AVX512 instruction set, and bypassing the CPU cache level by combining non-temporal cache to reduce the impact of memory latency and improve bandwidth utilization.

[0043] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] The system memory peak bandwidth measurement method provided in this application can be applied to, for example... Figure 1 In the application environment shown, terminal 102 communicates with a data processing platform set on server 104 via a network. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Server 104 can be implemented as a standalone server or a server cluster consisting of multiple servers.

[0045] like Figure 2 As shown, embodiments of this application provide a method for measuring system memory peak bandwidth, which is applied to... Figure 1 Taking the terminal in the example, the explanation includes the following steps:

[0046] S1: In response to receiving a system memory peak bandwidth measurement request, obtain the instruction set support flag of the CPU within the system, and determine the vector instructions with the target data width supported by the CPU based on the instruction set support flag. The system memory peak bandwidth measurement request includes the number of iterations.

[0047] It should be noted that the Central Processing Unit (CPU) is a very large-scale integrated circuit, serving as the core of a computer's processing and control. Instruction set support flags are specific bits in the CPU's internal characteristic registers. Their state (0 or 1) indicates whether the CPU supports a specific instruction set extension. For example, the CPU ID instruction in the x86 architecture returns a set of characteristic bits. By checking whether a particular bit (such as the corresponding bit in AVX2) is 1, it can be determined whether the processor supports the AVX2 instruction set. Target data width vector instructions refer to single-instruction multiple-data instructions with the largest data bit width, dynamically selected based on the current CPU hardware capabilities. For example, on a CPU supporting AVX-512, the target instruction is a 512-bit vector instruction used to process as much data as possible in a single operation to maximize memory access throughput.

[0048] S2: Vector instructions based on the target data width, configuring corresponding non-cached access instructions and memory barrier instructions.

[0049] It should be noted that non-cached access instructions are a special type of CPU instruction used to bypass the CPU's multi-level cache and directly write data to or read data from memory. These instructions (such as the x86 MOVNT series) reduce cache usage and consistency overhead by avoiding data pollution of the cache, thereby significantly improving memory bandwidth utilization in scenarios with a large amount of sequential data flow and measuring more realistic memory subsystem performance. Memory barrier instructions are a type of CPU instruction that enforces the order of memory operations. They ensure that all memory access operations (such as storage) before the barrier instruction are completed before subsequent operations can be executed, preventing instruction reordering by the CPU or compiler for optimization purposes and ensuring the visibility and order of memory accesses.

[0050] S3: Obtain the topology information of the non-uniform memory access architecture, and based on the topology information, create the target test thread and the memory buffer accessed by the target test thread, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0051] It should be noted that the topology information of the non-uniform memory access architecture is structured data describing the physical connection relationship between the CPU and memory in a multiprocessor system. It describes how many NUMA nodes the system contains, which physical CPU cores each node contains, and which memory modules are directly connected to which node, revealing the speed differences in processor access to memory at different locations. The target test thread is a worker process specifically created to perform memory bandwidth tests. Its task is to perform specific memory access operations to generate memory traffic. The memory buffer accessed by the target test thread is a contiguous memory region pre-allocated according to a specified size before the test. It serves as the target object for thread read and write operations. Under the NUMA architecture, by binding the thread to a specific CPU core and allocating the buffer on the physical memory of the same NUMA node, cross-node access latency can be eliminated, ensuring that the test accurately reflects local memory performance.

[0052] S4: In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0053] It should be noted that the target data width refers to the maximum data bit width that can be processed in a single vector instruction operation, based on the current CPU hardware capabilities, during memory bandwidth testing.

[0054] S5: Based on the number of iterations, repeatedly execute memory buffer access operations and memory barrier instruction insertion operations. In response to the completion of the iteration operation, obtain the time consumed to access the memory buffer in order to calculate and determine the system's peak memory bandwidth.

[0055] It should be noted that the number of iterations refers to the cumulative value of the warm-up rounds and the formal test rounds. Accessing the memory buffer in order of target data width means reading or writing to the buffer continuously in ascending order of memory address, with the selected maximum vector width (e.g., 64 bytes) as the step size. The time consumed in accessing the memory buffer refers to the total time consumed when executing the corresponding test in the formal test round. The peak memory bandwidth refers to the maximum continuous data transfer rate that the memory subsystem can achieve under ideal conditions, usually measured in GB / s. It is determined by the memory type, frequency, number of channels, and memory controller, and is the theoretical performance limit.

[0056] In the above implementation, by coordinating the dynamic selection of maximum width vector instructions, forced non-cached access, and NUMA-aware binding, the memory bandwidth measurement process is optimized. By utilizing the CPU's vector processing capabilities, the data throughput of a single operation can be increased to 512 bits or even higher. By combining non-temporary instructions with memory barrier instructions, the cache level is bypassed, eliminating the interference of cache hits or jitter on the measurement results, ensuring that the measurement results truly reflect the performance of the memory system itself. The automatic NUMA binding mechanism avoids the latency and congestion caused by cross-node access, improving the accuracy, stability, and repeatability of the test results.

[0057] In some specific implementations, in response to receiving a system memory peak bandwidth measurement request, the method further includes:

[0058] like Figure 3 As shown, after the program starts, it parses the user's command-line parameters, that is, it parses the system memory peak bandwidth measurement request to obtain the target test parameters. The target test parameters include at least one of the following: the memory capacity to be tested Size (bytes), the number of parallel threads P, the number of warm-up rounds W, and the number of formal test rounds N. Among them, the memory capacity to be tested refers to the size of the memory region that needs to be evaluated for performance evaluation in advance for memory bandwidth testing. It is the working set size of the test, which is usually specified by the user (e.g., 1GB) and passed as a parameter to the test program to allocate a memory buffer of the corresponding size. The number of parallel threads refers to the total number of threads that run and execute memory access operations simultaneously in memory bandwidth testing. This number is usually set to be equal to or greater than the number of physical cores in the NUMA node. The number of warm-up rounds is the warm-up phase executed before the formal test. Its purpose is to allow components such as DRAM line buffers and hardware prefetchers to enter a stable state and eliminate cold start errors. The formal test rounds are the actual measurement phase after warm-up. The average bandwidth is calculated through multiple samplings to ensure that the results are stable and reliable. Warm-up allows the system to reach a steady state, and the formal rounds are used to perform accurate measurements under this steady state.

[0059] In the above implementation, the test request is parsed to extract key parameters such as the memory capacity to be tested and the number of threads, so that the test framework has high configurability and can flexibly adapt to different hardware scales (such as single node / multi-node) and test targets (such as sustainable bandwidth / peak pressure), thereby generating accurate and customized memory load and improving the practicality and comparability of measurement results.

[0060] In some specific implementations, obtaining the instruction set support flags of the central processing unit within the system includes:

[0061] The function identification information of the central processing unit is obtained. The function identification information is a set of configuration data provided by the CPU that describes the features and instruction sets it supports. This information can be obtained by executing specific instructions (such as the CPUID of x86). The program determines the hardware capabilities by parsing the feature bits (such as AVX support bits) and realizes adaptive selection of instruction sets.

[0062] The function identification information is parsed to determine the support flags corresponding to the target vector instruction set;

[0063] Based on the status of the support flag, determine whether the central processing unit supports the target vector instruction set;

[0064] In response to the state of the support flag being in the first state, it is determined that the central processing unit supports the target vector instruction set, where the first state is 1;

[0065] In response to the support flag being in the second state, it is determined that the central processing unit does not support the target vector instruction set, where the second state is 0.

[0066] In some specific implementations, the vector instructions that determine the target data width supported by the central processing unit based on the instruction set support flag include:

[0067] Obtain the priority order of the preset vector instruction data width, where the priority order can be 512-bit, 256-bit, 128-bit, and scalar instructions (64-bit).

[0068] Based on priority order, the instruction set support flags corresponding to the first state are traversed in descending order. For example, checking 512-bit support includes checking the AVX-512F flag, and checking 256-bit support includes checking the AVX2 flag. If none of the predefined vector instruction widths are supported, scalar instructions are selected by default and a downgrade warning is triggered.

[0069] Based on the traversal results, the data width of the first vector instruction marked as supported in the priority order is determined as the target data width. That is, whether the AVX-512F flag is supported or not, if supported, the target data width is 512.

[0070] Define the vector instruction corresponding to the target data width as the vector instruction supported by the central processing unit for the target data width.

[0071] Specifically, the above steps involve dynamically detecting CPU instruction set support. For example, x86: checking the AVX2 / AVX512F flag bit via CPUID; ARM: calling getauxval(AT_HWCAP) to verify SVE2 support; RISC-V: using vsetvl to obtain the variable vector length (VL); and a downgrade strategy: if AVX512 is requested but the hardware does not support it, automatically downgrade to AVX256 and issue an alarm. Further, vector instructions are initialized: x86: activating the NT (Non-Temporal) instruction set of AVX512 / AVX256; ARM: configuring SVE2 non-cached memory instructions (stntld); RISC-V: enabling RVV non-cached instructions (vse.v), using CPUID. Instructions or compiler built-in functions (such as _builtin_cpu_supports) detect the vector instruction sets supported by the processor: check the AVX2 flag (supports 256-bit vectors), check the AVX512F flag (supports 512-bit basic vectors), and check the extended bits such as AVX512BW / AVX512DQ (support specific operations); standard vectorized memory mode selection: use ordinary vectorized instructions (such as AVX-512, SVE2, RVV's store) to write data directly into the cache level. The data will remain in the cache, improving the speed of subsequent data reads. Bandwidth is affected by cache capacity and replacement strategy. The standard modes included in the three architectures are shown in Table 1.

[0072] Table 1: Standard Patterns Included in the Three Architectures

[0073]

[0074] Furthermore, the non-cached access mode selection includes performing sequential write operations using the processor's largest bit-width non-temporary memory instruction (such as 512-bit VMOVNTDQ), with a memory barrier instruction (SFENCE) inserted after each non-temporary instruction is completed: since out-of-order execution of non-cached instructions may cause memory access conflicts, the barrier instruction forces the write order, ensuring that data reaches memory directly and eliminating measurement bias. The non-cached modes included in the three architectures are shown in Table 2.

[0075] Table 2: Non-caching modes included in the three architectures

[0076]

[0077] Specifically, the above steps are used to maximize the effective data path width, that is, to dynamically detect and use the CPU's maximum bit-width vector instruction for continuous memory access to match the physical width of the memory channel (such as 64 bytes / DDR channel), thus overcoming the narrow instruction issue bottleneck. The pseudocode is as follows:

[0078] The function to get the optimal vector size():

[0079] If AVX512 is supported: return 512

[0080] If SVE2 is supported: Return the length of the ARM vector.

[0081] Otherwise, return 128.

[0082] In the above implementation, by dynamically detecting and selecting the maximum vector width supported by the current CPU, it can automatically match processors of different architectures, ensuring that the test program always performs data processing on the optimal processor, thereby generating the corresponding memory access pressure, so as to obtain the bandwidth result closest to the theoretical peak and improve the accuracy of the measurement results.

[0083] In some specific implementations, the configuration of corresponding non-cached access instructions and memory barrier instructions based on the vector instructions of the target data width includes:

[0084] The vector instruction that obtains the target data width, CPU architecture information, and mapping table are used to store the mapping relationship between the data width, CPU architecture information, and instructions.

[0085] Based on the target data width and the architecture information of the central processing unit, extract the corresponding non-cached access instruction identifier and memory barrier instruction identifier from the mapping table;

[0086] Configure the corresponding non-cached access instructions and memory barrier instructions based on the non-cached access instruction identifier and the memory barrier instruction identifier.

[0087] Specifically, based on the above steps, cache level interference is eliminated by forcing the use of non-cache access instructions (such as NT instructions) in conjunction with memory barrier instructions, so that the data flow bypasses the CPU cache level and directly accesses memory, ensuring that the measurement results reflect the true bandwidth of the memory subsystem itself, and avoiding the deviation caused by cache hit / miss and replacement strategies. This includes using non-cache write instructions, executing memory barriers after writing, and dynamic memory address jumps to avoid cache line conflicts. The instruction mapping table is shown in Table 3.

[0088] Table 3: Instruction Mapping Table

[0089]

[0090] Its pseudocode is:

[0091] Function vector storage (address, data):

[0092] If x86 platform: Execute AVX512 storage instructions

[0093] If ARM platform: Execute SVE memory instruction

[0094] In the above implementation, by matching the selected wide vector instructions with the corresponding non-cached and barrier instructions, an efficient memory access path is constructed to ensure that the generated large data stream can bypass the cache level and reach the memory in order, thereby eliminating cache interference and out-of-order execution deviation, and improving the stability and accuracy of peak bandwidth testing of the memory subsystem.

[0095] In some specific implementations, obtaining the topology information of a non-uniform memory access architecture, and based on the topology information, creating the target test thread and the memory buffer accessed by the target test thread, includes:

[0096] Obtain the topology information of the system's non-uniform memory access architecture;

[0097] Based on topology information, the target non-uniform memory access node in the non-uniform memory access architecture is determined, and a memory buffer is allocated based on the target non-uniform memory access node and the memory capacity to be tested.

[0098] Create multiple test threads based on the number of parallel threads;

[0099] Based on multiple test threads, the target test thread corresponding to the memory buffer is determined.

[0100] In some specific implementations, mapping the target test thread and the memory buffer to the same non-uniform memory access node in a non-uniform memory access architecture includes:

[0101] Set the processor affinity of the target test thread to bind to at least one physical processor core within the target non-uniform memory access node. If the target NUMA node has insufficient physical cores, mark the risk of cross-node access and label it "cross-node" in the results.

[0102] The physical storage location of the memory buffer accessed by the target test thread is allocated in the physical memory of the target non-uniform memory access node.

[0103] Specifically, the starting address of the memory buffer is aligned according to the cache line size. Alignment methods include: directly allocating aligned memory using the `aligned_alloc()` function or manually aligning via base address offset. The memory allocation, alignment, and NUMA binding steps include: NUMA binding: constructing a "node-core" mapping table and binding the test thread to the physical core of the target NUMA node using `pthread_setaffinity_np`; buffer physical location verification: calling `numactl --hardware` and rebinding using `mbind()` when crossing nodes; buffer allocation: allocating 64 bytes of aligned physical contiguous memory (BufA / BufB) using `aligned_alloc()`; pre-filling data and triggering a page fault to eliminate first-access latency. The pseudocode for its memory management is as follows:

[0104] Function initializes memory (state):

[0105] State buffer = alignment allocation(64 bytes, number of state bytes) / / 64-byte alignment

[0106] Fill buffer (0) / / Clear initialization

[0107] If a second buffer is needed:

[0108] state.buffer2 = aligned allocation(64 bytes, number of state bytes + 2048)

[0109] If alignment is required:

[0110] Adjust the buffer address (2048-128) / / Special alignment processing

[0111] In the above implementation, based on the system NUMA topology information, the test thread is bound to the physical core within the NUMA node where its target memory buffer is located, and the memory buffer is physically allocated on that node. This eliminates the additional latency and bus congestion caused by cross-NUMA node access, and improves the accuracy, repeatability and stability of the test.

[0112] In some specific implementations, within the memory bandwidth testing framework based on wide-vector instructions and uncached access, a dynamic address offset mechanism is introduced to optimize the access patterns of dynamic random access memory (DRAM), including the following steps:

[0113] Memory buffer initialization: Allocate a contiguous memory buffer based on the test memory capacity (Size) parameter, and ensure that the starting address of the buffer is aligned with the current system cache line size;

[0114] Dynamic address offset parameter settings: A maximum offset span S is preset. The maximum offset span S is in units of cache lines and is an integer between 1 and 16. A random or deterministic offset within the current span is generated for each storage operation. The maximum offset span S is adaptively adjusted according to the number of detected memory channels or DRAM configuration information. The more channels there are, the larger the allowed offset span S becomes.

[0115] Integrated non-cached access loop: In the non-cached sequential access main loop executed by the test thread, after each non-cached storage operation with the maximum data width is completed once or in a batch, the address to be accessed next is increased by a step determined by the product of the target data width and the dynamic address offset.

[0116] Offset boundary handling: During the address offset process, the current access address is monitored in real time to see if it exceeds the boundary of the initially allocated memory buffer. When an address out of bounds is detected, the access address is wrapped back to the area near the starting address of the buffer through modulo operation or address remapping technology to ensure that the entire access process is carried out within the preset buffer.

[0117] In conjunction with barrier instructions: The dynamic address offset operation is embedded between the uncached store instruction and the memory barrier instruction, ensuring that the store operation after each address jump is completed under the forced ordering protection of the memory barrier.

[0118] In the above implementation, the dynamic address offset mechanism effectively distributes the access pressure on the DRAM memory bank and rows by introducing controllable jumps in sequential access, reduces the probability of row conflicts, makes the measured sustainable memory bandwidth closer to the theoretical peak, and has less fluctuation in the results, thus improving stability and accuracy.

[0119] In some specific implementations, based on non-cached access instructions, the target test thread accesses the memory buffer sequentially according to the target data width. Upon completion of the task corresponding to the non-cached access instruction, the memory barrier insertion instruction includes:

[0120] Based on the target test thread, the memory buffer is accessed in order of target data width using the configured non-cached access instructions;

[0121] In response to the task corresponding to the current non-cached access instruction having been completed, insert a memory barrier instruction.

[0122] In some specific implementations, memory buffer access operations and memory barrier instruction insertion operations are repeatedly executed based on the number of iterations. In response to the completion of the iteration operation, the time consumed by accessing the memory buffer is obtained to calculate and determine the system's peak memory bandwidth, including:

[0123] The number of iterations is determined based on the number of warm-up rounds and the number of formal testing rounds;

[0124] Based on the number of iterations, repeat the uncached access operations to the memory buffer and the insertion operations of memory barrier instructions;

[0125] In response to the completion of the iteration operation, based on a high-precision timer, the total time consumed by accessing the memory buffer when the current iteration is in the formal test round is obtained;

[0126] The system's peak memory bandwidth is calculated based on the total time and the total amount of data accessed in the memory buffer.

[0127] Specifically, during the iterative testing process, the initial phase includes a warm-up phase, which involves continuously executing W rounds of the same test mode as the actual measurement. The purpose of the warm-up is to stabilize the DRAM row buffer: to bring the row buffer inside the DRAM chip to a steady-state access mode, avoiding the additional latency caused by the first row activation (RAS); and to stabilize the hardware prefetcher: by using continuous memory access mode, to force the CPU hardware prefetcher to enter a steady state, reducing performance jitter caused by changes in the prefetch strategy. Further, the later phase is the actual measurement phase, where the buffer is traversed in order of maximum vector width (e.g., 512 bits), and a barrier instruction (SFENCE / DSB) is inserted after each non-cache storage. SY); x86 uses RDTSCP, and ARM uses PMCCNTR (performance counter) for high-precision timing. All threads are strictly synchronized when entering and exiting the formal measurement interval through the actual synchronization mechanism pthread_barrier_wait(). Each thread is still bound to different physical cores of the same NUMA node to avoid contention between cores within the node. Cross-node concurrency (explicitly requested by the user): On the basis of single-node concurrency, an additional synchronization barrier between nodes is inserted (which may require coarser-grained synchronization primitives). The results are statistically analyzed and output as "local bandwidth" (thread access to local node memory) and "cross-node bandwidth" (thread access to remote node memory). Furthermore, empty loop calibration includes executing 30+ pure loop instructions, sampling 30 times and taking the standard deviation, and calculating the average overhead T_overhead. Its pseudocode is as follows:

[0128] Adjusted bandwidth for function computation (total time, bytes, iterations, overhead):

[0129] Pure time = (Total time / Number of iterations - Cost) / 1,000,000

[0130] Data volume in MB = Number of bytes / 1,000,000

[0131] Bandwidth = Data volume (MB) / Pure time

[0132] if bandwidth < 1: Output in decimal format

[0133] else: Output standard format.

[0134] Furthermore, the average bandwidth (bytes / second) is calculated using the bandwidth calculation formula B = Size × N / (T_avg - T_overhead), and then converted to MB / s or GB / s output. Here, B represents the actual memory bandwidth, Size represents the amount of data accessed each time, N represents the total number of iterations, T_avg - T represents the actual total time, and T_overhead represents the empty loop overhead time, i.e., the pure overhead time of the same loop but without accessing memory. At the same time, the output results are the core indicators: average bandwidth B, minimum value B_min, maximum value B_max, standard deviation σ (MB / s or GB / s) and detailed metadata: NUMA node number, thread affinity mask (CPU mask), vector width used, whether uncached access (NT) is enabled, buffer size, whether cross-node marking is used, etc.

[0135] In the above implementation, by coordinating non-cached access and barrier instructions, and combining multiple iterative measurements, it is ensured that data reaches memory directly and is completed in the order of operations, thereby accurately eliminating interference from caching and out-of-order execution and improving the accuracy of measurement results.

[0136] To verify the above method, this application conducted tests based on the method and compared it with related technologies, specifically:

[0137] 1. Based on the x86 platform;

[0138] 1) Experimental environment: Platform 1: Intel Xeon 6761P (64 cores / 64 threads, 4 NUMA nodes, memory frequency 6400MT / s, memory size 125GB, 8 channels); OS: CentOS 8.2 (kernel 4.18)

[0139] 2) Core Algorithm:

[0140] #pseudocode

[0141] AVX512 Unbuffered Write (Iteration Count, State):

[0142] pointer = state.buffer

[0143] Count = Status.Number of bytes / (64 * 8) / / Loop expansion of 8

[0144] Initialize vector group [8] / / Multi-register parallel

[0145] Loop iteration count:

[0146] Loop i from 0 to count step 8:

[0147] Perform uncached storage (pointer + i + 0, vector[0])

[0148] Perform uncached storage (pointer + i + 1, vector[1]) ...

[0149] Perform uncached storage (pointer + i + 7, vector[7])

[0150] Execute full memory barrier()

[0151] 3) Experimental Verification and Conclusions: Without using AVX instructions and non-temporary cache, the measured bandwidth of the related technologies was 210GB / s. With AVX256 and non-temporary cache, the measured bandwidth was 220GB / s. With AVX512 and non-temporary cache, the measured bandwidth was 259GB / s. On the Intel Xeon 6761P platform, the theoretical upper limit of system memory bandwidth is 332GB / s (limited by the MCH bus). Test conclusions: Due to memory controller bus contention, the bandwidth did not reach 100%. When using related technologies (without AVX / non-temporary cache), the measured bandwidth was 210GB / s, with a utilization rate of approximately 63%. After enabling AVX512 and non-temporary cache optimization, the measured bandwidth increased to 259GB / s, with a utilization rate of 78%. Compared with related technologies, this method improved bandwidth utilization by approximately 15 percentage points (78%-63%).

[0152] 2. Based on the ARM platform;

[0153] 1) Test environment: Hardware: NVIDIA Grace CPU (72 cores / 144 threads, 8-channel HBM2e memory, theoretical bandwidth 819.2 GB / s); OS: Ubuntu 22.04 (kernel 5.15); Memory configuration: 512GB HBM2e (4096-bit bus, 6400 MT / s).

[0154] 2) Core Algorithm:

[0155] #pseudocode

[0156] ARM Unbuffered Write Function (Iteration Count, State):

[0157] pointer = state.buffer

[0158] Total bytes = status.bytes

[0159] Vector byte length = Get SVE vector length()

[0160] Value = Create padding vector (0xFFFF0000FFFF0000)

[0161] Loop iteration count:

[0162] Remaining bytes = Total bytes

[0163] Current pointer = pointer

[0164] Loop through the remaining bytes until the vector length is greater than or equal to the remaining bytes.

[0165] Perform non-cached store (current pointer, value).

[0166] Current pointer += vector byte length * (random(1-4)) / / address randomization

[0167] Remaining bytes -= Vector byte length

[0168] if page boundary alignment: execute memory barrier()

[0169] Execute full memory barrier()

[0170] 3) Experimental verification and conclusions:

[0171] Table 4: Comparison of Test Results

[0172]

[0173] Conclusion: Theoretical bandwidth = 8 channels × 6400MT / s × 4096bit ÷ 8 = 819.2GB / s. According to the NVIDIA Grace CPU architecture manual (Document ID: NV-G2000), the actual usable bandwidth of the HBM2e stacking interface is 20% of the theoretical value. Through 256-bit SVE2 non-cached instructions, the single data throughput reaches 32 bytes, which is 4 times higher than that of 64-bit instructions. The address randomization strategy reduces the probability of DRAM row conflicts, and the measured bandwidth fluctuation rate is reduced to 1 / 9 of that of related methods. The measured bandwidth reaches 16.6% of the theoretical value, which is 160% higher than that of related methods, verifying the memory access efficiency bottleneck of HBM2e.

[0174] 3. Implementation based on RISC-V vector extension.

[0175] 1) Test environment: Hardware: SipeedLicheePi4A (SG2042 chip, 4-core RISC-V, DDR4 3200MT / s); OS: TinaLinux (kernel 5.10); Memory configuration: 16GB DDR4 (64-bit channel).

[0176] 2) Core algorithm: Call perf_event_open() to collect L2D_CACHE_REFILL events;

[0177] #pseudocode

[0178] RISC-V Unbuffered Write Function (Iteration Count, State):

[0179] pointer = state.buffer

[0180] Total bytes = status.bytes

[0181] Vector length = Get the maximum vector length of RVV()

[0182] Value = Create padding vector (0xAA)

[0183] Loop iteration count:

[0184] Remaining bytes = Total bytes

[0185] Current pointer = pointer

[0186] Loop through the remaining bytes > 0:

[0187] Current vector length = adaptive setting (number of remaining bytes)

[0188] Perform a strafing store (current pointer, 64, value, current vector length).

[0189] Current pointer += current vector length * 64

[0190] Remaining bytes -= Current vector length * 64

[0191] Execute memory barrier()

[0192] 3) Experimental verification and conclusions

[0193] Table 5: Comparison of Test Results

[0194]

[0195] Conclusion: By using vsoxei64 uncached instructions and step access, the L2 cache is completely bypassed (measured miss rate >99%); dynamic vector length adaptation (32B-128B) solves the matching problem between RISC-V variable-length vectors and fixed memory channels (64B); measured bandwidth reaches 34% of the theoretical value, which is 625% higher than the scalar method, verifying the universality of this application in reduced instruction set architecture.

[0196] The above-mentioned method for measuring peak system memory bandwidth includes: in response to receiving a system memory peak bandwidth measurement request, obtaining the instruction set support flag of the CPU within the system; based on the instruction set support flag, determining the vector instructions for the target data width supported by the CPU; the system memory peak bandwidth measurement request includes the number of iterations; configuring corresponding non-cached access instructions and memory barrier instructions based on the vector instructions for the target data width; obtaining the topology information of the non-uniform memory access architecture; based on the topology information, creating a target test thread and the memory buffer accessed by the target test thread; mapping the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture; in response to the completion of the mapping, accessing the memory buffer in order of target data width by the target test thread based on the non-cached access instructions; in response to the completion of the task execution corresponding to the non-cached access instructions, inserting a memory barrier instruction; repeatedly executing the memory buffer access operation and the memory barrier instruction insertion operation according to the number of iterations; in response to the completion of the iteration operation, obtaining the time consumed by accessing the memory buffer to calculate and determine the system memory peak bandwidth; the beneficial effects of this application include:

[0197] (1) Closer to theoretical peak: By adopting the maximum vector width instruction (such as 512-bit AVX-512) that matches the physical width of the memory channel, the bottleneck of narrow instruction (64 / 128-bit) is overcome, significantly improving the data throughput of a single instruction, and making the generated memory access pressure more fully occupy the memory controller and physical channel.

[0198] (2) Eliminate cache interference: By combining non-temporary (NT) storage instructions with write barriers (SFENCE / DSB), non-cache access is forced and memory is accessed directly. This avoids the artificially high bandwidth caused by cache hits and the bandwidth dilution caused by cache jitter / replacement strategies. The measured results truly reflect the performance of the memory subsystem itself.

[0199] (3) Eliminate cross-node noise: By automatically detecting NUMA topology and strictly binding the test thread and its accessed memory buffer to the same NUMA node, the additional latency and bus congestion introduced by cross-node access under the non-uniform memory access (NUMA) architecture are eliminated, the repeatability and accuracy of test results are improved, and the possible cross-node access risks are clearly marked.

[0200] (4) Improve measurement stability and auditability: High-precision timing reference calibration deducts loop overhead, buffer alignment and pre-allocation avoid page faults, preheating stabilizes DRAM and prefetcher, etc., reduce measurement error sources; combined with the performance monitoring unit (PMU) to verify the effectiveness of non-cached access and output detailed metadata (NUMA node, thread binding, vector width, NT state, cross-node marker, etc.), the test results have better auditability. At the same time, experiments show that on typical platforms, the memory bandwidth value measured by this application is closer to the theoretical peak than that of related tools (such as bw_mem), and the result has lower volatility.

[0201] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0202] It should be understood that, although Figures 2-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 2-3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0203] In one embodiment, an electronic device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown, the electronic device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for measuring the peak bandwidth of system memory. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the device's casing, or an external keyboard, touchpad, or mouse.

[0204] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0205] Embodiments of this application provide an electronic device, including a memory and a processor. The memory stores a computer program, and the processor is configured to run the computer program to perform the steps in the embodiments of the system memory peak bandwidth measurement method, including:

[0206] S1: In response to receiving a system memory peak bandwidth measurement request, obtain the instruction set support flag of the CPU in the system, and determine the vector instructions with the target data width supported by the CPU based on the instruction set support flag. The system memory peak bandwidth measurement request includes the number of iterations.

[0207] S2: Vector instructions based on the target data width, configuring corresponding non-cached access instructions and memory barrier instructions;

[0208] S3: Obtain the topology information of the non-uniform memory access architecture, and based on the topology information, create the target test thread and the memory buffer accessed by the target test thread, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0209] S4: In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0210] S5: Based on the number of iterations, repeatedly execute memory buffer access operations and memory barrier instruction insertion operations. In response to the completion of the iteration operation, obtain the time consumed to access the memory buffer in order to calculate and determine the system's peak memory bandwidth.

[0211] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in the embodiments of the system memory peak bandwidth measurement method at runtime, including:

[0212] S1: In response to receiving a system memory peak bandwidth measurement request, obtain the instruction set support flag of the CPU in the system, and determine the vector instructions with the target data width supported by the CPU based on the instruction set support flag. The system memory peak bandwidth measurement request includes the number of iterations.

[0213] S2: Vector instructions based on the target data width, configuring corresponding non-cached access instructions and memory barrier instructions;

[0214] S3: Obtain the topology information of the non-uniform memory access architecture, and based on the topology information, create the target test thread and the memory buffer accessed by the target test thread, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0215] S4: In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0216] S5: Based on the number of iterations, repeatedly execute memory buffer access operations and memory barrier instruction insertion operations. In response to the completion of the iteration operation, obtain the time consumed to access the memory buffer in order to calculate and determine the system's peak memory bandwidth.

[0217] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0218] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the embodiment of the system memory peak bandwidth measurement method, including:

[0219] S1: In response to receiving a system memory peak bandwidth measurement request, obtain the instruction set support flag of the CPU in the system, and determine the vector instructions with the target data width supported by the CPU based on the instruction set support flag. The system memory peak bandwidth measurement request includes the number of iterations.

[0220] S2: Vector instructions based on the target data width, configuring corresponding non-cached access instructions and memory barrier instructions;

[0221] S3: Obtain the topology information of the non-uniform memory access architecture, and based on the topology information, create the target test thread and the memory buffer accessed by the target test thread, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0222] S4: In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0223] S5: Based on the number of iterations, repeatedly execute memory buffer access operations and memory barrier instruction insertion operations. In response to the completion of the iteration operation, obtain the time consumed to access the memory buffer in order to calculate and determine the system's peak memory bandwidth.

[0224] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps in the embodiments of the system memory peak bandwidth measurement method, including:

[0225] S1: In response to receiving a system memory peak bandwidth measurement request, obtain the instruction set support flag of the CPU in the system, and determine the vector instructions with the target data width supported by the CPU based on the instruction set support flag. The system memory peak bandwidth measurement request includes the number of iterations.

[0226] S2: Vector instructions based on the target data width, configuring corresponding non-cached access instructions and memory barrier instructions;

[0227] S3: Obtain the topology information of the non-uniform memory access architecture, and based on the topology information, create the target test thread and the memory buffer accessed by the target test thread, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture.

[0228] S4: In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task corresponding to the non-cached access instruction, a memory barrier instruction is inserted.

[0229] S5: Based on the number of iterations, repeatedly execute memory buffer access operations and memory barrier instruction insertion operations. In response to the completion of the iteration operation, obtain the time consumed to access the memory buffer in order to calculate and determine the system's peak memory bandwidth.

[0230] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0231] The foregoing has provided a detailed description of a system memory peak bandwidth measurement method, apparatus, electronic device, and storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for measuring peak bandwidth of system memory, characterized in that, The method includes: In response to receiving a system memory peak bandwidth measurement request, the system obtains the instruction set support flag of the central processing unit within the system, and determines the vector instructions with a target data width supported by the central processing unit based on the instruction set support flag. The system memory peak bandwidth measurement request includes the number of iterations. Based on the vector instructions of the target data width, configure the corresponding non-cached access instructions and memory barrier instructions; Obtain the topology information of the non-uniform memory access architecture, create a target test thread and the memory buffer accessed by the target test thread based on the topology information, and map the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture. In response to the completion of the mapping, based on the non-cached access instruction, the target test thread accesses the memory buffer in the order of the target data width. In response to the completion of the task execution corresponding to the non-cached access instruction, the memory barrier instruction is inserted. Based on the number of iterations, the memory buffer access operation and the memory barrier instruction insertion operation are repeatedly executed. In response to the completion of the iteration operation, the time consumed in accessing the memory buffer is obtained to calculate and determine the system memory peak bandwidth.

2. The system memory peak bandwidth measurement method according to claim 1, characterized in that, The instruction set support flags for the CPU within the system include: Obtain the function identification information of the central processing unit; The functional identification information is parsed to determine the support flag bits corresponding to the target vector instruction set; Based on the state of the support flag, determine whether the central processing unit supports the target vector instruction set; In response to the support flag being in a first state, it is determined that the central processing unit supports the target vector instruction set; In response to the support flag being in the second state, it is determined that the central processing unit does not support the target vector instruction set.

3. The method for measuring peak bandwidth of system memory according to claim 2, characterized in that, Based on the instruction set support flags, the vector instructions supporting the target data width supported by the central processing unit include: Priority order for obtaining the pre-set vector instruction data width; Based on the priority order, the instruction set support flags corresponding to the first state are traversed sequentially from high to low. Based on the traversal results, the data width of the first vector instruction marked as supported in the priority order is determined as the target data width; The vector instruction corresponding to the target data width is defined as the vector instruction for the target data width supported by the central processing unit.

4. The method for measuring peak bandwidth of system memory according to claim 1, characterized in that, Based on the vector instructions for the target data width, the corresponding non-cached access instructions and memory barrier instructions are configured as follows: The target data width of the vector instruction for obtaining the target data width, the architecture information of the central processing unit, and the mapping table are used to store the mapping relationship between the data width, the architecture information of the central processing unit, and the instruction. Based on the target data width and the architecture information of the central processing unit, extract the corresponding non-cached access instruction identifier and memory barrier instruction identifier from the mapping table; Configure the corresponding non-cached access instruction and memory barrier instruction based on the non-cached access instruction identifier and the memory barrier instruction identifier.

5. The method for measuring peak bandwidth of system memory according to claim 1, characterized in that, In response to receiving a system memory peak bandwidth measurement request, the method further includes: The system memory peak bandwidth measurement request is parsed to obtain target test parameters, which include at least one of the following: the memory capacity to be tested, the number of parallel threads, the number of warm-up rounds, and the number of formal test rounds.

6. The method for measuring peak bandwidth of system memory according to claim 5, characterized in that, Obtaining the topology information of a non-uniform memory access architecture, and based on the topology information, creating a target test thread and the memory buffer accessed by the target test thread, includes: Obtain the topology information of the system's non-uniform memory access architecture; Based on the topology information, the target non-unified memory access node in the non-unified memory access architecture is determined, and a memory buffer is allocated based on the target non-unified memory access node and the memory capacity to be tested. Based on the stated number of parallel threads, create multiple test threads; Based on the multiple test threads, the target test thread corresponding to the memory buffer is determined.

7. The system memory peak bandwidth measurement method according to claim 6, characterized in that, Mapping the target test thread and the memory buffer to the same non-uniform memory access node in the non-uniform memory access architecture includes: Set the processor affinity of the target test thread to bind to at least one physical processor core within the target non-uniform memory access node; The physical storage location of the memory buffer accessed by the target test thread is allocated in the physical memory of the target non-uniform memory access node.

8. The method for measuring peak bandwidth of system memory according to claim 1, characterized in that, Based on the non-cached access instruction, the target test thread accesses the memory buffer sequentially according to the target data width. In response to the completion of the task corresponding to the non-cached access instruction, the memory barrier insertion instruction includes: Based on the target test thread, the memory buffer is accessed sequentially according to the target data width using the configured non-cached access instructions; In response to the completion of the task corresponding to the current non-cached access instruction, the memory barrier instruction is inserted.

9. The method for measuring peak bandwidth of system memory according to claim 5, characterized in that, Based on the number of iterations, the memory buffer access operation and the memory barrier instruction insertion operation are repeatedly executed. In response to the completion of the iteration operation, the time consumed in accessing the memory buffer is obtained to calculate and determine the system's peak memory bandwidth, including: The number of iterations is determined based on the preheating rounds and the formal testing rounds. Based on the number of iterations, the non-cached access operation of the memory buffer and the insertion operation of the memory barrier instruction are repeatedly executed; In response to the completion of the iteration operation, the total time consumed by accessing the memory buffer when the current iteration is in the formal test round is obtained based on a high-precision timer; Based on the total time and the total amount of data accessed in the memory buffer, the peak system memory bandwidth is calculated and determined.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the system memory peak bandwidth measurement method as described in any one of claims 1 to 9 when executing the computer program.

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