Data processing device, method and equipment

Abstract

The invention discloses a data processing device, method and equipment, and belongs to the field of computers. The device comprises; the instruction decoder is used for decoding a four-word loading instruction, a first memory address and a target register are specified in the four-word loading instruction, and the processing circuit is used for responding to the four-word loading instruction and determining a next register of the target register; and the data loading module is used for reading continuous four-word data from the first memory address and orderly loading the continuous four-word data to the target register and the next register. Therefore, on the premise that the instruction format of the processor architecture is followed, the four-word instruction is loaded, and conflicts with existing instructions of the architecture are avoided. Based on similar principles, the device can store four-word instructions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and particularly relates to a data processing device, method and equipment. BACKGROUND

[0002] In the 64-bit fifth generation reduced instruction set (reduced instruction set computing-V, RISC-V), the load quad word instruction and the store quad word instruction are originally lacked. Therefore, how to implement the functions of the two instructions in the 64-bit RISC-V architecture or similar instruction set architecture is a problem to be solved. SUMMARY

[0003] The present application provides a data processing device, method and equipment, which can implement the functions of the load quad word instruction and the store quad word instruction in the 64-bit RISC-V architecture or similar instruction set architecture. The technical solution is as follows:

[0004] In a first aspect, the present application provides a data processing device, the device comprising:

[0005] an instruction decoder configured to decode a load quad word instruction, the load quad word instruction specifying a first memory address and a target register;

[0006] a processing circuit configured to determine, in response to the load quad word instruction, a next register of the target register, and configured to read data of consecutive quad words starting from the first memory address and to load the data of the quad words in order to the target register and the next register.

[0007] In some possible examples, when decoding the load quad word instruction specifying the first memory address and the target register, the instruction decoder is configured to:

[0008] decode the load quad word instruction to obtain an index of a first base register, a first immediate number and an index of the target register, the index of the target register being used to represent the target register;

[0009] read a base address in the first base register according to the index of the first base register;

[0010] add the base address and the first immediate number to obtain the first memory address.

[0011] In some possible examples, when determining the next register of the target register, the processing circuit is configured to:

[0012] determine a jump condition of the load quad word instruction hit according to the target register;

[0013] According to the hit jump condition, the next register of the target register is determined.

[0014] In some possible examples, in determining the next register of the target register, the processing circuitry is configured to:

[0015] In a case where the target register is determined to be the zero register, the hit jump condition of the load quadword instruction is determined to be a first condition.

[0016] According to the first condition, the zero register is determined to be the next register of the target register.

[0017] In some possible examples, in determining the next register of the target register, the processing circuitry is configured to:

[0018] In a case where the target register is determined to be the last register and the first register is the zero register, the hit jump condition of the load quadword instruction is determined to be a second condition.

[0019] According to the second condition, the zero register is determined to be the next register of the target register.

[0020] In some possible examples, in determining the next register of the target register, the processing circuitry is configured to:

[0021] In a case where the target register is determined to be a non-zero register and a non-last register, the hit jump condition of the load quadword instruction is determined to be a third condition.

[0022] According to the third condition, the next register of the target register is searched.

[0023] In some possible examples, the load quadword instruction has execution authority in a machine state, a supervisor state and a user state.

[0024] In a second aspect, the present application provides a data processing apparatus, the apparatus comprising:

[0025] an instruction decoder configured to decode a store quadword instruction, the store quadword instruction specifying a source data register and a second memory address;

[0026] processing circuitry configured to determine, in response to the store quadword instruction, a next register of the source data register, and configured to read data of a quadword from the source data register and the next register of the source data register, and to store the data of the quadword in a continuous address starting from the second memory address in order.

[0027] In some possible examples, in decoding the store quadword instruction specifying the source data register and the second memory address, the instruction decoder is configured to:

[0028] decode the store quad instruction to obtain an index of a second base register, a second immediate number, and an index of a source data register, the index of the source data register being used to represent the source data register;

[0029] read a base address in the second base register according to the index of the second base register;

[0030] add the base address in the second base register and the second immediate number to obtain a second memory address.

[0031] In some possible examples, in determining the next register of the source data register, the processing circuitry is configured to:

[0032] determine a jump condition of the store quad instruction hit according to the source data register;

[0033] determine the next register of the source data register according to the jump condition of the store quad instruction hit.

[0034] In some possible examples, in determining the next register of the source data register, the processing circuitry is configured to:

[0035] determine that the jump condition of the store quad instruction hit is a fourth condition in a case where the source data register is a zero register;

[0036] determine that the zero register is the next register of the source data register according to the fourth condition.

[0037] In some possible examples, in determining the next register of the source data register, the processing circuitry is configured to:

[0038] determine that the jump condition of the store quad instruction hit is a fifth condition in a case where the source data register is a last register and a first register is a zero register;

[0039] determine that the zero register is the next register of the source data register according to the fifth condition.

[0040] In some possible examples, in determining the next register of the source data register, the processing circuitry is configured to:

[0041] determine that the jump condition of the store quad instruction hit is a sixth condition in a case where the source data register is a non-zero register and a non-last register;

[0042] determine the next register of the source data register according to the sixth condition.

[0043] In some possible examples, the store quad instruction has execution authority in a machine state, a supervisor state, and a user state.

[0044] In a third aspect, the present application provides a data processing method, the method comprising:

[0045] decoding a load quadword instruction, the load quadword instruction specifying a first memory address and a target register;

[0046] in response to the load quadword instruction, determining a next register of the target register;

[0047] reading data of consecutive quadwords from the first memory address, and loading the data of the quadwords to the target register and the next register in order.

[0048] In some possible examples, the decoding the load quadword instruction, the load quadword instruction specifying the first memory address and the target register, comprises:

[0049] decoding the load quadword instruction to obtain an index of a first base register, a first immediate number, and an index of the target register, the index of the target register being used to represent the target register;

[0050] reading a base address in the first base register according to the index of the first base register;

[0051] adding the base address and the first immediate number to obtain the first memory address.

[0052] In some possible examples, the determining the next register of the target register comprises:

[0053] determining a jump condition of the load quadword instruction hit according to the target register;

[0054] determining the next register of the target register according to the jump condition of the load quadword instruction hit.

[0055] In some possible examples, the determining the next register of the target register comprises:

[0056] in a case where the target register is a zero register, determining that the jump condition of the load quadword instruction hit is a first condition;

[0057] determining the zero register as the next register of the target register according to the first condition.

[0058] In some possible examples, the determining the next register of the target register comprises:

[0059] in a case where the target register is a last register and a first register is a zero register, determining that the jump condition of the load quadword instruction hit is a second condition;

[0060] determining the zero register as the next register of the target register according to the second condition.

[0061] In some possible examples, determining the next register of the target register comprises:

[0062] In a case where it is determined that the target register is a non-zero register and a non-last register, determining that a jump condition of the load quadword instruction hit is a third condition;

[0063] According to the third condition, searching for the next register of the target register.

[0064] In a fourth aspect, the present application provides a data processing method, comprising:

[0065] Decoding a store quadword instruction, the store quadword instruction specifying a source data register and a second memory address;

[0066] In response to the store quadword instruction, determining the next register of the source data register;

[0067] Reading quadword data from the source data register and the next register of the source data register, and storing the quadword data in a continuous address starting from the second memory address in order.

[0068] In some possible examples, decoding the store quadword instruction specifying the source data register and the second memory address comprises:

[0069] Decoding the store quadword instruction to obtain an index of a second base register, a second immediate number, and an index of the source data register, the index of the source data register being used to represent the source data register;

[0070] According to the index of the second base register, reading a base address in the second base register;

[0071] Adding the base address in the second base register and the second immediate number to obtain the second memory address.

[0072] In some possible examples, determining the next register of the source data register comprises:

[0073] According to the source data register, determining a jump condition of the store quadword instruction hit;

[0074] According to the jump condition hit, determining the next register of the source data register.

[0075] In some possible examples, determining the next register of the source data register comprises:

[0076] In a case where it is determined that the source data register is a zero register, determining that a jump condition of the store quadword instruction hit is a fourth condition;

[0077] According to the fourth condition, the zero register is determined as the next register of the source data register.

[0078] In some possible examples, the next register of the source data register is determined by:

[0079] In a case where the source data register is determined as the last register and the first register is the zero register, the jump condition of the store quad instruction hit is determined as a fifth condition.

[0080] According to the fifth condition, the zero register is determined as the next register of the source data register.

[0081] In some possible examples, the next register of the source data register is determined by:

[0082] In a case where the source data register is determined as a non-zero register and a non-last register, the jump condition of the store quad instruction hit is determined as a sixth condition.

[0083] According to the sixth condition, the next register of the source data register is searched.

[0084] In some possible examples, the store quad instruction has execution authority in a machine state, a supervisor state and a user state.

[0085] In a fifth aspect, a computer device is provided, which includes a processor and a memory. The memory stores at least one computer program. The at least one computer program is loaded and executed by the processor, so that the computer device implements any of the above data processing methods.

[0086] In a sixth aspect, a computer readable storage medium is further provided. The computer readable storage medium stores at least one computer program. The at least one computer program is loaded and executed by a processor, so that the computer implements any of the above data processing methods.

[0087] In a seventh aspect, a computer program product or a computer program is further provided. The computer program product or the computer program includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium. The processor executes the computer instructions, so that the computer device executes any of the above data processing methods.

[0088] In an eighth aspect, a chip is further provided. The chip includes a processor configured to call and run instructions stored in a memory, so that a computer installed with the chip executes any of the above data processing methods.

[0089] In a ninth aspect, a chip system is further provided. The chip system includes any of the above data processing apparatuses.

[0090] The technical solutions provided by the application bring at least the following beneficial effects:

[0091] In the application, the load quadword instruction and the store quadword instruction conforming to the instruction format under the RISCV architecture or similar architecture are constructed, so that the data of a quadword is loaded from the memory to the register or stored from the register to the memory by responding to the decoding of the load quadword instruction or the store quadword instruction. In this way, a single instruction can access the data of a quadword, which is beneficial to improve the memory bandwidth of the system and reduce the code area of the instruction set. BRIEF DESCRIPTION OF DRAWINGS

[0092] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0093] Figure 1 is a structural schematic diagram of a data processing device provided by an embodiment of the application;

[0094] Figure 2 is a structural schematic diagram of a data processing system provided by an embodiment of the application;

[0095] Figure 3 is a schematic diagram of the data processing device executing the load quadword instruction in one example of the application;

[0096] Figure 4 is a schematic diagram of the data processing device executing the load quadword instruction in another example of the application;

[0097] Figure 5 is a schematic diagram of the data processing device executing the load quadword instruction in another example of the application;

[0098] Figure 6 is a schematic diagram of the data processing device executing the store quadword instruction in one example of the application;

[0099] Figure 7 is a schematic diagram of the data processing device executing the store quadword instruction in another example of the application;

[0100] Figure 8 is a schematic diagram of the data processing device executing the store quadword instruction in another example of the application;

[0101] Figure 9 is a schematic diagram of the data processing device executing the store quadword instruction in another example of the application;

[0102] Figure 10 is a flowchart of a decoding process in a data processing method provided by an embodiment of the present application;

[0103] Figure 11 is a flowchart of a data processing method provided by another embodiment of the present application;

[0104] Figure 12 is a flowchart of a decoding process in a data processing method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0105] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0106] It should be understood that “multiple” mentioned herein refers to two or more. “And / or” describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A existing alone, A and B existing together, and B existing alone. The character “ / ” generally represents that the associated objects before and after it are in an “or” relationship.

[0107] In order to facilitate understanding of the technical solutions of the present application, the technical terms involved in the present application are explained below.

[0108] Instruction set architecture (ISA): It is a general term for a series of contents that define the external behavior of a processor, which serves as the core interface for the interaction between software and hardware in a computer system, and defines the set of executable instructions of the processor, the register organization structure, the memory access mode, and the interrupt processing mechanism, etc. Basic hardware characteristics. It includes two major technical paths of complex instruction set (CISC) and reduced instruction set (RISC).

[0109] RISC-V: It is an open instruction set architecture (ISA) that defines the set of all instructions that a processor can execute, such as including basic instruction sets such as RV32I (32-bit integer instruction set) and RV64I (64-bit integer instruction set). There are also various extension instruction sets. It can implement, but is not limited to, integer register operations, load and immediate number operations, storage operations, branch operations, and jump operations.

[0110] Code size: It refers to the physical space size occupied by the machine code generated by the tool chain in the memory or storage medium.

[0111] Quad word: Also known as quad word, it represents four times the length of a word. Quad word = 2 double word data.

[0112] Load quad word instruction: also known as LQ instruction, used to load a quad word of data from memory into a register.

[0113] Store quad word instruction: also known as SQ instruction, used to store a quad word of data in a general purpose register to a specified memory location.

[0114] Immediate: refers to the numerical data directly contained in the computer instruction, which appears in the instruction of immediate addressing mode, and is used for assignment operation on registers or memory units. Its characteristics are directly embedded in the instruction as the source operand, and cannot be used as the destination operand. For example, 1234H in the instruction "MOV AX, 1234H" is an immediate number, which is used to assign an initial value to the register.

[0115] Operand: refers to the field in the instruction used to specify the operation object. According to the type of instruction, the operand can be a register, a memory address, an immediate number (constant) or other types of data.

[0116] Source register: a register used to temporarily store data or addresses required for instruction execution.

[0117] Opcode: used to indicate the operation type, such as arithmetic operation (such as addition, subtraction, etc.), logic operation (such as and, or, not, etc.), data transfer (such as load, store, move, etc.) and control flow (such as conditional jump, call, etc.).

[0118] The embodiment of the present application provides a data processing device, which can mainly realize the functions of load quad word instruction and store quad word instruction on a 64-bit RISC-V or similar architecture, so as to improve the memory bandwidth and reduce the code area through the execution of the two instructions.

[0119] The data processing device provided by the embodiment of the present application is introduced below.

[0120] Exemplarily, Figure 1 The structure schematic diagram of the data processing device provided by the embodiment of the present application is shown. As Figure 1 shown, the device 100 can include an instruction decoder 110 and a processing circuit 120.

[0121] In some possible implementation manners, with reference to Figure 1The data processing apparatus 100 can be deployed in a processor 10 provided by the embodiments of the present application, and used to execute some instructions to realize data processing. As a possible example but not limitation, in the case that the data processing apparatus 100 is deployed in the processor 10, the instruction decoder 110 can be configured as software, hardware or a combination of software and hardware, and the processing circuit 120 can be configured as hardware or a combination of hardware and software, but is not limited thereto.

[0122] Optionally, the processor 10 can further include a register file 130, which can include a plurality of registers (such as registers X0-X31 as shown in the figure, but is not limited thereto), and the processor 10 can further include a memory 20 or the processor 10 can communicate with the memory 20 through a bus. Figure 1

[0123] Thus, as a possible example, in the data processing apparatus 100, the instruction decoder 110 can be configured to decode a load quad instruction LQ, the load quad instruction LQ specifying a first memory address and a target register (from the register file 130). Wherein, "specifying" can be understood as including or indicating. It can be said that the load quad instruction LQ includes (or indicates) the first memory address and the target register. Then, the processing circuit 120 can be configured to determine a next register of the target register in response to the load quad instruction, and to read data of consecutive quad words from the first memory address, and to load the data of the quad words to the target register and the next register in order.

[0124] Or, as another possible example, the instruction decoder 110 can be configured to decode a store quad instruction SQ, the store quad instruction SQ specifying a source data register and a second memory address. Then, the processing circuit 120 can be configured to determine a next register of the source data register in response to the store quad instruction SQ, and to read data of quad words from the source data register and the next register of the source data register, and to store the data of the quad words to consecutive addresses starting from the second memory address in order.

[0125] Optionally, the first memory address and the second memory address can be storage spaces provided by the memory 20.

[0126] ​It can be understood that the number of bits of a quad word is also different for different architectures of the processor 10. For example, in the 64-bit RISC-V architecture processor 10, the length of the instructions of the basic instruction set (such as RV64I) provided by the RISC-V architecture can be 32 bits, and the bit width of the register is 64 bits (bits), based on which, a word can be 32 bits. Therefore, the device 100 can decode and execute the load quad instruction LQ to access and load 128 bits (quad word) of data from the memory to the corresponding register at a time, or decode and execute the store quad instruction SQ to read 128 bits (quad word) of data from the register and store it to the memory at a time.

[0127] In this way, compared with the single execution of the load instruction (ld) or the store instruction (sd) which can only access 64 bits, the data processing device 100 provided by the embodiment of the application can access quad word data at a time, greatly improving the memory bandwidth and facilitating the reduction of the code area of the instruction set architecture (ISA). For example, if the instruction accesses 64 bits at a time, 2 instructions are required to access 128 bits of data, while the device 100 provided by the embodiment of the application can access 128 bits of data by executing the load quad instruction LQ or the store quad instruction SQ at a time, which reduces the number of instructions and thus reduces the code area of the instruction set architecture (ISA).

[0128] In addition, it should be pointed out that the instruction format in different architecture processors is fixed, and the above-mentioned fields (such as the index of the register and the memory address) included in the load quad instruction LQ and the store quad instruction SQ in the embodiment comply with the fields defined by the corresponding instruction format of the RISC-V architecture, so as not to conflict with the existing instructions in the architecture, and are easy to implement.

[0129] Next, the working principle of the data processing device provided by the embodiment of the application will be described in detail in combination with the drawings.

[0130] Please refer to Figure 2 , Figure 2 is a structural schematic diagram of a data processing system 00 provided by the embodiment of the application. The data processing system 00 includes a processor 10 and a memory 20. As an example, the processor 10 can be implemented as the processor 10 shown in Figure 1 , and the memory 20 can be implemented as the memory 20 shown in Figure 1 .

[0131] The memory 20 may, for example, include one or more forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM), cache memory, and / or the like, which can be used as the memory to provide corresponding memory address spaces for direct data exchange with the processor 10. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, and / or the like, which can be used as the external storage. The external storage can be used to store various application programs, data, such as one or more computer program modules.

[0132] The processor 10 may, for example, be a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), a system on chip (SOC), or other forms of processors with data processing capabilities and / or program execution capabilities. The central processing unit (CPU) may, for example, be a RISC architecture (such as RISC-V) or the like. The processor 10 can be a general-purpose processor or a special-purpose processor. The processor 10 can be implemented as a single processor, a multi-core processor, and / or a cluster of processors arranged for parallel processing (which can include homogeneous and / or heterogeneous processor architectures), which can be deployed in a computing device to implement desired functions through instructions executed by the above-mentioned data processing apparatus 100 to control other components in the computing device.

[0133] The processor 10 may, for example, include an instruction decoder 110 and a processing circuit 120, as shown in the data processing apparatus 100 included in the processor 10. Figure 2 The instruction decoder 110 may, for example, be configured to decode instructions, such as decoding machine code instructions into micro-operations.

[0134] The processing circuit 120 may, for example, include a load store unit (LSU) 121, the functions of which include executing load instructions (including load quadword instructions LQ) and store instructions (including store quadword instructions SQ). The load store unit 121 may, for example, include a three-level cache (i.e., L1-L3), in which Figure 2As shown, the level one (L1) cache can include an instruction cache (I-Cache) 1211 and a data cache (D-cache) 1212. The instruction cache (I-Cache) 1211 can be used to store recently used instructions, and the data cache (D-cache) 1212 can be used to store recently accessed data.

[0135] As an example, the load store unit 121 can further include a condition judgment unit 1210. The condition judgment unit 1210 can be used to perform comparison, arithmetic or logical operation processing, etc. according to the decoding result of the instruction decoder 110 to obtain a condition judgment result. For example, the condition judgment unit can include, but is not limited to, an arithmetic and logic unit (ALU).

[0136] As an example, the load store unit 121 can further include an address generation unit (AGU) 1213 and a translation lookaside buffer (TLB) 1214. The address generation unit 1213 is used to calculate the corresponding memory address according to the condition judgment result and the decoding result output by the instruction decoder 110, and the translation lookaside buffer 1214 is used to perform memory address translation buffering. Moreover, the load store unit 121 can further include a load queue to maintain the order of load instructions, and can further include a store queue to temporarily store the data of store instructions, to ensure the order of the store operation.

[0137] As an example, the processor 10 can further include a register file 130. Optionally, the register file 130 includes at least a plurality of general-purpose integer registers, such as the X0~X31 registers included in the RISC-V architecture processor, also known as register X0~register X31. The first register is numbered X0, and this register X0 is a zero register. The zero register is a register whose value is always 0 and cannot be modified. In addition, as an example, the processor 10 can further include registers for other purposes, such as a base register, but is not limited thereto.

[0138] As an example, the processor 10 can further include an instruction fetch unit (IFU) 140. The instruction fetch unit 140 can be used to read instructions from the instruction cache (I-Cache) 1211, and then deliver them to the instruction decoder 110 for decoding instructions and implementing subsequent instruction execution.

[0139] It can be appreciated that the pipeline of instruction execution can include fetch, decode, execute, memory access (load / store), and write back (for load only instructions), and thus the process of executing the load quadword instruction LQ and the store quadword instruction by the data processing apparatus 100 will be described below in terms of the pipeline.

[0140] Exemplarily, before describing the process of executing the load quadword instruction LQ, the syntax and the instruction format of the load quadword instruction LQ provided by the embodiments of the present application are described.

[0141] In some possible implementation manners, the syntax of the load quadword instruction LQ can be expressed as “ew.lq rd, imm(rs1)”, but is not limited thereto. Wherein, “ew.lq” is an instruction identifier in an assembly language (such as RISC-V assembly language), indicating the load quadword instruction LQ. “rd” indicates a target register. “imm” indicates an immediate number, which can be a 12-bit binary data in the present example. “rs1” indicates a base register, which is a register for storing an operand (such as a base address), and can be represented as a 5-bit register number in the present example.

[0142] Exemplarily, the instruction format of the load quadword instruction LQ can be defined as the format shown in Table 1 below.

[0143] Table 1

[0144]

[0145] As shown in Table 1, in the present example, the load quadword instruction LQ is an I-Type (immediate operation) instruction format, and the instruction length is 32 bits. In the instruction format, the fields distributed in the order from high bit to low bit include: the 31st-20th bit is a 12-bit immediate number (imm); the 19th-15th bit is the number (or index) of the base register rs1; the 14th-12th bit is the operation type, for example, “011” can represent the load operation; the 11th-7th bit is the number (or index) of the target register; and the 6th-0th bit is the basic type (also referred to as the operation code) of the instruction, for example, “0101011” corresponds to the type of the conditional jump instruction.

[0146] Thus, because the instruction format of the load quadword instruction LQ complies with the specification of the RISCV architecture, there is no conflict with the existing instructions or the encoding space of the RISCV architecture in terms of instruction encoding, which is conducive to implementation.

[0147] It should be noted that the instruction format of the load quadword instruction LQ can be different in different architectures. Moreover, the instruction length of the load quadword instruction LQ can be shorter (e.g., compressed to 16 bits) or longer to meet the actual system (software or hardware) requirements or as technology evolves, while maintaining the function of the load quadword instruction LQ.

[0148] Based on the syntax and instruction format of the load quadword instruction LQ described above, the execution process of the load quadword instruction LQ is introduced below according to the pipeline.

[0149] For example, in the fetch stage (Fetch), the fetch unit 140 reads the load quadword instruction LQ from the L1 instruction cache (I-Cache) 1211 and passes the load quadword instruction LQ to the instruction decoder 110.

[0150] Then, the decode stage (Decode) is entered. The instruction decoder 110 parses the operation code (opcode) from the load quadword instruction LQ, identifies it as a load operation, and extracts the index of the target register rd, the index of the base register rs1, and the immediate number imm. Then the instruction decoder 110 generates control signals to read the value of the base register rs1 (i.e., the virtual address) from the register file 130 according to the index of the base register rs1. It can be understood that the operation code (opcode), operation type, index of the target register rd, index of the base register rs1, and immediate number imm parsed by the instruction decoder 110, as well as the value of the base register rs1, together form the decoding result of the load quadword instruction LQ by the instruction decoder 110.

[0151] Then, the execute stage (Execute) is entered. The condition judging unit 1210 of the processing circuit 120 first performs a logical operation according to the decoding result output by the instruction decoder 110 to determine whether the current decoding result hits the jump condition.

[0152] For example, the jump condition of the load quadword instruction LQ can include:

[0153] In the case that the target register rd is a non-zero register and is not the last register, for example, the target register rd can be any of the registers X1 to X30, the data (128 bits in total) of the quadword stored in the consecutive memory addresses is loaded into the target register rd and the next register rd+1 of the target register rd, respectively, the target register rd is used to load the low doubleword data (64 bits) in the data of the quadword, and the register rd+1 is used to load the high doubleword data (64 bits);

[0154] In the case that the target register rd is the zero register, the register rd+1 is also configured to the zero register, that is, the four words of data are all assigned to the zero register; the load quadword instruction LQ is normally executed, and no exception is reported.

[0155] In the case that the target register rd is the last register, and the first register is the zero register, the register rd+1 is the zero register, that is, the low doubleword data in the four words of data is loaded into the last register, and the high doubleword data is loaded into the zero register; the load quadword instruction LQ is normally executed, and no exception is reported.

[0156] It can be understood that, since the zero register is not writable in the register file 130, the data loaded into the zero register is equivalent to invalid or lost, and will not cause modification of the zero register. In the present example, the indication of loading data into the zero register in the jump condition is not determined as an exception.

[0157] In this way, in the implementation of the load quadword instruction LQ based on the register file 130 of the system architecture (such as the RISCV architecture), the special nature of the zero register is taken into account, and the smooth execution of the load quadword instruction LQ is ensured.

[0158] In some possible examples, the operation of the load quadword instruction LQ can be implemented through the following code snippet:

[0159]

[0160] In the code snippet, “rs1+imm” is the address (also referred to as the first memory address herein) obtained by adding the base address indicated by the base register rs1 and the immediate number (imm). “value[rd]=mem[rs1+imm]” indicates that the low doubleword data (64 bits) stored starting from the first memory address “mem[rs1+imm]” is loaded into the target register rd, and “value[rd+1]=mem[rs1+imm+8]” indicates that the high doubleword data (64 bits) in the four words, which is offset by 8 bytes from the first memory address “mem[rs1+imm]”, is loaded into the next register rd+1 of the target register rd. In this way, through the assignment relationship between the memory address and the corresponding register, it is ensured that the four words of data can be sequentially loaded into the corresponding registers.

[0161] Also, if the jump condition of the if instruction (also referred to as a first condition herein) is defined as rd=X0, then rd+1=X0. That is, under the jump condition of the if instruction, the four words of data are loaded into the zero register X0. Since the zero register X0 is not writable, although the load store unit 121 normally executes the instruction under the condition, the zero register X0 and the next number register X1 thereof are not updated, and the original data remains unchanged, which is equivalent to the currently loaded four words of data being discarded.

[0162] Also, if the jump condition of the if instruction (also referred to as a first condition herein) is defined as rd=X0, then rd+1=X0. That is, under the jump condition of the if instruction, the four words of data are loaded into the zero register X0. Since the zero register X0 is not writable, although the load store unit 121 normally executes the instruction under the condition, the zero register X0 and the next number register X1 thereof are not updated, and the original data remains unchanged, which is equivalent to the currently loaded four words of data being discarded.

[0163] It can be understood that, under the jump condition of the if instruction and the jump condition of the else if instruction, the remaining jump conditions of the else instruction (also referred to as a third condition herein) are normally executed, the load quad instruction LQ is executed, the low double word data is loaded into the target register rd, and the high double word data is loaded into the next register rd+1 of the target register, completing the loading of the quad data.

[0164] Then, after the condition judging unit 1210 determines that the current hit is the jump condition of the if instruction, the jump condition of the else if instruction, or the jump condition of the else instruction, the processing circuit 120 continues to execute the subsequent processing according to the hit jump condition. The AGU 1213 calculates a first memory address according to the value of the base register rs1 and the immediate number imm. The first memory address is the sum of the value of the base register rs1 and the immediate number imm. In addition, if the physical conversion fails, a page table traversal or an exception, such as a load page fault, is triggered.

[0165] Then, the TLB 1214 of the processing circuit 120 translates the first memory address, that is, converts the virtual address into a corresponding physical address.

[0166] Next, in the memory access stage, the load store unit 121 sends a read request of the physical address and the corresponding hit jump condition to the data cache (D-Cache) 1212. In this way, after the cache hit, the data of four consecutive words, i.e., 128 bits, is read from the physical address. Subsequently, the load quadword instruction LQ enters the load queue to wait for the data return. After the data return, if the page table state is abnormal, a load page fault is triggered.

[0167] Then, the write back stage is entered. After the data of four words is returned from the data cache (D-Cache) 1212, the corresponding hit jump condition writes the low 64 bits of the data of four words into the target register rd and the high 64 bits into the next register rd+1 of the target register rd, completing the execution of the load quadword instruction LQ.

[0168] That is, if the if instruction jump condition is hit, the data of four words read is written into the zero register X0. For example, as shown in Figure 3 If the target register rd specified in the load quadword instruction LQ is the zero register X0, when the low 64 bits of the data 0x12345678_9ABCDEF0 at the memory address "0x2000" and the high 64 bits of the data 0xFFEEDDCC_BBAA9988 at the memory address "0x2008" offset by 8 bytes are loaded into the target register rd and the register rd+1, it is actually indicated that the two data are loaded into the zero register X0, and finally the registers X0 and X1 remain unchanged, where the zero register X0 remains "0x00000000_00000000" unchanged, which is equivalent to completing the instruction execution without the current write back.

[0169] If the else if instruction jump condition is hit, the data of four words read is written into the register X31 and the zero register X0. As shown in Figure 4 If the target register rd specified in the load quadword instruction LQ is the register X31, when the low 64 bits of the data 0x12345678_9ABCDEF0 at the memory address "0x2000" and the high 64 bits of the data 0xFFEEDDCC_BBAA9988 at the memory address "0x2008" offset by 8 bytes are loaded into the register X31 and the zero register X0, the execution result is that the zero register X0 remains "0x00000000_00000000" unchanged.

[0170] If the else instruction jump condition is hit, the data of four words read is written into the target register rd and the register rd+1. As shown in Figure 5As shown in the middle, still taking the example of loading data starting from the memory address "0x2000", if the target register rd specified in the loading quadword instruction LQ is register X1, the result of executing the loading quadword instruction LQ is that the low 64-bit data 0x12345678_9ABCDEF0 is loaded to register X1, and the high 64-bit data 0xFFEEDDCC_BBAA9988 is loaded to register X2.

[0171] In the embodiment, the loading quadword instruction LQ can be well integrated into the above-mentioned pipeline of the processor, in other words, the loading quadword instruction LQ can be correctly processed in each pipeline stage from instruction fetching to write back, and can be implemented on the RISCV architecture or similar architecture while not causing excessive modification to the architecture, and has high adaptability.

[0172] In addition, the implementation of the loading quadword instruction LQ reuses hardware such as ALU, AGU, etc. under the processor architecture, which reduces the implementation difficulty.

[0173] The process of executing the storage quadword instruction SQ is described below, and before that, a syntax and an instruction format of the storage quadword instruction SQ provided by the embodiment are described.

[0174] For example, the syntax of the storage quadword instruction SQ can be expressed as "ew.sq rs2, imm(rs1)", but is not limited thereto. Wherein, "ew.sq" is an instruction identifier in the assembly language (such as RISC-V assembly language), indicating the storage quadword instruction SQ. "rs2" indicates a source data register of the current data to be stored, which can be represented as a 5-bit register number in the example. "imm" indicates an immediate number, which can be a 12-bit binary data in the example. "rs1" indicates a base register, which is used to store a base address and can be represented as a 5-bit register number in the example.

[0175] For example, the instruction format of the storage quadword instruction SQ can be defined as the format shown in Table 2 below.

[0176] Table 2

[0177] 31-25 24-20 19-15 14-12 11-07 06-00 imm[11:5] rs2 rs1 100 imm[4:0] 0101011

[0178] As shown in Table 2, in the present example, the store quadword instruction SQ is in the S-Type (store instruction) instruction format, and the instruction length is 32 bits. In the instruction format, the fields distributed in the order from high bit to low bit include: bits 31 to 20 are a high 7-bit immediate number (imm); bits 24 to 20 are the number (or index) of the base register rs2; bits 19 to 15 are the base register rs1 (or index); bits 14 to 12 are the operation type, for example, "100" represents a store operation; bits 11 to 7 are a low 5-bit immediate number (imm) concatenated with the aforementioned high 7-bit immediate number (imm) to form 12 bits; bits 6 to 0 are the basic type of the instruction.

[0179] It should be noted that the instruction format of the store quadword instruction SQ can be different in different architectures. Moreover, to meet the actual system (software or hardware) requirements, or as technology evolves, the instruction length of the store quadword instruction SQ can also be shorter (e.g., compressed to 16 bits) or longer.

[0180] Based on the syntax and instruction format of the store quadword instruction SQ described above, the execution process of the store quadword instruction SQ is introduced below according to the pipeline.

[0181] For example, in the instruction fetch and decode stage, the process is similar to that of the load quadword instruction LQ, and the main difference is that the instruction decoder 110 identifies the current store operation and extracts the index of the source data register rs2, the index and value of the base register rs1, and the immediate number offset (imm), etc., and outputs the decoding result.

[0182] Next, the execution stage is entered. The condition judging unit 1210 of the processing circuit 120 first performs logical operation according to the decoding result output by the instruction decoder 110 to determine whether the current decoding result hits the jump condition.

[0183] For example, the jump condition of the store quadword instruction SQ can include:

[0184] In the case where the source data register rs2 is a non-zero register and is not the last register, for example, the source data register rs2 can be any of X1 to X30, then the data (a total of four words) in the source data register rs2 and the next register rs2+1 is stored into the corresponding continuous memory address; wherein the low doubleword data (64 bits) of the source data register rs2 is stored into the low 64 bits in the continuous memory address, and the high doubleword data (64 bits) in the register rs2+1 is stored into the high 64 bits in the continuous memory address;

[0185] In the case that the source data register rs2 is the zero register, the register rs2+1 is also configured to the zero register, that is, the continuous memory address of the quadword size is filled with 0; the store quadword instruction SQ is normally executed, and no exception is reported;

[0186] In the case that the source data register rs2 is the last register, and the first register is the zero register, the store quadword instruction SQ indicates that the register rs2+1 is the zero register, that is, the low doubleword data of the last register is stored in the low 64 bits of the continuous memory address, and the data of the zero register is stored in the high 64 bits of the continuous memory address, that is, the high 64 bits of the continuous memory address are filled with 0. The store quadword instruction SQ is normally executed, and no exception is reported.

[0187] In this way, when the store quadword instruction SQ is implemented based on the register file 130 of the system architecture (such as the RISCV architecture), the special nature of the zero register is taken into account to ensure the smooth execution of the store quadword instruction SQ.

[0188] In some possible examples, the operation of the store quadword instruction SQ can be implemented by the following code snippet:

[0189] “if(rs2=X0)

[0190] mem[rs1+imm]=0

[0191] mem[rs1+imm+8]=0

[0192] else if(rs2=X31)

[0193] mem[rs1+imm]=value[rs2]

[0194] mem[rs1+imm+8]=0

[0195] else

[0196] mem[rs1+imm]=value[rs2]

[0197] mem[rs1+imm+8]=value[rs2+1]”

[0198] Similar to the load quadword instruction LQ, in the if instruction jump condition (also referred to as the fourth condition herein) of the code snippet, it is defined that if the source data register rs2 is the zero register X0, the continuous address of the quadword size starting from the second memory address “mem[rs1+imm]” is filled with 0, that is, the data of the zero register X0 is stored.

[0199] else if instruction jump condition (also referred to herein as the fifth condition) is defined, if the source data register rs2 is the last numbered register X31, the values of the register X31 and the next register rs2+1 (i.e. the zero register X0) are stored in the consecutive addresses starting from the second memory address "mem[rs1+imm]". In this way, the low 64-bit data from the register X31 is stored starting from the second memory address, and the high 64-bit data stored starting from the memory address "mem[rs1+imm+8]" offset by 8 bytes from "mem[rs1+imm]" are all 0.

[0200] Under the if instruction jump condition and the else jump condition outside the else if (also referred to herein as the sixth condition), the data of the source data register rs2 and the next register rs2+1 are normally written into the consecutive addresses starting from the second memory address "mem[rs1+imm]".

[0201] Then, after the condition judging unit 1210 determines that the current hit is one of the above if instruction jump condition, else if instruction jump condition or else jump condition, the processing circuit 120 continues to perform the subsequent address calculation, conversion and memory access processing according to the hit jump condition, and the processing process is also similar to the above load quadword instruction LQ. The main difference is that in the execution stage, the AGU 1213 calculates and converts the second memory address according to the value of the base register rs1 and the immediate number imm, and reads the data to be stored from the source data register rs2 and the register rs2+1 according to the hit jump condition.

[0202] For example, if the current hit is the if instruction jump condition, the source data register rs2 and the register rs2+1 are both the zero register X0, which is equivalent to reading two 64-bit "0x00000000_00000000", for example Figure 6 as shown.

[0203] For example, if the current hit is the else if instruction jump condition, i.e. the source data register rs2 is the register X31 and the register rs2+1 is the zero register X0, 64-bit data is read from these two registers respectively, for example Figure 7 as shown, "0x12345678_9ABCDEF0" is read from the register X31, and "0x00000000_00000000" is read from the zero register X0.

[0204] For example, if the current hit is the else instruction jump condition, 64-bit data is read from the source data register rs2 and the register rs2+1 respectively, for example Figure 8As shown, "0x12345678_9ABCDEF0" is read from register X1, "0x00000000_00000000" is read from zero register X0, and "0xFFEEDDCC_BBAA9988" is read from register X2.

[0205] Next, in the memory access stage, the load store unit 121 stores the translation result (physical address) of the second memory address and the read quadword data into the store queue, waiting for commit. After commit, the data is written into the cache L1 D-Cache 1212 or directly into memory according to the current hit jump condition. It can be understood that the storage into memory will also be different corresponding to the hit jump rule. For example Figure 6 In the example shown in FIG. 12B, corresponding to the if jump condition, two 64-bit "0x00000000_00000000" are stored into (store) memory addresses "0x2000", "0x2008", respectively. Or as shown in FIG. 12C Figure 7 corresponding to the else if jump condition, the doubleword data "0x12345678_9ABCDEF0" of register X31 is stored into (store) memory address "0x2000", and the data "0x00000000_00000000" in zero register X0 is stored into (store) memory address "0x2008". Or as shown in FIG. 12D Figure 8 corresponding to the else jump condition, the data "0x12345678_9ABCDEF0" of register X1 is stored into (store) memory address "0x2000", and the data "0xFFEEDDCC_BBAA9988" in register X2 is stored into (store) memory address "0x2008".

[0206] In addition, the load store unit 121 in this stage will check the write permission. If it is a read-only page, a store page fault exception will be triggered.

[0207] Exemplarily, the store quadword instruction SQ can report the following exceptions: a store page fault, a store access fault, and a store guest page fault. The store page fault is that when the store quadword instruction SQ is executed, the memory address (virtual address) cannot be mapped to a legal physical address, resulting in an instruction execution exception. The store access fault is that when the store quadword instruction SQ is executed, the accessed address is illegal at the physical level (irrelevant to the virtual address). The store guest page fault is that in the support of virtualization extension (such as RISC-V Hypervisor extension), the guest executes the store quadword instruction SQ, and a physical address translation failure exception occurs.

[0208] It should be noted that these exceptions belong to the store instruction exceptions supported by the processor architecture (RISC-V architecture), and the store quadword instruction SQ has the triggering mechanism of these exceptions, which does not introduce new exceptions as much as possible, and can avoid making many changes to the processor architecture when implementing the store quadword instruction SQ.

[0209] Similarly, the load quadword instruction LQ can report the following exceptions: a load page fault, a load access fault, and a load guest page fault. The load page fault is that when the load quadword instruction LQ is executed, the accessed memory address (virtual address) is valid, but the corresponding physical page is not allocated or not resident in memory, resulting in an instruction LQ execution exception. The load access fault is that when the load quadword instruction LQ is executed, the access permission is violated (such as writing a read-only page, unauthorized access to a kernel page), resulting in an instruction LQ execution exception. The load guest page fault is that in a virtualization environment, when the guest executes the load quadword instruction LQ, the accessed memory address (virtual address) is invalid in its page table or has insufficient permissions, resulting in an instruction LQ execution exception.

[0210] It can be understood that the above-mentioned exceptions triggered by the load quadword instruction LQ and the above-mentioned exceptions triggered by the store quadword instruction SQ all belong to the store instruction exceptions supported by the processor architecture (RISC-V architecture), which avoids making many changes to the processor architecture when implementing the load quadword instruction LQ and the store quadword instruction SQ, and is conducive to reducing the implementation difficulty.

[0211] For example, the execution permission of the load quadword instruction LQ and the store quadword instruction SQ can be run in a full execution mode, such as a highest permission machine mode (M mode), a supervisor mode (S mode) corresponding to an operating system kernel, or a user mode (U mode), and the like. In this way, the implementation of the load quadword instruction LQ and the store quadword instruction SQ does not need to be additionally modified at a software layer for a system execution mode, which facilitates reducing the implementation difficulty of the instructions.

[0212] Referring to Figure 9 , Figure 9 is a flowchart of a data processing method provided by an embodiment of the present application. For example, the method can be implemented on any suitable device, apparatus, platform, such as the data processing apparatus 100 or the data processing system 100 shown in Figure 1 or Figure 2 , but is not limited thereto.

[0213] For example, as shown in Figure 9 , the method can include steps S910 to S930.

[0214] S910, decoding the load quadword instruction, the load quadword instruction specifying a first memory address and a target register.

[0215] For example, as shown in Figure 10 , the step S910 can include S911 to S913.

[0216] S911, decoding the load quadword instruction to obtain an index of a first base register, a first immediate number, and an index of the target register, the index of the target register being used to represent the target register;

[0217] S912, reading a base address in the first base register according to the index of the first base register;

[0218] S913, adding the base address and the first immediate number to obtain the first memory address.

[0219] S920, determining a next register of the target register in response to the load quadword instruction.

[0220] In some possible examples, when determining the next register of the target register in S920, it can include: determining a jump condition of the load quadword instruction hit according to the target register; and determining the next register of the target register according to the jump condition hit.

[0221] Exemplarily, in the step S920, when determining the next register of the target register, the following cases (S921-S926) can be included (not marked in the figure). Figure 9

[0222] Case 1

[0223] According to the target register, the jump condition of the hit of the load quadword instruction is determined, including S921, in the case where the target register is determined as the zero register, the jump condition of the hit of the load quadword instruction is determined as the first condition.

[0224] Then, according to the jump condition of the hit, the next register of the target register is determined, including S922, according to the first condition, the zero register is determined as the next register of the target register.

[0225] Case 2

[0226] According to the target register, the jump condition of the hit of the load quadword instruction is determined, including S923, in the case where the target register is determined as the last register, and the first register is determined as the zero register, the jump condition of the hit of the load quadword instruction is determined as the second condition.

[0227] Then, according to the jump condition of the hit, the next register of the target register is determined, including S924, according to the second condition, the zero register is determined as the next register of the target register.

[0228] Case 3

[0229] According to the target register, the jump condition of the hit of the load quadword instruction is determined, including S925, in the case where the target register is determined as the non-zero register and the non-last register, the jump condition of the hit of the load quadword instruction is determined as the third condition.

[0230] Then, according to the jump condition of the hit, the next register of the target register is determined, including S926, according to the third condition, the next register of the target register is searched.

[0231] Exemplarily, after the above S920, the step S930 can be implemented, the data of the continuous quadwords starting from the first memory address is read, and the data of the quadwords is sequentially loaded to the target register and the next register.

[0232] In this way, according to different hit cases, the next register of the target register is determined, and then the sequential loading of the quadword data stored starting from the first memory address to the target register and the next register is continued.

[0233] Please refer to Figure 11 The embodiment of the application further provides another data processing method. As shown in Figure 11 ​As shown, the method can include steps S1110-S1130. Among them:

[0234] S1110, decode the store quadword instruction, the store quadword instruction specifies a source data register and a second memory address.

[0235] Exemplarily, as Figure 12 As shown, the step S1110 can include sub-steps S1111-S1113.

[0236] S1111, decode the store quadword instruction to obtain the index of the second base register, the second immediate number and the index of the source data register, the index of the source data register is used to represent the source data register;

[0237] S1112, read the base address in the second base register according to the index of the second base register;

[0238] S1113, add the base address in the second base register and the second immediate number to obtain the second memory address.

[0239] S1120, determine the next register of the source data register in response to the store quadword instruction.

[0240] In some possible examples, the determination of the next register of the source data register in S1120 can include: determining a jump condition of the store quadword instruction hit according to the source data register; and determining the next register of the source data register according to the jump condition hit.

[0241] Exemplarily, the determination of the next register of the source data register in S1120 can include the following cases (not marked in S1121-S1126). Figure 11

[0242] Case one

[0243] According to the source data register, the determination of the jump condition of the store quadword instruction hit includes S1121, in the case of determining that the source data register is a zero register, determining that the jump condition of the store quadword instruction hit is a fourth condition;

[0244] Then, according to the jump condition hit, the determination of the next register of the source data register includes S1122, according to the fourth condition, determining that the zero register is the next register of the source data register.

[0245] Case two

[0246] ​According to the source data register, a jump condition of the store quad instruction hit is determined, including S1123. In a case where the source data register is the last register and the first register is the zero register, it is determined that the jump condition of the store quad instruction hit is the fifth condition.

[0247] Then, according to the hit jump condition, the next register of the source data register is determined, including S1124. According to the fifth condition, the zero register is determined as the next register of the source data register.

[0248] Case three

[0249] According to the source data register, a jump condition of the store quad instruction hit is determined, including S1125. In a case where the source data register is a non-zero register and a non-last register, it is determined that the jump condition of the store quad instruction hit is the sixth condition.

[0250] Then, according to the hit jump condition, the next register of the source data register is determined, including S1126. According to the sixth condition, the next register of the source data register is searched.

[0251] For example, after S1120, S1130 can be implemented to read the data of the quad from the source data register and the next register of the source data register, and store the data of the quad in the continuous addresses starting from the second memory address in order.

[0252] For example, the load quad instruction and the store quad instruction have execution authority in the machine state, the supervisor state and the user state.

[0253] It should be noted that the functions or beneficial effects of the steps in the above data processing method can also be referred to the above description of the data processing apparatus 100, and will not be repeated here.

[0254] In an exemplary embodiment, a computer device is also provided, which includes a processor and a memory. The memory stores at least one computer program. The at least one computer program is loaded and executed by the one or more processors to enable the computer device to implement any of the above data processing methods.

[0255] In an example embodiment, a computer readable storage medium is also provided, and the computer readable storage medium stores at least one computer program. The at least one computer program is loaded and executed by a processor of a computer device, so that the computer implements any one of the above data processing methods. The computer readable storage medium can be a Read-Only Memory (ROM), a Random Access Memory (RAM), a Compact Disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0256] In an example embodiment, a computer program product or computer program is also provided, and the computer program product or computer program includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes any one of the above data processing methods.

[0257] In an example, a chip is also provided, and the chip includes a processor configured to call and run instructions stored in a memory, so that a computer device installed with the chip executes any one of the above data processing methods.

[0258] In an example, a chip system is also provided, and the chip system includes any one of the above data processing devices.

[0259] The above merely illustrates the example embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, and the like made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data processing apparatus, characterized by, The apparatus comprises: an instruction decoder configured to decode a load quadword instruction, the load quadword instruction specifying a first memory address and a target register; processing circuitry configured to determine, in response to the load quadword instruction, a next register of the target register; and read data of consecutive quadwords from the first memory address and load the data of the quadwords to the target register and the next register in order.

2. The apparatus of claim 1, wherein, The instruction decoder is configured to: decode the load quadword instruction to obtain an index of a first base register, a first immediate number and an index of the target register, the index of the target register being indicative of the target register; read a base address in the first base register according to the index of the first base register; add the base address and the first immediate number to obtain the first memory address.

3. The apparatus of claim 1 or 2, wherein, In the determination of the next register of the target register, the processing circuitry is configured to: determine a jump condition of the load quadword instruction hit according to the target register; determine the next register of the target register according to the jump condition hit.

4. The apparatus of claim 3, wherein, In the determination of the next register of the target register, the processing circuitry is configured to: determine a jump condition of the load quadword instruction hit as a first condition in a case that the target register is a zero register; determine the zero register as the next register of the target register according to the first condition.

5. The apparatus of claim 3, wherein, In the determination of the next register of the target register, the processing circuitry is configured to: determine a jump condition of the load quadword instruction hit as a second condition in a case that the target register is a last register and a first register is a zero register; determine the zero register as the next register of the target register according to the second condition.

6. The apparatus of claim 3, wherein, In the determination of the next register of the target register, the processing circuitry is configured to: determine a jump condition of the load quadword instruction hit as a third condition in a case that the target register is a non-zero register and a non-last register; determine the next register of the target register according to the third condition.

7. The apparatus of claim 1 or 2, wherein, The load quadword instruction has execution authority in a machine state, a supervisor state and a user state.

8. A data processing apparatus, characterized by, The apparatus comprises: an instruction decoder configured to decode a store quadword instruction, the store quadword instruction specifying a source data register and a second memory address; processing circuitry configured to determine, in response to the store quadword instruction, a next register of the source data register; and read data of quadwords from the source data register and the next register of the source data register and store the data of the quadwords to consecutive addresses starting from the second memory address in order.

9. The apparatus of claim 8, wherein, The instruction decoder is configured to: decode the store quadword instruction to obtain an index of a second base register, a second immediate number and an index of the source data register, the index of the source data register being indicative of the source data register; reading a base address in the second base register according to an index of the second base register; adding the base address in the second base register and the second immediate number to obtain the second memory address.

10. The apparatus of claim 8 or 9, wherein, In determining the next register of the source data register, the processing circuitry is configured to: determining a jump condition of the store quadword instruction hit according to the source data register; determining the next register of the source data register according to the jump condition hit.

11. The apparatus of claim 10, wherein, In determining the next register of the source data register, the processing circuitry is configured to: determining a jump condition of the store quadword instruction hit as a fourth condition in a case that the source data register is a zero register; determining the zero register as the next register of the source data register according to the fourth condition.

12. The apparatus of claim 10, wherein, In determining the next register of the source data register, the processing circuitry is configured to: determining a jump condition of the store quadword instruction hit as a fifth condition in a case that the source data register is a last register and a first register is a zero register; determining the zero register as the next register of the source data register according to the fifth condition.

13. The apparatus of claim 10, wherein, In determining the next register of the source data register, the processing circuitry is configured to: determining a jump condition of the store quadword instruction hit as a sixth condition in a case that the source data register is a non-zero register and a non-last register; determining the next register of the source data register according to the sixth condition.

14. The apparatus of any one of claims 8 or 9, wherein, The store quadword instruction has execution authority in a machine state, a supervisor state and a user state.

15. A data processing method, characterized by, The method comprises: decoding a load quadword instruction, the load quadword instruction specifying a first memory address and a target register; determining a next register of the target register in response to the load quadword instruction; reading data of consecutive quadwords starting from the first memory address and loading the data of the quadwords to the target register and the next register in order.

16. A data processing method, characterized by, The method comprises: decoding a store quadword instruction, the store quadword instruction specifying a source data register and a second memory address; determining a next register of the source data register in response to the store quadword instruction; reading data of quadwords from the source data register and the next register of the source data register and storing the data of the quadwords to consecutive addresses starting from the second memory address in order.

17. A computer device, comprising: The computer device comprises a processor and a memory, and the memory stores at least one computer program, the at least one computer program is loaded and executed by the processor, so that the computer device implements the method of claim 15 or 16.

18. A computer-readable storage medium, characterized in that, The computer readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by the processor, so that the computer implements the method of claim 15 or 16.

Images