Data transmission method and apparatus, device, and storage medium

Abstract

The embodiment of the application discloses a data transmission method and device, equipment and a storage medium, the method is applied to a first system on chip, the first system on chip and a second system on chip are connected through a high-speed serial computer expansion bus standard (PCIe bus), and the method comprises the following steps: obtaining target channel corresponding to to-be-transmitted data, wherein the target channel is one of PCIe channels between the first system on chip and the second system on chip, the target channel is configured with corresponding channel resources, the channel resources comprise shared memory resources and direct memory access (DMA) resources; and sending the to-be-transmitted data to the second system on chip through target channel resources of the target channel, wherein the target channel resources are one of the shared memory resources and the DMA resources, the target channel resources are matched with target information corresponding to the to-be-transmitted data, and the target information comprises a service type or a data length. The efficiency of cross-system on chip data transmission based on the PCIe bus can be improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and includes, but is not limited to, a data transmission method, apparatus, device, and storage medium. Background Technology

[0002] In the field of communication technology, the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) bus can be used to connect various components inside a computer, such as processors, network devices, memory, and graphics cards. The PCIe bus features serial transmission, full-duplex transmission, and high bandwidth, enabling interaction and data transmission between components.

[0003] In related technologies, when systems interact via the PCIe bus, data transmission typically relies on Direct Memory Access (DMA) transfer or Base Address Register (BAR) resource mapping. However, these two methods differ in terms of speed and latency, requiring users to weigh the appropriate method based on their specific needs. This increases manual costs and complexity, and results in relatively low data transmission efficiency. Summary of the Invention

[0004] In view of this, the data transmission method, apparatus, device, and storage medium provided in the embodiments of this application can improve the efficiency of cross-on-chip system data transmission based on the PCIe bus. The data transmission method, apparatus, device, and storage medium provided in the embodiments of this application are implemented as follows:

[0005] This application provides a data transmission method, the method being applied to a first system-on-a-chip (SoC), wherein the first SoC and a second SoC are communicatively connected via a high-speed serial computer expansion bus (PCIe) standard bus, the method comprising:

[0006] Obtain the target channel corresponding to the data to be transmitted, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, and the target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources;

[0007] The target channel resource is used to send the data to be transmitted to the second on-chip system. The target channel resource is one of the shared memory resource and the DMA resource. The target channel resource is matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0008] By implementing the above technical solution, in the data transmission method provided in this application embodiment, the target channel is one of the PCIe channels between the first system-on-chip and the second system-on-chip. The target channel is configured with corresponding channel resources. Based on target information such as the service type or data length of the data to be transmitted, the target channel resource matching the target information is selected to send the data to be transmitted to the second system-on-chip. This eliminates the need for the user to select or configure resources, simplifying the operation process and improving the efficiency of cross-system data transmission.

[0009] As an optional implementation, in the first aspect of this application embodiment, the target information includes a service type, the service type includes a control type and a data type, and the step of sending the data to be transmitted to the second system-on-a-chip through the target channel resources of the target channel includes:

[0010] When the service type of the data to be transmitted is the control type, the data to be transmitted is sent to the second on-chip system through the shared memory resources of the target channel;

[0011] When the service type of the data to be transmitted is the data type mentioned above, the data to be transmitted is sent to the second system-on-chip through the DMA resources of the target channel.

[0012] By implementing the above technical solution, data transmission can be achieved through shared memory resources of the target channel when the service type is control-type, and through DMA resources of the target channel when the service type is data-type. This flexible selection of target channel resources based on service type can meet the data transmission needs of different service scenarios, improving data transmission efficiency and adaptability.

[0013] As an optional implementation, in the first aspect of this application embodiment, the target information includes data length, and sending the data to be transmitted to the second on-chip system through the target channel resource of the target channel includes:

[0014] If the length of the data to be transmitted is less than or equal to the target threshold, the data to be transmitted is sent to the second on-chip system through the shared memory resources of the target channel;

[0015] If the length of the data to be transmitted is greater than the target threshold, the data to be transmitted is sent to the second on-chip system through the DMA resources of the target channel.

[0016] By implementing the above technical solution, when the data length is less than or equal to the target threshold, shared memory resources are used for transmission; when the data length is greater than the target threshold, DMA resources are used for transmission. This allows for flexible selection of the transmission method based on the data volume, balancing transmission efficiency and the rational utilization of channel resources.

[0017] As an optional implementation, in a first aspect of this application, the shared memory resource includes a target memory block in shared memory corresponding to the target channel, and the step of sending the data to be transmitted to the second system-on-a-chip through the shared memory resource of the target channel includes:

[0018] The data to be transmitted is sent to the target memory block through the target channel;

[0019] A first doorbell signal is sent to the second system-on-chip so that the second system-on-chip can receive the data to be transmitted in the target memory block.

[0020] By implementing the above technical solution, the data to be transmitted is sent through a specific target memory block in the shared memory corresponding to the target channel, and a first doorbell signal is sent to the second on-chip system to notify the second on-chip system to receive the data, so as to meet the scenario requirements such as the service type of the data to be transmitted being the control type, or the data length being less than or equal to the target threshold.

[0021] As an optional implementation, in a first aspect of this application, the DMA resource includes a DMA memory block, and the step of sending the data to be transmitted to the second on-chip system through the DMA resource of the target channel includes:

[0022] The data to be transmitted is sent to the DMA memory block through the target channel;

[0023] Send transmission information to the target memory block in the shared memory corresponding to the target channel, wherein the transmission information includes a destination address and the data length of the data to be transmitted, and the destination address is the address of the DMA memory block;

[0024] A second doorbell signal is sent to the second system-on-chip so that the second system-on-chip receives the data to be transmitted in the DMA memory block according to the transmission information in the target memory block.

[0025] By implementing the above technical solution, the first system on the chip sends the data to be transmitted to the DMA memory block through the target channel, and then sends the transmission information containing the DMA memory block address and data length to the target memory block in the shared memory. Subsequently, it sends a second doorbell signal to the second system on the chip, notifying the second system on the chip to receive the data to be transmitted in the DMA memory block according to the transmission information. This is suitable for scenarios with large data volumes, such as when the service type of the data to be transmitted is a data type, or when the data length of the data to be transmitted is greater than the target threshold.

[0026] As an optional implementation, in the first aspect of the embodiments of this application, the destination address is sent by the second on-chip system to the target memory block. Before sending the data to be transmitted to the DMA memory block through the target channel, the method includes:

[0027] Obtain the destination address stored in the target memory block.

[0028] By implementing the above technical solution, the target address of the DMA memory block can be pre-sent to the target memory block by the second on-chip system and obtained by the first on-chip system. In this way, the first on-chip system can accurately send the data to be transmitted to the DMA memory block specified by the second on-chip system, ensuring the accuracy and reliability of data transmission and guaranteeing efficient coordination between the sender and receiver.

[0029] As an optional implementation, in the first aspect of the embodiments of this application, the target channel includes a shared channel or a dedicated channel. The shared channel is used to transmit data from multiple processes, and the dedicated channel is used to transmit data from one process. Obtaining the target channel corresponding to the data to be transmitted includes:

[0030] Based on the process priority of the target process corresponding to the data to be transmitted, the target channel is determined to be either the shared channel or the dedicated channel.

[0031] By implementing the above technical solution, the target channel is determined to be either a shared channel or a dedicated channel based on the process priority of the target process corresponding to the data to be transmitted. In this way, high-priority processes can use dedicated channels to ensure efficient data transmission, while low-priority processes can use shared channels to transmit data, improving the utilization of memory resources.

[0032] A second aspect of this application provides a data transmission method applied to a second system-on-a-chip (SoC), wherein the second SoC and a first SoC are communicatively connected via a high-speed serial computer expansion bus (PCIe) standard bus, and the method includes:

[0033] The system receives data to be transmitted sent by the first system-on-a-chip (SoC) through the target channel resources of the target channel. The target channel is one of the PCIe channels between the first SoC and the second SoC. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources. The target channel resources are one of the shared memory resources and the DMA resources. The target channel resources are matched with target information corresponding to the data to be transmitted. The target information includes service type or data length.

[0034] By implementing the above technical solution, the second system-on-chip can receive data to be transmitted from the first system-on-chip, reducing the complexity and resource overhead of establishing connections between systems-on-chip and improving data transmission efficiency.

[0035] A third aspect of this application provides a data transmission apparatus, the apparatus being applied to a first system-on-a-chip (SoC), wherein the first SoC and a second SoC are communicatively connected via a high-speed serial computer expansion bus (PCIe) standard bus, the apparatus comprising:

[0036] The channel acquisition module is used to acquire the target channel corresponding to the data to be transmitted, wherein the target channel is one of the PCIe channels between the first on-chip system and the second on-chip system, and the target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources;

[0037] The data transmission module is used to send the data to be transmitted to the second on-chip system through the target channel resource of the target channel, wherein the target channel resource is one of the shared memory resource and the DMA resource, and the target channel resource is matched with the target information corresponding to the data to be transmitted, the target information including service type or data length.

[0038] A fourth aspect of this application provides a data transmission apparatus, the apparatus being applied to a second system-on-a-chip (SoC), the second SoC being communicatively connected to a first SoC via a high-speed serial computer expansion bus (PCIe) standard bus, the apparatus comprising:

[0039] The data receiving module is used to receive data to be transmitted sent by the first system-on-chip through the target channel resources of the target channel. The target channel is one of the PCIe channels between the first system-on-chip and the second system-on-chip. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources. The target channel resources are one of the shared memory resources and the DMA resources. The target channel resources are matched with target information corresponding to the data to be transmitted. The target information includes service type or data length.

[0040] The fifth aspect of this application provides a computer device including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the program to implement the method described in the first or second aspect of the embodiments of this application.

[0041] The sixth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the first or second aspect of the embodiments of this application. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0043] Figure 1 This is an illustration of an application scenario for the data transmission method provided in an embodiment of this application;

[0044] Figure 2 A schematic diagram of the architecture of a system-on-a-chip provided in an embodiment of this application;

[0045] Figure 3 A schematic flowchart of a data transmission method provided in an embodiment of this application;

[0046] Figure 4 A schematic diagram of a data transmission method using shared memory resources provided in an embodiment of this application;

[0047] Figure 5 A schematic diagram of a data transmission method using DMA resources provided in an embodiment of this application;

[0048] Figure 6 Another flowchart illustrating the data transmission method provided in this application embodiment;

[0049] Figure 7 A schematic diagram illustrating data transmission between a first system-on-a-chip and a second system-on-a-chip.

[0050] Figure 8 This is a schematic diagram illustrating another process for transmitting data via shared memory resources in the data transmission method provided in this application embodiment;

[0051] Figure 9 This is a schematic diagram illustrating another process for transferring data via DMA resources in the data transfer method provided in the embodiments of this application.

[0052] Figure 10 A schematic diagram illustrating the implementation of DMA transfer in the data transfer method provided in this application embodiment;

[0053] Figure 11 A schematic diagram of the structure of a data transmission device provided in an embodiment of this application;

[0054] Figure 12 This is another schematic diagram of the data transmission device provided in the embodiments of this application;

[0055] Figure 13 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0058] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0059] It should be noted that the terms "first, second, third" used in the embodiments of this application are used to distinguish similar or different objects and do not represent a specific order of objects. It can be understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0060] In the field of communication technology, PCIe is a high-speed serial computer expansion bus standard, and the PCIe bus is the bus that uses this standard to enable interaction and data transmission between various computer components. Compared with other types of buses such as Peripheral Component Interconnect (PCI), Accelerated Graphics Port (AGP), and Industry Standard Architecture (ISA), the PCIe bus is favored by users due to its serial transmission, full-duplex transmission, and high bandwidth characteristics.

[0061] In related technologies, when computer components and systems interact via the PCIe bus, data transfer is typically achieved using DMA (Direct Memory Access) or BAR (Base Address Register) resource mapping. DMA allows certain hardware or systems to directly read and write memory independently of the Central Processing Unit (CPU). Data transfer can occur directly between memory and devices without frequent CPU intervention, thus improving data transfer efficiency and reducing CPU load. BAR, on the other hand, defines the device's memory address space through a base address register, ensuring that data is read and written accurately at the specified location. These two methods differ in terms of speed and latency. When handling different business types, the appropriate method must be selected based on actual needs. The lack of a unified standard increases manual costs and complexity, ultimately affecting data transfer efficiency.

[0062] In view of this, embodiments of this application provide a data transmission method, apparatus, device, and storage medium, which can improve the efficiency of data transmission across systems or components based on the PCIe bus.

[0063] The following explains the application scenario of the data transmission method provided in the embodiments of this application, as well as the first on-chip system, the second on-chip system, and the PCIe bus included in the scenario, in order to understand the data transmission method provided in this application.

[0064] Please see Figure 1 , Figure 1 This is an illustration of an application scenario for the data transmission method provided in an embodiment of this application, such as... Figure 1 The application scenario shown includes a first system-on-a-chip 10, a second system-on-a-chip 20, and a PCIe bus 30. The first system-on-a-chip 10 communicates with the second system-on-a-chip 20 through the PCIe bus 30.

[0065] A System-on-Chip (SoC) is an integrated circuit that integrates multiple functional modules onto a single chip. It may include one or more processing cores, such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or a Digital Signal Processor (DSP); storage units, such as Random Access Memory (RAM) or Read-Only Memory (ROM); communication interfaces, such as WiFi, Bluetooth, and Ethernet; and peripheral interfaces, etc., which are not limited here.

[0066] In this embodiment, the first system-on-a-chip (SoC) 10 is communicatively connected to the second SoC 20 via the PCIe bus 30, enabling data communication between the two SoCs. The first SoC 10 can act as either a data sender or receiver, and correspondingly, the second SoC can act as either a data receiver or sender. Thus, the two SoCs can transmit data via the PCIe bus 30, achieving data interaction between the systems and fulfilling functional requirements such as data processing and real-time communication.

[0067] It should be noted that, as Figure 1 The application scenario diagram shown is for illustrative purposes only. In practical applications, the PCIe bus 30 can connect to more on-chip systems, such as a third on-chip system, a fourth on-chip system, etc. Each on-chip system can transmit data with each other through the data communication method provided in this application embodiment to complete real-time communication, data processing, or other tasks, which is not limited here.

[0068] The following describes a possible system architecture of the system-on-a-chip in the embodiments of this application, so as to better understand the data transmission method provided in this application.

[0069] Please see Figure 2 , Figure 2 This is a schematic diagram of an architecture of a system-on-a-chip provided in an embodiment of this application.

[0070] like Figure 2As shown, the user-space layer in this architecture can include multiple applications (APPs) and various SDK toolkits, such as network SDKs and inter-process communication (IPC) SDKs. The kernel driver layer can include multiple clients, each client can correspond to a different SDK or APP in the user-space layer, or can schedule different controller devices through a virtual bus driver. Each controller device can be a device corresponding to a root complex (RC) or an endpoint (EP), for example, controller device 0 and controller device 1 corresponding to RC, and controller device 0 and controller device 1 corresponding to EP, etc., without limitation here.

[0071] Each controller device can connect to the physical communication link layer via a channel. The physical communication link layer interacts with the PCIe adapter driver through the PCIe adapter layer API. The PCIe adapter layer API provides an interface for configuring and managing PCIe devices, enabling upper-layer software to easily access and control the underlying PCIe hardware resources. PCIe adapter drivers include PCIe RC adapter drivers and PCIe EP adapter drivers, while PCIe controller drivers include PCIe RC controller drivers and PCIe EP controller drivers, to drive RC and EP devices, enabling data transmission on the PCIe bus and plug-and-play functionality.

[0072] It should be noted that the RC is the core control hub in PCIe, used to manage the enumeration and configuration of other devices on the PCIe bus, control channel configuration, and send commands. EP refers to the terminal device on the PCIe bus, which can receive and respond to requests from the RC or other devices, and perform data transmission or task processing according to the requests.

[0073] In some possible embodiments, when the first system-on-a-chip (SoC) and the second SoC transmit data via the PCIe bus, the first SoC can be the data sender and the corresponding second SoC can be the data receiver; or, the first SoC can also be the data receiver and the corresponding second SoC can be the data sender, without any limitation.

[0074] For example, in the case where the first system-on-chip (SoC) is the data sender and the second SoC is the data receiver, the first SoC sends the data to be transmitted to the second SoC in two ways: either the RC of the first SoC sends the data to be transmitted to the EP of the second SoC, or the EP of the first SoC sends the data to be transmitted to the RC of the second SoC.

[0075] In the case where the first system-on-a-chip (SoC) is the data receiver and the second SoC is the data sender, the second SoC can send the data to be transmitted to the first SoC in two ways: either the RC of the second SoC sends the data to be transmitted to the EP of the first SoC, or the EP of the second SoC sends the data to be transmitted to the RC of the first SoC. No specific limitation is made here.

[0076] In some possible embodiments, the data transmission method can also be applied to the RC or EP of the target on-chip system to send the data to be transmitted to the EP or RC of the target on-chip system. That is, the data transmission method can flexibly perform data interaction between different components of the on-chip system. Whether the RC sends data to the EP or the EP sends data to the RC, the data transmission task can be completed efficiently, improving the efficiency and reliability of data transmission.

[0077] The data transmission method provided in this application will now be described in conjunction with the accompanying drawings to provide a better understanding of its implementation.

[0078] Please see Figure 3 , Figure 3 This is a schematic flowchart of a data transmission method provided in an embodiment of this application. This data transmission method can be applied to a first on-chip system, such as... Figure 3 As shown, the method may include the following steps:

[0079] S301, obtain the target channel corresponding to the data to be transmitted, wherein the target channel is one of the PCIe channels between the first on-chip system and the second on-chip system, and the target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources.

[0080] In this embodiment, the first system-on-a-chip (SoC) and the second SoC are connected via a PCIe bus. For example, when the first SoC acts as the data sender, the data can be transmitted from the RC (Regulator) of the first SoC to the EP (Engineer) of the second SoC, or vice versa, or in other possible ways, without limitation.

[0081] The target channel is one of the PCIe lanes between the first and second on-chip systems, and it is configured with corresponding channel resources. The channel serves as the logical path for data transfer, defining the specific method and resources for data flow between the two systems. Each channel is associated with specific resources, which may include, but are not limited to, shared memory resources and direct DMA resources, to support efficient data transfer. Shared memory resources allow the two systems to share specific memory regions to exchange data; while DMA resources allow data to be transferred directly between memory and devices without direct CPU involvement, improving data transfer efficiency. In this way, the channel not only ensures efficient data transfer but also provides flexibility to adapt to different types or lengths of data transfer requirements.

[0082] In some possible embodiments, multiple PCIe channels can be configured between the first system-on-a-chip (SoC) and the second SoC. The target channel can be determined based on the target process corresponding to the data to be transmitted. The target process can be the process corresponding to the sender, the process corresponding to the receiver, or the processes corresponding to both the sender and receiver. That is, when the first SoC sends data to the second SoC, the target channel for transmitting the data can be determined from multiple PCIe channels based on the target process corresponding to the data to be transmitted, such as the process generated or processing the data to be transmitted in the first SoC, or the process receiving the data to be transmitted in the second SoC, or based on the above two processes and a preset mapping relationship. The preset mapping relationship includes a mapping relationship between a preset process and a preset channel.

[0083] For example, when process a in the first on-chip system transmits data to process b in the second on-chip system, the target channel can be determined based on parameters such as the source address and / or destination address of the data packet to be transmitted. In this way, according to the communication needs between processes, a suitable PCIe channel can be dynamically selected for data transmission, ensuring priority transmission of data for critical processes and improving the overall response speed and reliability of system data transmission.

[0084] In some possible embodiments, in addition to determining the target channel based on the target process corresponding to the data to be transmitted, the target channel can also be determined based on one or more factors such as the data length, data type, and transmission priority of the data to be transmitted, in order to meet the data transmission needs in different scenarios. By determining the target channel, the reuse and management of channel resources can be realized, avoiding resource waste, while ensuring the stability and reliability of data transmission.

[0085] For example, data of different lengths significantly impact transmission efficiency and resource consumption. For short data packets, channels with lower latency are preferred for faster transmission; while for large-capacity data, channels with higher bandwidth are preferred. Data type is also a crucial factor influencing transmission strategies. For instance, real-time data (such as video and audio streams) demands high real-time performance and bandwidth, typically requiring dedicated high-speed channels for smooth transmission; non-real-time data (such as file transfers and batch data processing) can utilize lower-priority channels to improve overall channel resource utilization. Furthermore, transmission priority can also be a basis for determining the target channel. Critical business data or data with extremely high timeliness requirements are given higher priority to ensure access to transmission channels for this data. By considering one or more of these factors to determine the target channel, we can more flexibly address data transmission needs in different scenarios, improving data transmission performance and reliability.

[0086] In some possible embodiments, shared memory resources allow different processes or systems to share the same memory region, thereby enabling rapid data exchange. Between a first on-chip system and a second on-chip system, the shared memory resource may include a memory block of either the first or second on-chip system. Processes can access the memory block through mapping, suitable for multi-process collaboration scenarios where processes need to frequently exchange data, such as in real-time data processing or distributed computing. Access to shared memory resources is typically managed by the operating system to ensure data consistency and access security.

[0087] In some possible embodiments, DMA resources allow direct data transfer between memory and devices without direct CPU involvement in data movement, making them suitable for large-volume data transfers such as image processing and large-scale data acquisition. DMA transfers can significantly reduce CPU load and improve overall system performance. Between a first on-chip system and a second on-chip system, DMA resources can include DMA memory blocks and be managed by a DMA controller to achieve efficient data transfer.

[0088] In some possible embodiments, an interrupt refers to a mechanism in a computer system that, when a specific event occurs (such as data transmission completion, an error occurring, or an external device requesting service), suspends the currently executing program and instead executes the corresponding interrupt handler. Interrupt resources can include various interrupt functions related to data transmission and channel management. By storing the interrupt handling code in the memory block corresponding to the target channel and setting appropriate interrupt trigger conditions, the system can respond and handle situations promptly upon data transmission completion or when an exception occurs. This approach improves the reliability and real-time performance of data transmission, ensuring effective monitoring and management of data during transmission.

[0089] S302 sends the data to be transmitted to the second on-chip system through the target channel resource of the target channel. The target channel resource is one of the shared memory resource and DMA resource. The target channel resource is matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0090] In this embodiment, the target channel resource is matched with the target information corresponding to the data to be transmitted in order to select the target channel resource and ensure the efficiency and applicability of data transmission.

[0091] In some possible embodiments, the target information includes a service type, which includes control type and data type. Data to be transmitted is sent to the second on-chip system via the target channel resources, including:

[0092] When the service type of the data to be transmitted is control type, the data to be transmitted is sent to the second on-chip system through the shared memory resources of the target channel;

[0093] When the service type of the data to be transmitted is a data type, the data to be transmitted is sent to the second on-chip system through the DMA resources of the target channel.

[0094] It should be noted that the target information includes the service type, which is divided into control type and data type. The service type is categorized based on the purpose and transmission requirements of the data to be transmitted. Control types typically involve coordination, synchronization, or management commands between devices, used to implement system control logic, such as enabling or disabling functions, adjusting parameters, etc. Data types refer to the dataset used to transmit service load information, carrying specific data content, such as data collected by sensors, user input information, etc. Different data types can correspond to different channel resources of the target channel.

[0095] For example, when the service type is control-related, data transmission can be achieved through shared memory resources of the target channel, allowing for rapid exchange of control commands and ensuring the system's real-time responsiveness. When the service type is data-related, data transmission can be achieved through DMA resources of the target channel, reducing CPU intervention and improving the efficiency of large data transmission. Thus, flexibly selecting target channel resources based on the service type can meet the data transmission needs of different business scenarios, improving data transmission efficiency and adaptability.

[0096] In some possible embodiments, the target information includes the data length, and the data to be transmitted is sent to the second on-chip system via the target channel resources of the target channel, including:

[0097] If the length of the data to be transmitted is less than or equal to the target threshold, the data to be transmitted is sent to the second on-chip system through the shared memory resources of the target channel;

[0098] If the length of the data to be transmitted exceeds the target threshold, the data to be transmitted is sent to the second on-chip system through the DMA resources of the target channel.

[0099] It is understandable that data of different lengths have different requirements for transmission resources. When the data length is less than or equal to the target threshold, shared memory resources are used for transmission; while when the data length is greater than the target threshold, DMA resources are used for transmission. This allows for flexible selection of the transmission method based on the data volume, balancing transmission efficiency and rational utilization of channel resources. The target threshold can be determined based on the bandwidth of the target channel and system performance, dynamically adjusted based on historical data transmission statistics, or preset by the user according to their needs; no specific limitations are imposed here.

[0100] In some possible embodiments, the first system on chip sends the data to be transmitted to the second system on chip through the shared memory resources of the target channel. This can be understood as the first system on chip sending the data to be transmitted to a memory block area shared by the first system on chip and the second system on chip so that the second system on chip can receive the data.

[0101] In some possible embodiments, sending the data to be transmitted to the second system-on-a-chip via the DMA resources of the target channel can be understood as the first system-on-a-chip using DMA resources, such as a DMA controller, to transfer the data to be transmitted to a DMA memory block. This DMA memory block is different from the memory block shared by the two systems and can be a memory area dedicated to the second system-on-a-chip so that the second system-on-a-chip can receive data from the DMA memory block.

[0102] The data transmission method provided in this application embodiment uses a target channel, which is one of the PCIe channels between the first system-on-a-chip (SoC) and the second SoC. The target channel is configured with corresponding channel resources. Based on target information such as the service type or data length of the data to be transmitted, a target channel resource matching the target information is selected to send the data to be transmitted to the second SoC. This eliminates the need for user selection or configuration of resources, simplifying the operation process and improving the efficiency of cross-system data transmission. Furthermore, the PCIe bus only needs to provide basic shared memory and DMA resources externally. The physical communication link layer is independent of the underlying controller driver; it only exposes its controller device object and communication channel, allowing it to adapt to different chip platforms and meet diverse service requirements.

[0103] The following section, in conjunction with the accompanying drawings, will describe how the first on-chip system sends the data to be transmitted to the second on-chip system through the shared memory resources of the target channel, in order to better understand the implementation process of this data transmission method.

[0104] Please see Figure 4 , Figure 4 This application provides a schematic flowchart illustrating a data transmission method that uses shared memory resources to transmit data. This data transmission method can be applied to a first on-chip system, such as... Figure 4 As shown, the method may include the following steps:

[0105] S401, Obtain the target channel corresponding to the data to be transmitted.

[0106] It should be noted that the implementation method of step S401 is the same as that described in step S301 above, and will not be repeated here.

[0107] S402 sends the data to be transmitted to the target memory block through the target channel.

[0108] In some possible embodiments, the target communication resource matching the target information corresponding to the data to be transmitted includes a shared memory resource. The shared memory resource includes a target memory block within shared memory corresponding to the target channel.

[0109] It should be noted that shared memory is memory accessible to both the first and second on-chip systems. Its physical address can point to memory within either the first or second on-chip system. For example, shared memory can be the memory of an EP (Extended Processing Unit) in either the first or second on-chip system. For instance, when the two on-chip systems are transmitting data, the shared memory between the EP of the first on-chip system and the RC (Responsible Controller) of the second on-chip system can be located within the EP of the first on-chip system, or vice versa. This allows both the first and second on-chip systems to access the shared memory, enabling data transmission.

[0110] In some possible implementations, shared memory can be partitioned based on factors such as the number of PCIe lanes, the bandwidth requirements of each PCIe lane, or lane priority, to allocate memory blocks corresponding to each lane for use as the data transmission area for that lane. This partitioning method helps improve the organization and efficiency of data transmission, ensuring that each lane has independent memory space for data operations and avoiding data corruption and conflicts.

[0111] It should be noted that the target channel corresponds to a target memory block, which is part of the shared memory. The first on-chip system can send the data to be transmitted to the target memory block through the target channel. In this way, the second on-chip system can also access the target memory block to receive and read the transmitted data, enabling the two systems to transmit data efficiently and in an orderly manner, fully ensuring the stability and reliability of data transmission.

[0112] S403 sends a first doorbell signal to the second system on-chip so that the second system on-chip can receive the data to be transmitted in the target memory block.

[0113] It should be noted that the doorbell signal refers to the signal sent by the first on-chip system to the second on-chip system via the doorbell mechanism in PCIe. A doorbell is a way to notify a device that there are new commands or data to process. By sending a doorbell signal to the receiver, the sender can notify the receiver that there is a new task or event to handle. For example, the first doorbell signal sent by the first on-chip system can instruct the second on-chip system to receive data to be transmitted from the target memory block.

[0114] In the above technical solution, the data to be transmitted is sent through a specific target memory block in the shared memory corresponding to the target channel, and a first doorbell signal is sent to the second on-chip system to notify the second on-chip system to receive the data, so as to meet the scenario requirements such as the service type of the data to be transmitted being the control type, or the data length being less than or equal to the target threshold.

[0115] The following section, in conjunction with the accompanying drawings, describes how the first on-chip system sends data to the second on-chip system via the DMA resources of the target channel in the data transmission method, in order to better understand the implementation process of this data transmission method.

[0116] Please see Figure 5 , Figure 5 This is a schematic diagram of a data transmission method using DMA resources provided in an embodiment of this application. This data transmission method can be applied to a first on-chip system, such as... Figure 5 As shown, the method may include the following steps:

[0117] S501, obtain the target channel corresponding to the data to be transmitted.

[0118] It should be noted that the implementation method of step S501 is the same as that described in step S301 above, and will not be repeated here.

[0119] S502 sends the data to be transferred to the DMA memory block through the target channel.

[0120] In some possible embodiments, the target communication resource that matches the target information corresponding to the data to be transmitted includes DMA resources. DMA resources include DMA memory blocks.

[0121] It should be noted that DMA memory blocks can be memory blocks within the data receiver. For example, when the first on-chip system is transmitting data to the second on-chip system, the DMA memory block can be a memory block of the second on-chip system, used to receive the data to be transmitted from the first on-chip system. DMA memory blocks can also be memory blocks outside of the first and second on-chip systems, such as other memory devices connected via the PCIe bus, enabling DMA transfers to adapt to different system architectures and application scenarios, improving the flexibility and efficiency of data transmission.

[0122] In some possible embodiments, the DMA resource may further include a DMA controller, which is a hardware component for managing direct memory access operations. It controls the direct transfer of data between memory and peripherals without direct CPU involvement. The DMA controller plays a crucial role in data transfer, responsible for initializing, executing, and terminating data transfer operations, while monitoring the transfer process to ensure data integrity and accuracy. In this way, the DMA controller significantly improves data transfer efficiency, reduces the CPU load, and thus enhances data transfer efficiency.

[0123] In some possible embodiments, sending data to be transferred to the DMA memory block through the target channel can be understood as the first on-chip system using DMA resources such as the DMA memory block and DMA controller corresponding to the target channel to send the data to be processed to the DMA memory block for storage through DMA transfer.

[0124] S503 sends transmission information to the target memory block in shared memory corresponding to the target channel. The transmission information includes the destination address and the data length of the data to be transmitted. The destination address is the address of the DMA memory block.

[0125] In some possible embodiments, after the first system on-chip sends the data to be transmitted to the DMA memory block through the target channel, it also needs to send transmission information to the target memory block in the shared memory corresponding to the target channel. This transmission information includes the destination address of the DMA memory block and the data length of the data to be transmitted, so that the second system on-chip can locate the data position in the DMA memory block according to the transmission information and realize the receiving process of the data to be transmitted based on the data length.

[0126] In some possible embodiments, where the destination address is sent from the second on-chip system to the target memory block, the data transmission method includes the following before sending the data to be transmitted to the DMA memory block through the target channel:

[0127] Obtain the destination address stored in the target memory block.

[0128] It should be noted that the DMA memory block can be determined by the second on-chip system according to preset rules or requirements, and the second on-chip system sends the destination address of the DMA memory block to the target memory block. In this way, the first on-chip system can obtain the target address of the DMA memory block through the target memory block in the shared memory and send the data to be transferred to the DMA memory block.

[0129] For example, the DMA memory block can be a memory block on the second on-chip system that is used by default to receive data. Before the first on-chip system and the second on-chip system transmit data, the second on-chip system can store the target address in the target memory block of the shared memory to ensure the accuracy of data transmission.

[0130] S504 sends a second doorbell signal to the second system on the chip, so that the second system on the chip can receive the data to be transferred in the DMA memory block according to the transfer information in the target memory block.

[0131] In some possible embodiments, the first system on-chip sends a second doorbell signal to the second system on-chip, so that the second system on-chip can obtain transmission information from the target memory block through the second doorbell signal, and receive the data to be transmitted from the DMA memory block based on the transmission information.

[0132] In the above technical solution, the data to be transmitted is sent through the DMA memory block corresponding to the target channel, and a second doorbell signal is sent to the second on-chip system to notify the second on-chip system to receive the data to be transmitted in the DMA memory block according to the transmission information. This is suitable for scenarios with large data volumes, such as when the service type of the data to be transmitted is a data type, or when the data length of the data to be transmitted is greater than the target threshold.

[0133] Please see Figure 6 , Figure 6This is another schematic flowchart illustrating the data transmission method provided in this application embodiment. This data transmission method can be applied to a second system-on-a-chip, such as... Figure 6 As shown, the method may include the following steps:

[0134] S601 receives the data to be transmitted sent by the first on-chip system through the target channel resource of the target channel.

[0135] In this embodiment, the second system-on-a-chip (SoC) and the first SoC are connected via a high-speed serial computer expansion bus standard PCIe bus. The target channel is one of the PCIe channels between the first SoC and the second SoC. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources. The target channel resource is one of the shared memory resources and DMA resources. The target channel resource is matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0136] It should be noted that the data transmission method can be applied to both receiving and transmitting. The second on-chip system can receive the data to be transmitted from the first on-chip system, which reduces the complexity and resource overhead of establishing connections between on-chip systems and improves data transmission efficiency.

[0137] In some possible embodiments, receiving the data to be transmitted sent by the first on-chip system through the target channel resource of the target channel includes:

[0138] The system receives a first doorbell signal sent by the first on-chip system, wherein the first doorbell signal is used to instruct the second on-chip system to receive the data to be transmitted in the target memory block;

[0139] Based on the first doorbell signal, receive the data to be transmitted from the target memory block.

[0140] It should be noted that if the second on-chip system receives the first doorbell signal, the second on-chip system can receive the data to be transmitted in the target memory block, which will not be elaborated here.

[0141] In some possible embodiments, receiving the data to be transmitted sent by the first on-chip system through the target channel resource of the target channel includes:

[0142] The system receives a second doorbell signal sent by the first on-chip system, wherein the second doorbell signal is used to instruct the second on-chip system to receive the data to be transferred in the DMA memory block according to the transfer information in the target memory block;

[0143] Obtain the transfer information in the target memory block, where the transfer information includes the destination address and the data length of the data to be transferred, and the destination address is the address of the DMA memory block;

[0144] Based on the destination address and the length of the data to be transmitted, receive the data to be transmitted from the DMA memory block.

[0145] It should be noted that if the second on-chip system receives the second doorbell signal, the second on-chip system can receive the data to be transferred in the DMA memory block according to the transfer information in the target memory block, which will not be elaborated here.

[0146] In some possible embodiments, the data transmission method applied to the second on-chip system before receiving the second doorbell signal sent by the first on-chip system further includes:

[0147] Send the destination address to the target memory block, where the destination address is the address of the DMA memory block and the target memory block is the memory block in shared memory corresponding to the target channel.

[0148] It should be noted that by sending the destination address to the target memory block, the second system-on-a-chip enables the first system-on-a-chip to obtain the memory location where the data should be transmitted, thereby achieving efficient and accurate data transmission.

[0149] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating data transmission between a first system-on-a-chip (SoC) and a second SoC. In one possible embodiment, the sender can be a root complex RC (such as the RC in the first SoC), and the receiver can be an endpoint EP (such as the EP in the second SoC). The sender can send the data to be transmitted via shared memory resources or DMA resources.

[0150] When the sender uses DMA resources to transfer data, the receiver can send the target address of the DMA memory block through a channel, and the sender can then send the data to be transferred to the DMA memory block. For example, the receiver's EP sends the destination address of the DMA memory block to the target memory block in shared memory through the corresponding channel, ensuring that the RC of the first on-chip system can obtain the target location for data transmission. The sender's RC uses the corresponding channel and DMA resources to send the data to be transferred to the DMA memory block, ensuring that data is directly transferred from the sender's memory to the receiver's DMA memory block, improving transmission efficiency. After sending data to the DMA memory block, the sender can send transmission information, such as data length and destination address, to the target memory block in shared memory so that the receiver can accurately receive and process the data.

[0151] The sending of the destination address to the target memory block in the receiving direction and the sending of the transmission information to the target memory block in the sending direction can be implemented through different channels or different queues of the same channel, such as a sending queue or a receiving queue, which is not limited here.

[0152] In the above technical solution, the second system-on-chip can receive data to be transmitted from the first system-on-chip, which reduces the complexity and resource overhead of establishing connections between systems-on-chip and improves data transmission efficiency.

[0153] Please see Figure 8 , Figure 8 This is another schematic diagram illustrating the data transmission method provided in this application embodiment, which transmits data via shared memory resources. This data transmission method can be applied to a first on-chip system, such as... Figure 8 As shown, the method may include the following steps:

[0154] S801, obtain the target channel corresponding to the data to be transmitted.

[0155] In some possible embodiments, before obtaining the target channel corresponding to the data to be transmitted, the data transmission method applied to the first on-chip system further includes:

[0156] The first on-chip system is registered as a sender to the PCIe bus.

[0157] It should be noted that registering the first on-chip system as a sender to the PCIe bus can be understood as the first on-chip system sending a registration request to the PCIe bus controller through its RC or EP, instructing the first on-chip system to participate in the subsequent data transmission process as a data sender. The registration process involves a series of configuration operations, which may include, but are not limited to, allocating system resources (such as memory address space, interrupt request lines, etc.) and setting communication parameters to ensure that the first on-chip system can establish a valid communication link with the second on-chip system on the PCIe bus. These details will not be elaborated here. After registration is completed, the first on-chip system has the permission and ability to send data through the PCIe bus and can begin data transmission-related operations.

[0158] In some possible embodiments, the target channel includes a shared channel or a dedicated channel. A shared channel is used to transmit data from multiple processes, while a dedicated channel is used to transmit data from a single process. Obtaining the target channel corresponding to the data to be transmitted includes:

[0159] The target channel is determined to be either a shared channel or a dedicated channel based on the process priority of the target process corresponding to the data to be transmitted.

[0160] It's important to note that shared channels allow multiple processes to share the same channel for data transmission, which helps improve channel utilization and reduce system resource waste. Shared channels are suitable for processes with less stringent real-time requirements or smaller data volumes. Through shared channels, multiple processes can reuse the same channel resources, thereby reducing overall system resource consumption. Dedicated channels, on the other hand, are reserved for a single process, ensuring that its data transmission is not interfered with by other processes. They are suitable for processes with high real-time requirements or large data volumes. Dedicated channels provide more stable and predictable transmission performance, ensuring that critical processes can transmit data in a timely and accurate manner.

[0161] In some possible embodiments, the process priorities of each process can be preset by the system based on factors such as process type, data transmission requirements, and real-time requirements. For example, real-time data processing processes may be given higher priorities to ensure that data can be transmitted and processed quickly; while non-real-time batch data processing processes may have lower priorities to share channel resources. In addition, users can also manually adjust process priorities according to actual needs, which is not limited here.

[0162] In some possible embodiments, the data transmission method applied to the first on-chip system further includes:

[0163] Callbacks related to registering the target channel.

[0164] It should be noted that the relevant callbacks may include, but are not limited to, data transmission completion callbacks, error handling callbacks, and data arrival callbacks. By registering these callback functions, the system-on-a-chip can automatically execute the corresponding processing logic when data transmission is completed, errors occur, or other critical events occur. For example, when data transmission is successfully completed, the data transmission completion callback can notify the application that the data has been successfully sent or received; if an error occurs during transmission, the error handling callback can promptly capture and handle the error, ensuring the stability of data transmission.

[0165] S802, Is the send queue of the destination channel not empty?

[0166] In some possible implementations, data transmission through the target channel can be achieved using the virtio mechanism (protocol). virtio provides a virtual queue management mechanism that allows the first-chip system to efficiently monitor and manage the status of the transmit queue (Virtqueue Ring). Through virtio's virtual queue, the first-chip system can monitor the number of data packets or the space occupied in the transmit queue in real time. When there is data to be transmitted in the transmit queue, the virtual queue will be in a non-empty state, triggering the corresponding data transmission operation. This mechanism ensures that the data to be transmitted can be sent out through the PCIe bus in a timely manner, while avoiding unnecessary resource consumption and latency.

[0167] In some possible embodiments, S803 is implemented when the destination channel's transmission queue is not empty; while when the destination channel's transmission queue is not empty, the first on-chip system can continuously monitor the status of the transmission queue until the queue is not empty. For example, the system can detect changes in the queue status through polling or event notification mechanisms. Once a data packet is detected added to the transmission queue, the queue becomes non-empty, and the system triggers corresponding operations, such as data transmission or status updates. This mechanism ensures timely data transmission and efficient system operation while avoiding resource waste.

[0168] S803 sends the data to be transmitted to the target memory block through the target channel.

[0169] In some possible embodiments, sending the data to be transmitted to the target memory block via the target channel includes:

[0170] Obtain the first resource descriptor, wherein the first resource descriptor includes the address of the target memory block;

[0171] Copy the data to be transferred to the contiguous memory space corresponding to the target memory block indicated by the first resource descriptor;

[0172] Submit the first resource descriptor to the used descriptor queue corresponding to the target channel.

[0173] It should be noted that, through resource descriptors and queuing mechanisms, the system can process multiple data transmission requests in an orderly manner, ensuring the accuracy and timeliness of data transmission. At the same time, it also helps optimize the use of system resources and reduce latency and errors during data transmission.

[0174] S804 sends a first doorbell signal to the second system on-chip so that the second system on-chip can receive the data to be transmitted in the target memory block.

[0175] It should be noted that after receiving the first doorbell signal, the system on the second chip can retrieve the data to be transmitted from the target memory block and return the queue resources to the receiving queue, that is, release the channel resources corresponding to the first resource descriptor so that subsequent data transmission tasks can reuse these resources. This ensures the effective recycling of resources and improves the overall efficiency of data transmission.

[0176] S805, is there any new data to be transmitted?

[0177] In some possible embodiments, if there is new data to be transmitted in the first on-chip system, S802 is implemented to continue data transmission with the second on-chip system; otherwise, the data transmission process is terminated.

[0178] In the above technical solution, the virtio mechanism can be used to realize the data transmission of shared memory resources between on-chip systems through the target channel.

[0179] Please see Figure 9 , Figure 9 This is another schematic diagram illustrating the data transfer method via DMA resources provided in the embodiments of this application. This data transfer method can be applied to a first on-chip system, such as... Figure 9 As shown, the method may include the following steps:

[0180] S901, obtain the target channel corresponding to the data to be transmitted.

[0181] S902, Is the send queue of the destination channel not empty?

[0182] In some possible embodiments, S903 is implemented when the transmit queue of the destination channel is not empty; while when the transmit queue of the destination channel is not empty, the first on-chip system can continuously monitor the status of the transmit queue until the queue is not empty.

[0183] S903 sends the data to be transferred to the DMA memory block through the target channel.

[0184] In some possible embodiments, sending the data to be transferred to the DMA memory block via the target channel includes:

[0185] Obtain the second resource descriptor, wherein the second resource descriptor includes the address of the target memory block, and the target memory block is the memory block in shared memory corresponding to the target channel;

[0186] Based on the second resource descriptor, obtain the destination address where the target memory block is stored, where the destination address is the address of the DMA memory block;

[0187] Send the data to be transmitted to the DMA memory block.

[0188] Please see Figure 10 , Figure 10 This is a schematic diagram illustrating DMA transfer in the data transfer method provided in this application embodiment. For example... Figure 8 As shown, in some possible embodiments, the virtqueue component of the virtio mechanism can be used to send data to be transferred to the DMA memory block through the target channel.

[0189] It should be noted that the virtqueue component is a component of the virtio mechanism (protocol). It is a channel for data exchange between the front-end driver and the back-end virtual device, allowing efficient transmission of batch data in a virtual environment without simulating traditional physical device interfaces.

[0190] In some possible embodiments, the target channel may include a sender queue and a receiver queue, and data to be transmitted can be sent to the DMA memory block through the virtqueue component and the target channel resources of the target channel. For example, firstly, the receiving party (such as the second system-on-a-chip) can pre-fill the second resource descriptor corresponding to the DMA memory block into the descriptor table; secondly, the first system-on-a-chip obtains the previous index in the used ring through the target channel and the corresponding mapping relationship, and obtains the second resource descriptor in the descriptor table, thereby obtaining the target address of the DMA memory block; then, the sending party, i.e., the first system-on-a-chip, can send the data to be transferred to the DMA memory block through the DMA resources (which may include the DMA memory block and the DMA controller, etc.) of the target channel, write the index of the second resource descriptor after DMA transfer to the available ring, and send a second doorbell signal to the second system-on-a-chip to notify the second system-on-a-chip to receive the data; furthermore, after receiving the second doorbell signal, the second system-on-a-chip can obtain the address and data length of the DMA memory block according to the second resource descriptor after DMA transfer obtained through the available ring, thereby receiving the data to be transferred; finally, the second system-on-a-chip can write the index of the second resource descriptor back to the used ring to return the free resources, realizing the DMA transfer of the data to be transferred.

[0191] S904: Check if the data to be transferred to the DMA memory block was successfully sent.

[0192] In some possible embodiments, it can be detected whether the first on-chip system successfully sends the data to be transferred to the DMA memory block through the DMA resources of the target channel. If the data to be transferred is successfully sent to the DMA memory block, S905 is implemented; if the data to be transferred fails to be sent to the DMA memory block, there may be insufficient space in the DMA memory block or other faults, and the data transfer process can be terminated. For example, after detecting that the first on-chip system has failed to send the data to be transferred to the DMA memory block, actions such as reclaiming the memory block, reallocating resources, or performing other necessary maintenance operations can be taken, without limitation.

[0193] S905 sends transmission information to the target memory block in shared memory corresponding to the target channel.

[0194] S906 sends a second doorbell signal to the second system on the chip, so that the second system on the chip can receive the data to be transferred in the DMA memory block according to the transfer information in the target memory.

[0195] S907, is there any new data to be transmitted?

[0196] In some possible embodiments, if there is new data to be transmitted in the first on-chip system, S902 is implemented to continue data transmission with the second on-chip system; otherwise, the data transmission process is terminated.

[0197] It should be noted that, in addition to using the virtqueue component to implement data transmission between on-chip systems, QP queues or other circular buffer queues can also be used to implement data transmission based on the target channel to meet the data transmission needs in different scenarios. No limitation is made here.

[0198] In the above technical solution, the virtio mechanism can be used to realize the data transfer between on-chip systems through the DMA resources of the target channel.

[0199] It should be understood that although the steps in the above flowcharts are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the above flowcharts may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0200] Based on the foregoing embodiments, this application provides a data transmission device, which includes the included modules and the units included in each module, which can be implemented by a processor; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), microprocessor (MPU), digital signal processor (DSP) or field programmable gate array (FPGA), etc.

[0201] Please refer to Figure 11 , Figure 11 A schematic diagram of a data transmission device provided in an embodiment of this application is shown below. Figure 11 As shown, the data transmission device is applied to the first system-on-a-chip (SoC), which is connected to the second SoC via a high-speed serial computer expansion bus standard PCIe bus. It includes a channel acquisition module 1101 and a data transmission module 1102, wherein:

[0202] The channel acquisition module 1101 is used to acquire the target channel corresponding to the data to be transmitted. The target channel is one of the PCIe channels between the first on-chip system and the second on-chip system. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources.

[0203] The data transmission module 1102 is used to send data to be transmitted to the second on-chip system through the target channel resource of the target channel. The target channel resource is one of the shared memory resource and DMA resource. The target channel resource is matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0204] In some possible embodiments, the target information includes a service type, which includes a control type and a data type. The data sending module 1102 is further configured to send the data to be transmitted to the second system on the chip via the shared memory resources of the target channel when the service type of the data to be transmitted is a control type; and to send the data to be transmitted to the second system on the chip via the DMA resources of the target channel when the service type of the data to be transmitted is a data type.

[0205] In some possible embodiments, the target information includes the data length. The data sending module 1102 is also used to send the data to be transmitted to the second system on the chip through the shared memory resources of the target channel when the data length of the data to be transmitted is less than or equal to the target threshold; and to send the data to be transmitted to the second system on the chip through the DMA resources of the target channel when the data length of the data to be transmitted is greater than the target threshold.

[0206] In some possible embodiments, the shared memory resource includes a target memory block in the shared memory corresponding to the target channel. The data transmission module 1102 is also used to send data to be transmitted to the target memory block through the target channel; and to send a first doorbell signal to the second system on the chip so that the second system on the chip can receive the data to be transmitted in the target memory block.

[0207] In some possible embodiments, the DMA resource includes a DMA memory block. The data transmission module 1102 is further configured to send data to be transmitted to the DMA memory block via a target channel; send transmission information to the target memory block in shared memory corresponding to the target channel, wherein the transmission information includes a destination address and the data length of the data to be transmitted, and the destination address is the address of the DMA memory block; and send a second doorbell signal to the second system on-chip so that the second system on-chip receives the data to be transmitted in the DMA memory block according to the transmission information in the target memory block.

[0208] In some possible embodiments, where the destination address is sent to the target memory block by the second on-chip system, the data sending module 1102 is further configured to: obtain the destination address stored in the target memory block.

[0209] In some possible embodiments, the target channel includes a shared channel or a dedicated channel. The shared channel is used to transmit data from multiple processes, and the dedicated channel is used to transmit data from one process. The channel acquisition module 1101 is also used to determine whether the target channel is a shared channel or a dedicated channel based on the process priority of the target process corresponding to the data to be transmitted.

[0210] Please refer to Figure 12 , Figure 12 Another schematic diagram of the data transmission device provided in the embodiments of this application is shown below. Figure 12 As shown, the data transmission device is applied to the second system-on-a-chip (SoC), which is connected to the first SoC via a high-speed serial computer expansion bus standard PCIe bus. It includes a data receiving module 1201, wherein:

[0211] The data receiving module 1201 is used to receive the data to be transmitted sent by the first system on-chip through the target channel resources of the target channel. The target channel is one of the PCIe channels between the first system on-chip and the second system on-chip. The target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources. The target channel resources are one of the shared memory resources and DMA resources. The target channel resources are matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length.

[0212] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0213] It should be noted that, in the embodiments of this application... Figure 11 or Figure 12 The module division shown in the data transmission device is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or be integrated into one unit with two or more units. The integrated units can be implemented in hardware, as software functional units, or a combination of both.

[0214] It should be noted that, in the embodiments of this application, if the above-described methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0215] This application provides a computer device, which may be a server, and its internal structure diagram may be as follows: Figure 13 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data. The network interface communicates with external terminals via a network connection. When the computer program is executed by the processor, it implements the methods described above.

[0216] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the method provided in the above embodiments.

[0217] This application provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the steps in the method provided in the above-described method embodiments.

[0218] Those skilled in the art will understand that Figure 13 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0219] In one embodiment, the data transmission apparatus provided in this application can be implemented as a computer program, and the computer program can be implemented as follows: Figure 13 The device operates on the computer device shown. The computer device's memory can store the various program modules that make up the above-described apparatus. The computer program, composed of the various program modules, causes the processor to execute the steps of the methods in the various embodiments of this application described in this specification.

[0220] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium, storage medium, and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0221] It should be understood that the phrases "one embodiment," "an embodiment," or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment," "in one embodiment," or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely for descriptive purposes and do not represent the superiority or inferiority of the embodiments. The descriptions of the various embodiments above tend to emphasize the differences between the various embodiments; their similarities or commonalities can be referred to mutually, and for the sake of brevity, they will not be repeated here.

[0222] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three kinds of relationships. For example, object A and / or object B can represent three situations: object A exists alone, object A and object B exist simultaneously, and object B exists alone.

[0223] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0224] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or modules can be electrical, mechanical, or other forms.

[0225] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules. They may be located in one place or distributed across multiple network units. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0226] In addition, each functional module in the various embodiments of this application can be integrated into one processing unit, or each module can be a separate unit, or two or more modules can be integrated into one unit; the integrated modules can be implemented in hardware or in the form of hardware plus software functional units.

[0227] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0228] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0229] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0230] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0231] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0232] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission method, characterized in that, The method is applied to a first system-on-a-chip, wherein the first system-on-a-chip and a second system-on-a-chip are connected via a high-speed serial computer expansion bus standard PCIe bus. The method includes: Obtain the target channel corresponding to the data to be transmitted, wherein the target channel is one of the PCIe channels between the first system on chip and the second system on chip, and the target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources; The target channel resource is used to send the data to be transmitted to the second on-chip system. The target channel resource is one of the shared memory resource and the DMA resource. The target channel resource is matched with the target information corresponding to the data to be transmitted. The target information includes the service type or data length. Wherein, the DMA resource includes a DMA memory block, and sending the data to be transmitted to the second on-chip system through the target channel resource of the target channel includes: sending the data to be transmitted to the second on-chip system through the DMA resource of the target channel; Sending the data to be transmitted to the second on-chip system via the DMA resources of the target channel includes: The data to be transmitted is sent to the DMA memory block through the target channel; Send transmission information to the target memory block in the shared memory corresponding to the target channel, wherein the transmission information includes a destination address and the data length of the data to be transmitted, and the destination address is the address of the DMA memory block; A second doorbell signal is sent to the second system-on-chip so that the second system-on-chip receives the data to be transmitted in the DMA memory block according to the transmission information in the target memory block.

2. The method according to claim 1, characterized in that, The target information includes a service type, which includes a control type and a data type. Sending the data to be transmitted to the second on-chip system via the target channel resource includes: When the service type of the data to be transmitted is the control type, the data to be transmitted is sent to the second on-chip system through the shared memory resources of the target channel; When the service type of the data to be transmitted is the data type mentioned above, the data to be transmitted is sent to the second system-on-chip through the DMA resources of the target channel.

3. The method according to claim 1, characterized in that, The target information includes the data length, and sending the data to be transmitted to the second on-chip system through the target channel resource of the target channel includes: If the length of the data to be transmitted is less than or equal to the target threshold, the data to be transmitted is sent to the second on-chip system through the shared memory resources of the target channel; If the length of the data to be transmitted is greater than the target threshold, the data to be transmitted is sent to the second on-chip system through the DMA resources of the target channel.

4. The method according to claim 2 or 3, characterized in that, The shared memory resource includes a target memory block in the shared memory corresponding to the target channel. Sending the data to be transmitted to the second on-chip system through the shared memory resource of the target channel includes: The data to be transmitted is sent to the target memory block through the target channel; A first doorbell signal is sent to the second system-on-chip so that the second system-on-chip can receive the data to be transmitted in the target memory block.

5. The method according to claim 1, characterized in that, The destination address is the one sent by the second on-chip system to the target memory block. Before sending the data to be transmitted to the DMA memory block through the target channel, the method includes: Obtain the destination address stored in the target memory block.

6. The method according to any one of claims 1-3, characterized in that, The target channel includes a shared channel or a dedicated channel. The shared channel is used to transmit data from multiple processes, and the dedicated channel is used to transmit data from one process. Obtaining the target channel corresponding to the data to be transmitted includes: Based on the process priority of the target process corresponding to the data to be transmitted, the target channel is determined to be either the shared channel or the dedicated channel.

7. A data transmission method, characterized in that, The method is applied to a second system-on-a-chip, which is connected to the first system-on-a-chip via a high-speed serial computer expansion bus standard PCIe bus. The method includes: The system receives data to be transmitted sent by the first system-on-a-chip through the target channel resources of the target channel, wherein the target channel is one of the PCIe channels between the first system-on-a-chip and the second system-on-a-chip, the target channel is configured with corresponding channel resources, the channel resources include shared memory resources and direct memory access (DMA) resources, the target channel resources are one of the shared memory resources and the DMA resources, and the target channel resources are matched with the target information corresponding to the data to be transmitted, the target information including service type or data length; The DMA resources include DMA memory blocks, and receiving the data to be transmitted sent by the first on-chip system through the target channel resources of the target channel includes: The system receives a second doorbell signal sent by the first on-chip system, wherein the second doorbell signal is used to instruct the second on-chip system to receive the data to be transferred in the DMA memory block according to the transfer information in the target memory block; Obtain the transfer information in the target memory block, where the transfer information includes the destination address and the data length of the data to be transferred, and the destination address is the address of the DMA memory block; Based on the destination address and the length of the data to be transmitted, receive the data to be transmitted from the DMA memory block.

8. A data transmission device, characterized in that, The device is applied to a first system-on-a-chip, which is connected to a second system-on-a-chip via a high-speed serial computer expansion bus standard PCIe bus. The device includes: The channel acquisition module is used to acquire the target channel corresponding to the data to be transmitted, wherein the target channel is one of the PCIe channels between the first on-chip system and the second on-chip system, and the target channel is configured with corresponding channel resources, including shared memory resources and direct memory access (DMA) resources; The data transmission module is used to send the data to be transmitted to the second on-chip system through the target channel resource of the target channel, wherein the target channel resource is one of the shared memory resource and the DMA resource, and the target channel resource is matched with the target information corresponding to the data to be transmitted, the target information including service type or data length; Wherein, the DMA resource includes a DMA memory block, and the data transmission module is used to send the data to be transmitted to the second on-chip system through the DMA resource of the target channel. Specifically, the data transmission module is used for: The data to be transmitted is sent to the DMA memory block through the target channel; Send transmission information to the target memory block in the shared memory corresponding to the target channel, wherein the transmission information includes a destination address and the data length of the data to be transmitted, and the destination address is the address of the DMA memory block; A second doorbell signal is sent to the second system-on-chip so that the second system-on-chip receives the data to be transmitted in the DMA memory block according to the transmission information in the target memory block.

9. A data transmission device, characterized in that, The device is applied to a second system-on-a-chip, which is communicatively connected to the first system-on-a-chip via a high-speed serial computer expansion bus standard PCIe bus. The device includes: The data receiving module is used to receive data to be transmitted sent by the first on-chip system through the target channel resources of the target channel. The target channel is one of the PCIe channels between the first on-chip system and the second on-chip system. The target channel is configured with corresponding channel resources, which include shared memory resources and direct memory access (DMA) resources. The target channel resources are one of the shared memory resources and the DMA resources. The target channel resources are matched with target information corresponding to the data to be transmitted. The target information includes service type or data length. The DMA resources include DMA memory blocks, and the data receiving module is specifically used for: The system receives a second doorbell signal sent by the first on-chip system, wherein the second doorbell signal is used to instruct the second on-chip system to receive the data to be transferred in the DMA memory block according to the transfer information in the target memory block; Obtain the transfer information in the target memory block, where the transfer information includes the destination address and the data length of the data to be transferred, and the destination address is the address of the DMA memory block; Based on the destination address and the length of the data to be transmitted, receive the data to be transmitted from the DMA memory block.

10. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-6 or 7.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-6 or 7.

Images