Power device and preparation method thereof

Abstract

The invention provides a power device and a preparation method thereof. The preparation method comprises the following steps: forming a P-type layer and an N-type layer on an N-type substrate; forming a groove; performing ion implantation to form an N-type source region; forming a gate oxide layer in the groove; forming a first polycrystalline silicon layer, a thick oxide layer and a second polycrystalline silicon layer in the groove; depositing a dielectric layer; forming a source contact region, wherein the source contact region exposes a part of the N-type source region and a part of the P-type layer; forming an insulating layer; forming a gate contact region, wherein the gate contact region extends into the first polycrystalline silicon layer; forming a drain contact region, wherein the N-type layer is exposed out of the drain contact region; and forming a source electrode, a grid electrode and a drain electrode, wherein the source electrode is simultaneously contacted with the N-type source region and the P-type epitaxial layer. According to the invention, the source electrode, the grid electrode and the drain electrode can be attached to the heat dissipation substrate at the same time, so that the heat dissipation path is greatly optimized, and the access inductance of the source electrode is reduced; the connection of the P-type layer and the N-type source region is formed in the device through the groove, so that the process can be effectively simplified, an additional lead-out process is avoided, and the manufacturing cost is effectively saved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a power device and a preparation method thereof. BACKGROUND

[0002] In a conventional vertical power MOSFET structure, the drain is usually fabricated on the back surface of a semiconductor wafer, and the source and the gate are fabricated on the front surface of the wafer. Although this structure is mature, it has limitations in high-frequency and high-power-density application scenarios: 1) the single back-surface drain heat dissipation method cannot meet the heat dissipation requirements of high-power-density applications; and 2) the source needs to be led out through wire bonding, which introduces a large parasitic inductance, resulting in serious voltage overshoot and switching loss in the switching process.

[0003] In order to overcome the above problems, the industry has proposed a "source-down" packaging technology. One of the key implementation methods is to place the source, gate, and drain electrodes on the same plane, which facilitates packaging interconnection and heat dissipation. However, how to realize the leading-out of the electrodes of the device within the device structure without sacrificing the electrical performance (such as on-resistance and breakdown voltage) of the device, and ensuring the feasibility and reliability of manufacturing, is a challenge faced by current technology.

[0004] It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art merely because they are described in the background section of the present application. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a power device and a preparation method thereof, which solves the problem that the source-down packaging method in the prior art cannot realize the leading-out of the electrodes within the device structure while ensuring the feasibility and reliability of manufacturing.

[0006] To achieve the above object and other related objects, the present application provides a method for manufacturing a power device, which comprises the following steps: providing an N-type substrate, forming a P-type layer and an N-type layer on the N-type substrate; etching to form a trench, the trench penetrating through the N-type layer and extending into the P-type layer; forming a barrier layer in the trench to shield part of the P-type layer, forming an N-type source region under the trench by ion implantation, the N-type source region extending from the lower part of the trench into the N-type substrate, and removing the barrier layer; forming a gate oxide layer in the trench; forming a gate stack structure of a first polysilicon layer, a thick oxide layer and a second polysilicon layer in the trench, the thick oxide layer also being formed on the sidewall between the second polysilicon layer and the trench; depositing a dielectric layer on the N-type layer; etching the dielectric layer and the gate stack structure in a first region to form a source contact region, the source contact region exposing part of the N-type source region and part of the P-type layer; forming an insulating layer on the sidewall of the gate stack structure in the source contact region; etching the dielectric layer and the gate stack structure in a second region to form a gate contact region, the gate contact region penetrating through the second polysilicon layer and the thick oxide layer and extending into the first polysilicon layer; etching and removing the dielectric layer in a third region to form a drain contact region, the drain contact region exposing the N-type layer; depositing a metal layer on the dielectric layer and in the source contact region, the gate contact region and the drain contact region, and patterning the metal layer to form a source electrode, a gate electrode and a drain electrode respectively, the source electrode being in contact with the N-type source region and the P-type epitaxial layer at the same time.

[0007] Optionally, forming the P-type layer and the N-type layer on the N-type substrate comprises: growing a P-type epitaxial layer on the N-type substrate by an epitaxial process; and growing an N-type epitaxial layer on the P-type epitaxial layer by an epitaxial process.

[0008] Optionally, the P-type epitaxial layer has a resistivity of 0.1 ohm·cm to 0.4 ohm·cm and a thickness of 0.2 μm to 1.5 μm, and the N-type epitaxial layer has a resistivity of 0.1 ohm·cm to 10 ohm·cm and a thickness of 0.5 μm to 10 μm.

[0009] Optionally, the trench has a depth of 1.5 μm to 12 μm, a distance from the bottom of the trench to the N-type substrate of 0.1 μm to 0.6 μm, and a width of 0.8 μm to 6 μm.

[0010] Optionally, the N-type source region extends into the N-type substrate from the bottom surface and part of the sidewall of the trench, and the N-type source region is formed by implanting N-type ions into the bottom of the trench to make at least the P-type epitaxial layer under the trench become an N-type source region, the N-type ions being phosphorus or arsenic, the energy of the ion implantation being 20 kev to 800 kev, and the dose of the ion implantation being 1e12 cm -2 ~1e16 cm -2 .

[0011] Optionally, the forming the gate stack structure comprises: filling the trench with the first polysilicon layer and etching the first polysilicon layer to a depth in the trench to expose the top of the trench, the top surface of the etched first polysilicon layer being higher than the interface between the N-type layer and the P-type layer; forming a thick oxide layer on the surface of the first polysilicon layer and the sidewall of the top of the trench; depositing the second polysilicon layer on the top of the trench and performing a planarization process on the second polysilicon layer to remove the second polysilicon layer on the surface of the N-type layer.

[0012] Optionally, the thickness of the gate oxide layer is 100 Å~1200 Å, the thickness of the thick oxide layer is 700 Å~2000 Å, and the top surface of the first polysilicon layer is 0.1 μm~1 μm higher than the interface between the N-type layer and the P-type layer.

[0013] Optionally, the depth of the gate contact region extending into the first polysilicon layer is 0 μm~0.5 μm.

[0014] Optionally, the thickness of the metal layer is 0.5 μm~8 μm, and the top surfaces of the source, the gate and the drain are at the same height.

[0015] Optionally, the width of the P-type layer exposed by the source contact region is 0.1 μm~20 μm, and the width of the N-type source region exposed by the source contact region is 0.1 μm~20 μm.

[0016] Optionally, the height difference between the upper surface of the second polysilicon layer and the surface of the N-type epitaxial layer is 0 μm~0.2 μm.

[0017] The application further provides a power device, which comprises: an N-type substrate, a P-type layer and an N-type layer being formed on the N-type substrate; a trench, the trench penetrating through the N-type layer and extending into the P-type layer; an N-type source region, the N-type source region being formed below part of the trench and extending from the lower part of the trench into the N-type substrate, and the P-type layer adjacent to the N-type source region being reserved below the trench; a gate oxide layer, the gate oxide layer being formed in the trench; a gate stack structure, the gate stack structure being formed in the trench and comprising a first polysilicon layer, a thick oxide layer and a second polysilicon layer, and the thick oxide layer being further formed on the sidewall between the second polysilicon layer and the trench; a dielectric layer, the dielectric layer being formed on the N-type layer; a source contact region, the source contact region being formed by etching the dielectric layer and the gate stack structure in a first region, and the source contact region exposing part of the N-type source region and part of the P-type layer; an insulating layer, the insulating layer being formed on the sidewall of the gate stack structure of the source contact region; a gate contact region, the gate contact region being formed by etching the dielectric layer and the gate stack structure in a second region, and the gate contact region penetrating through the second polysilicon layer and the thick oxide layer and extending into the first polysilicon layer; a drain contact region, the drain contact region being formed by etching the dielectric layer in a third region, and the drain contact region exposing the N-type layer; a source, a gate and a drain, the source, the gate and the drain being respectively formed in the source contact region, the gate contact region and the drain contact region, and the source simultaneously contacting the N-type source region and the P-type epitaxial layer.

[0018] Optionally, the P-type layer and the N-type layer are a P-type epitaxial layer and an N-type epitaxial layer respectively, the P-type epitaxial layer has a resistivity of 0.1 ohm·cm-0.4 ohm·cm and a thickness of 0.2 μm-1.5 μm, and the N-type epitaxial layer has a resistivity of 0.1 ohm·cm-10 ohm·cm and a thickness of 0.5 μm-10 μm.

[0019] Optionally, the gate oxide layer has a thickness of 100 Å-1200 Å, the thick oxide layer has a thickness of 700 Å-2000 Å, and the top surface of the first polysilicon layer is 0.1 μm-1 μm higher than the interface between the N-type layer and the P-type layer.

[0020] Optionally, the source, the gate and the drain have a thickness of 0.5 μm-8 μm, and the top surfaces of the source, the gate and the drain are at the same height.

[0021] Optionally, the P-type layer exposed by the source contact region has a width of 0.1 μm-20 μm, and the N-type source region exposed by the source contact region has a width of 0.1 μm-20 μm.

[0022] As described above, the power device and the preparation method thereof have the following beneficial effects: Different from the conventional P-type body region formed by ion implantation, the P-type layer is formed by epitaxial growth in the present application. The epitaxial growth can accurately control the thickness, doping concentration and uniformity of the P-type layer, and can avoid the lattice damage and defects caused by high-energy ion implantation, so that a more uniform and reliable body region is obtained, which is beneficial to improve the breakdown voltage and avalanche resistance of the device, and to improve the long-term reliability and consistency of the device.

[0023] In the present application, the source, the gate and the drain are arranged on the same plane by etching in a specific area and filling metal to connect to the N-type source region from the front surface of the device downward. On the one hand, the present application can omit the back grinding and metallization process, and simplify the packaging process; on the other hand, the present application can simultaneously mount the source, the gate and the drain to the heat dissipation substrate by realizing the “source downward” packaging structure, which greatly optimizes the heat dissipation path and reduces the source path inductance; on the third hand, the connection between the P-type layer (body region) and the N-type source region is formed inside the device through a groove, which can effectively simplify the process, avoid additional lead-out process and effectively save the manufacturing cost.

[0024] The present application adopts a two-layer shielding gate structure, and connects the first polysilicon layer and the second polysilicon layer through a contact hole, the first polysilicon layer in the lower layer acts as a control gate, which can more quickly control the switching of the power device, and the second polysilicon layer can accumulate carriers on the surface of the thick oxide layer when the device is turned on to reduce the on-resistance of the device, and can adjust the depletion and field strength in the N-type layer when the reverse withstand voltage, thereby improving the withstand voltage capacity of the device. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0026] Figure 1 A surface layout structure of a power device according to an embodiment of the present application.

[0027] Figures 2-14 A structure according to each step of a manufacturing method of a power device according to an embodiment of the present application. Figure 14 A structure of a power device according to an embodiment of the present application.

[0028] Element No. Explanation N-type substrate 101, P-type layer 102, N-type layer 103, Trench 104, Barrier layer 105, N-type source region 106, Gate oxide layer 107, First polysilicon layer 108, Thick oxide layer 109, Second polysilicon layer 110, Dielectric layer 111, Source contact region 112, Insulating layer 113, Gate contact region 114, Drain contact region 115, Source electrode 116, Gate electrode 117, Drain electrode 118. DETAILED DESCRIPTION

[0029] The above embodiments of the present application are shown and described by way of specific examples. Those skilled in the art will readily recognize from the disclosure herein that the application is not limited to the embodiments described and illustrated. The scope of the application is defined by the appended claims and their equivalents.

[0030] It should be emphasized that the term "comprises / comprising" when used in this specification is taken to mean the presence of stated features, integers, steps or components but not the exclusion of one or more other features, integers, steps, components or groups thereof.

[0031] Features described and / or illustrated with respect to one embodiment can be used in the same or similar manner in one or more other embodiments, in combination with or in place of features in other embodiments, or in place of or in addition to features in other embodiments.

[0032] As described in the detailed description of the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general scale for the convenience of explanation, and the schematic view is only an example, which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacture.

[0033] For the sake of convenience, the terms "under", "below", "lower", "beneath", "above", "upper" and the like can be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a layer overlies another layer, it can be the case that the layer is the only layer between the other layer and the underlying layer, or that one or more intervening layers can also be present. Moreover, when a layer is referred to as being "between" two layers, it can be the case that the layer is the only layer between the other two layers, or that one or more intervening layers can also be present.

[0034] In the context of the present application, a structure described as having a first feature "on" a second feature can include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features can not be in direct contact.

[0035] It should be noted that the drawings provided in the embodiments are only schematic and are intended to provide the basic understanding of the application. In the drawings, the shape, thickness and size of the components can be exaggerated for the sake of clarity and convenience, and the actual shape, thickness and size of the components can be different from those shown in the drawings. In addition, the layout of the components can be more complex than that shown in the drawings.

[0036] As shown in FIG. 1, Figures 1-14 As shown in FIG. 1, Figure 1 a surface layout of the power device is shown, Figures 2-14 Each of the figures in FIG. 1 shows a cross-sectional structure of the power device at the cross section of A-A', B-B', and C-C', respectively. The embodiments provide a preparation method of a power device, which includes the following steps: As shown in FIG. 1, Figure 2 First, step 1) is performed, and an N-type substrate 101 is provided. A P-type layer 102 and an N-type layer 103 are formed on the N-type substrate 101.

[0037] In one embodiment, the N-type substrate 101 can be a heavily doped N-type silicon substrate, and the resistivity of the N-type substrate 101 can be less than 0.01 ohm·cm.

[0038] In one embodiment, the step of forming the P-type layer 102 and the N-type layer 103 on the N-type substrate 101 includes the following steps: In step 1-1, a P-type epitaxial layer is grown on the N-type substrate 101 by an epitaxial process, and the dopant can be boron (B). The P-type epitaxial layer has a resistivity of 0.1 ohm-cm to 0.4 ohm-cm, for example, 0.1 ohm-cm, 0.2 ohm-cm, 0.3 ohm-cm, or 0.4 ohm-cm, and a thickness of 0.2 μm to 1.5 μm, for example, 0.2 μm, 0.5 μm, 1.0 μm, or 1.5 μm. Unlike the conventional P-type body region formed by ion implantation, the P-type layer 102 is formed by epitaxial growth in the present application. The epitaxial growth can precisely control the thickness, doping concentration, and uniformity of the P-type layer 102, and can avoid lattice damage and defects caused by high-energy ion implantation, thereby obtaining a more uniform and reliable body region, which is beneficial to improve the breakdown voltage and avalanche resistance of the device, and to improve the long-term reliability and consistency of the device.

[0039] In step 1-2, an N-type epitaxial layer is grown on the P-type epitaxial layer by an epitaxial process, and the dopant can be phosphorus (P) or arsenic (As).

[0040] In one embodiment, the N-type epitaxial layer has a resistivity of 0.1 ohm-cm to 10 ohm-cm, for example, 0.1 ohm-cm, 1 ohm-cm, 5 ohm-cm, or 10 ohm-cm, and a thickness of 0.5 μm to 10 μm, for example, 0.5 μm, 2 μm, 5 μm, or 10 μm.

[0041] As shown in FIG. 1C, step 2) is then performed to etch a trench 104 that extends through the N-type layer 103 and into the P-type layer 102. Figure 3 In one embodiment, the depth of the trench 104 is 1.5 μm to 12 μm, for example, 2 μm, 5 μm, 8 μm, or 12 μm, the distance from the bottom of the trench 104 to the N-type substrate 101 is 0.1 μm to 0.6 μm, for example, 0.1 μm, 0.3 μm, 0.5 μm, 0.6 μm, or the like, and the width of the trench 104 is 0.8 μm to 6 μm, for example, 0.8 μm, 2 μm, 4 μm, 6 μm, or the like.

[0042] As shown in FIG. 1D, step 3) is then performed to form a barrier layer 105 in the trench 104 to shield the P-type layer 102, form an N-type source region 106 by ion implantation under the trench 104, and remove the barrier layer 105.

[0043] Figures 4-5

[0044] ​​In one embodiment, forming a barrier layer 105 in the trench 104 to block a portion of the P-type layer 102 includes: fabricating photoresist by spin coating, and then forming a patterned photoresist layer by exposure and development processes to serve as the barrier layer 105.

[0045] In one embodiment, the N-type source region 106 extends from the bottom surface and part of the side surface of the trench 104 into the N-type substrate 101. The N-type source region 106 is formed by implanting N-type ions (e.g., phosphorus, arsenic, etc.) into the bottom of the trench 104 to at least invert the P-type epitaxial layer below the trench 104 into the N-type source region 106. The N-type ions are phosphorus or arsenic, the ion implantation energy is 20 keV to 800 keV, and the ion implantation dose is 1e12cm. -2 ~1e16cm -2 .

[0046] like Figure 6 As shown, then step 4) is performed to form a gate oxide layer 107 in the trench 104 by means of thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition; in some embodiments, the thickness of the gate oxide layer 107 is 100 Å to 1200 Å, for example, it can be 100 Å, 300 Å, 500 Å, 800 Å, 1200 Å, etc.

[0047] like Figures 7-9 As shown, step 5 is then performed, forming a gate stack structure of a first polysilicon layer 108, a thick oxide layer 109, and a second polysilicon layer 110 in the trench 104. The thick oxide layer 109 is also formed on the sidewall between the second polysilicon layer 110 and the trench 104.

[0048] In one embodiment, forming the gate stack structure includes: A first polysilicon layer 108 is filled into the trench 104 and etched to a depth within the trench 104 to expose the top of the trench 104. The top surface of the etched first polysilicon layer 108 is higher than the interface between the N-type layer 103 and the P-type layer 102 to form a gate 117 structure, so that the first polysilicon layer 108 can control the formation of a continuous channel when a suitable voltage is applied. For example, the top surface of the etched first polysilicon layer 108 is 0.1 μm to 1 μm higher than the interface between the N-type layer 103 and the P-type layer 102, for example, it can be 0.1 μm, 0.3 μm, 0.5 μm, 1 μm, etc.

[0049] A thick oxide layer 109 is formed on the surface of the first polysilicon layer 108 and the top sidewall of the trench 104 by means of thermal oxidation process, plasma-enhanced chemical vapor deposition process, etc.; in one embodiment, the thickness of the thick oxide layer 109 is 700 Å to 2000 Å, for example, it can be 700 Å, 1000 Å, 1500 Å, 2000 Å, etc.

[0050] A second polysilicon layer 110 is deposited on top of the trench 104, and the second polysilicon layer 110 is planarized to remove the second polysilicon layer 110 from the surface of the N-type layer 103. In one embodiment, the height difference between the upper surface of the second polysilicon layer 110 and the surface of the N-type epitaxial layer is 0 μm to 0.2 μm.

[0051] like Figure 10 As shown, then step 6) is performed to deposit a dielectric layer on the N-type layer 103; for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a stack of the above materials can be deposited on the N-type layer 103 as a dielectric layer using a process such as plasma-enhanced chemical vapor deposition.

[0052] like Figure 10 As shown, step 7) is then performed, etching the dielectric layer and gate stack structure in the first region to form source contact region 112, which exposes a portion of the N-type source region 106 and a portion of the P-type layer 102.

[0053] In one embodiment, the width of the P-type layer 102 exposed by the source contact region 112 is 0.1μm to 20μm, for example, it can be 0.1μm, 5μm, 10μm, 20μm, etc., and the width of the N-type source region 106 exposed by the source contact region 112 is 0.1μm to 20μm, for example, it can be 0.1μm, 5μm, 10μm, 20μm, etc.

[0054] like Figure 11 As shown, then step 8) is performed to form an insulating layer 113 on the sidewall of the gate stack structure in the source contact region 112.

[0055] For example, an insulating layer 113 can be formed on the sidewalls and bottom of the gate stack structure in the source contact region 112 by thermal oxidation or plasma-enhanced chemical vapor deposition. Then, the bottom insulating layer 113 can be removed by etching to expose the N-type source region 106 and part of the P-type layer 102.

[0056] like Figure 12 As shown, step 9) is then performed, etching the dielectric layer and gate stack structure in the second region to form a gate contact region 114, which penetrates the second polysilicon layer 110 and the thick oxide layer 109 and extends into the first polysilicon layer 108.

[0057] In one embodiment, the depth of the gate contact region 114 extending into the first polysilicon layer 108 is 0 μm to 0.5 μm, for example, it can be 0 μm, 0.1 μm, 0.2 μm, 0.5 μm, etc. This invention employs a two-layer shielded gate structure, connecting the first polysilicon layer 108 and the second polysilicon layer 110 simultaneously through a contact hole. The first polysilicon layer 108, connected to the lower layer, serves as a control gate, enabling faster control of the power device's switching. When the device is turned on, the second polysilicon layer 110 can accumulate charge carriers on the surface of the thick oxide layer 109 to reduce the device's on-resistance. During reverse voltage withstand, it can adjust the depletion and field strength distribution in the N-type layer 103, thereby improving the device's withstand voltage capability.

[0058] like Figure 13 As shown, then step 10) is performed, etching away the dielectric layer in the third region to form a drain contact region 115, which exposes the N-type layer 103.

[0059] like Figure 14 As shown, in step 11), a metal layer is deposited on the dielectric layer and in the source contact region 112, gate contact region 114, and drain contact region 115. The metal layer is patterned to form the source 116, gate 117, and drain 118, respectively. The source 116 is simultaneously in contact with the N-type source region 106 and the P-type epitaxial layer. This invention achieves a co-planar layout of the source 116, gate 117, and drain 118 by etching and filling metal in a specific area, directly connecting from the front side of the device downwards to the N-type source region 106. On the one hand, the present invention can eliminate the back-side grinding and metallization process, simplifying the packaging process; on the other hand, by realizing the "source 116 facing down" packaging structure, the present invention can simultaneously mount the source 116, gate 117, and drain 118 to the heat dissipation substrate, greatly optimizing the heat dissipation path and reducing the inductance of the source 116 path; thirdly, the connection between the P-type layer 102 (body region) and the N-type source region 106 is formed inside the device through the trench 104, which can effectively simplify the process, avoid additional lead-out processes, and effectively save manufacturing costs.

[0060] In one embodiment, the thickness of the metal layer is 0.5μm to 8μm. For example, the thickness of the metal layer can be 0.5μm, 1μm, 2μm, 5μm, 8μm, etc., and the top surface heights of the source 116, gate 117 and drain 118 are the same.

[0061] like Figure 1 and Figure 14As shown, the embodiment also provides a power device which can be prepared by the preparation method of the power device of the above embodiment, and the power device comprises: an N-type substrate 101, a P-type layer 102 and an N-type layer 103 are formed on the N-type substrate 101; a trench 104 which penetrates the N-type layer 103 and extends into the P-type layer 102; an N-type source region 106 which is formed below part of the trench 104, the N-type source region 106 extends from the lower part of the trench 104 into the N-type substrate 101, and the P-type layer 102 adjacent to the N-type source region 106 is also reserved below the trench 104; a gate oxide layer 107 which is formed in the trench 104; a gate stack structure which is formed in the trench 104, the gate stack structure comprises a first polysilicon layer 108, a thick oxide layer 109 and a second polysilicon layer 110, and the thick oxide layer 109 is also formed on the sidewall between the second polysilicon layer 110 and the trench 104; a dielectric layer 111 which is formed on the N-type layer 103; a source contact region 112 which is formed by etching the dielectric layer 111 and the gate stack structure in a first region, the source contact region 112 exposes part of the N-type source region 106 and part of the P-type layer 102; an insulating layer 113 which is formed on the gate stack structure sidewall of the source contact region 112; a gate contact region 114 which is formed by etching the dielectric layer 111 and the gate stack structure in a second region, the gate contact region 114 penetrates the second polysilicon layer 110 and the thick oxide layer 109 and extends into the first polysilicon layer 108; a drain contact region 115 which is formed by etching the dielectric layer in a third region, the drain contact region 115 exposes the N-type layer 103; a source electrode 116, a gate electrode 117 and a drain electrode 118 which are respectively formed in the source contact region 112, the gate contact region 114 and the drain contact region 115, and the source electrode 116 simultaneously contacts the N-type source region 106 and the P-type epitaxial layer.

[0062] In one embodiment, the P-type layer 102 and the N-type layer 103 are respectively a P-type epitaxial layer and an N-type epitaxial layer, the P-type epitaxial layer has a resistivity of 0.1 ohm·cm~0.4 ohm·cm and a thickness of 0.2 μm~1.5 μm, and the N-type epitaxial layer has a resistivity of 0.1 ohm·cm~10 ohm·cm and a thickness of 0.5 μm~10 μm.

[0063] In one embodiment, the thickness of the gate oxide layer 107 is 100 Å~1200 Å, the thickness of the thick oxide layer 109 is 700 Å~2000 Å, and the top surface of the first polysilicon layer 108 is 0.1 μm~1 μm higher than the interface between the N-type layer 103 and the P-type layer 102.

[0064] In one embodiment, the thickness of the source electrode 116, the gate electrode 117 and the drain electrode 118 is 0.5 μm~8 μm, and the top surfaces of the source electrode 116, the gate electrode 117 and the drain electrode 118 are at the same height.

[0065] In one embodiment, the width of the P-type layer 102 exposed by the source contact region 112 is 0.1-20 μm, and the width of the N-type source region 106 exposed by the source contact region 112 is 0.1-20 μm.

[0066] As described above, the power device and the preparation method thereof have the following beneficial effects: Unlike the conventional P-type body region formed by ion implantation, the P-type layer 102 is formed by epitaxial growth. The thickness and the doping concentration and uniformity of the P-type layer 102 can be precisely controlled, and the lattice damage and defects caused by high-energy ion implantation can be avoided, so that a more uniform and reliable body region is obtained, which is beneficial to improve the breakdown voltage and avalanche resistance of the device and improve the long-term reliability and consistency of the device.

[0067] The present application directly connects to the N-type source region 106 from the front of the device downward by etching in a specific region and filling metal, so as to realize the same-plane layout of the source 116, the gate 117 and the drain 118. On the one hand, the present application can omit the back-grinding and metallization process, and simplify the packaging process; on the other hand, the present application can simultaneously mount the source 116, the gate 117 and the drain 118 to the heat dissipation substrate by realizing the "downward source 116" packaging structure, so as to greatly optimize the heat dissipation path and reduce the source 116 path inductance; and thirdly, the connection between the P-type layer 102 (body region) and the N-type source region 106 is formed inside the device through the trench 104, which can effectively simplify the process, avoid the additional lead-out process and effectively save the manufacturing cost.

[0068] The present application adopts a two-layer shielding gate structure, and connects the first polysilicon layer 108 and the second polysilicon layer 110 through one contact hole, and the first polysilicon layer 108 in the lower layer is used as the control gate, so that the switching of the power device can be more quickly controlled; the second polysilicon layer 110 can accumulate carriers on the surface of the thick oxide layer 109 when the device is turned on, so as to reduce the on-resistance of the device, and can adjust the depletion and field strength in the N-type layer 103 when the reverse withstand voltage, so as to improve the withstand voltage capacity of the device.

[0069] Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0070] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a power device, characterized in that, The preparation method includes: An N-type substrate is provided, on which a P-type layer and an N-type layer are formed; Trenches are formed by etching, the trenches penetrating the N-type layer and extending into the P-type layer; A barrier layer is formed in the trench to partially block the P-type layer. An N-type source region is formed below the trench by ion implantation. The N-type source region extends from the lower part of the trench into the N-type substrate. The barrier layer is then removed. A gate oxide layer is formed in the trench; A gate stack structure consisting of a first polysilicon layer, a thick oxide layer, and a second polysilicon layer is formed in the trench, and the thick oxide layer is also formed on the sidewall between the second polysilicon layer and the trench. A dielectric layer is deposited on the N-type layer; The dielectric layer and the gate stack structure are etched in a first region to form a source contact region, the source contact region exposing a portion of the N-type source region and a portion of the P-type layer; An insulating layer is formed on the sidewall of the gate stack structure in the source contact region; The dielectric layer and the gate stack structure are etched in the second region to form a gate contact region, which penetrates the second polysilicon layer and the thick oxide layer and extends into the first polysilicon layer. The dielectric layer is etched away in the third region to form a drain contact region, which exposes the N-type layer. A metal layer is deposited on the dielectric layer and in the source contact region, gate contact region and drain contact region. The metal layer is patterned to form the source, gate and drain respectively. The source is in contact with both the N-type source region and the P-type layer.

2. The method for fabricating a power device according to claim 1, characterized in that: Forming a P-type layer and an N-type layer on the N-type substrate includes: A P-type epitaxial layer is grown on the N-type substrate using an epitaxial process. An N-type epitaxial layer is grown on the P-type epitaxial layer using an epitaxial process.

3. The method for fabricating the power device according to claim 2, characterized in that: The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm, and the thickness is 0.2 μm to 1.5 μm. The resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm, and the thickness is 0.5 μm to 10 μm.

4. The method for fabricating a power device according to claim 1, characterized in that: The trench has a depth of 1.5μm to 12μm, a distance of 0.1μm to 0.6μm between the bottom of the trench and the N-type substrate, and a width of 0.8μm to 6μm.

5. The method for fabricating a power device according to claim 1, characterized in that: The N-type source region extends from the bottom and part of the side of the trench into the N-type substrate. The N-type source region is formed by implanting N-type ions into the bottom of the trench to at least invert the P-type epitaxial layer below the trench into an N-type source region. The N-type ions are phosphorus or arsenic, the ion implantation energy is 20 keV to 800 keV, and the ion implantation dose is 1e12cm. -2 ~1e16cm -2 .

6. The method for fabricating a power device according to claim 1, characterized in that: The formation of the gate stack structure includes: The trench is filled with a first polysilicon layer and the first polysilicon layer is etched to a depth within the trench to expose the top of the trench. The top surface of the etched first polysilicon layer is higher than the interface between the N-type layer and the P-type layer. A thick oxide layer is formed on the surface of the first polysilicon layer and on the top sidewall of the trench; A second polysilicon layer is deposited on top of the trench, and the second polysilicon layer is planarized to remove the second polysilicon layer from the surface of the N-type layer.

7. The method for fabricating a power device according to claim 1, characterized in that: The thickness of the gate oxide layer is 100 Å to 1200 Å, the thickness of the thick oxide layer is 700 Å to 2000 Å, and the top surface of the first polysilicon layer is 0.1 μm to 1 μm higher than the interface between the N-type layer and the P-type layer.

8. The method for fabricating a power device according to claim 1, characterized in that: The depth of the gate contact area extending into the first polysilicon layer is 0 μm to 0.5 μm.

9. The method for fabricating a power device according to claim 1, characterized in that: The thickness of the metal layer is 0.5μm to 8μm, and the top surfaces of the source, gate, and drain are at the same height.

10. The method for fabricating a power device according to claim 1, characterized in that: The width of the P-type layer exposed in the source contact region is 0.1 μm to 20 μm, and the width of the N-type source region exposed in the source contact region is 0.1 μm to 20 μm.

11. The method for fabricating a power device according to claim 1, characterized in that: The height difference between the upper surface of the second polycrystalline silicon layer and the surface of the N-type layer is 0 μm ~ 0.2 μm.

12. A power device, characterized in that, The power device includes: An N-type substrate, wherein a P-type layer and an N-type layer are formed on the N-type substrate; The trench penetrates the N-type layer and extends into the P-type layer; An N-type source region is formed below a portion of the trench, the N-type source region extending from the lower part of the trench into the N-type substrate, and a P-type layer adjacent to the N-type source region is also retained below the trench; A gate oxide layer is formed in the trench; A gate stack structure is formed in the trench, the gate stack structure including a first polysilicon layer, a thick oxide layer and a second polysilicon layer, the thick oxide layer also being formed on the sidewall between the second polysilicon layer and the trench; A dielectric layer is formed on the N-type layer; The source contact region is formed by etching the dielectric layer and the gate stack structure of the first region, and the source contact region exposes part of the N-type source region and part of the P-type layer; An insulating layer is formed on the sidewall of the gate stack structure in the source contact region; The gate contact region is formed by etching the dielectric layer and the gate stack structure of the second region. The gate contact region penetrates the second polysilicon layer and the thick oxide layer and extends into the first polysilicon layer. The drain contact region is formed by etching the dielectric layer of the third region, and the drain contact region exposes the N-type layer; The source, gate, and drain are formed in the source contact region, gate contact region, and drain contact region, respectively, and the source is in contact with both the N-type source region and the P-type layer.

13. The power device according to claim 12, characterized in that: The P-type layer and N-type layer are respectively a P-type epitaxial layer and an N-type epitaxial layer. The resistivity of the P-type epitaxial layer is 0.1 ohm·cm to 0.4 ohm·cm and the thickness is 0.2 μm to 1.5 μm. The resistivity of the N-type epitaxial layer is 0.1 ohm·cm to 10 ohm·cm and the thickness is 0.5 μm to 10 μm.

14. The method for fabricating a power device according to claim 12, characterized in that: The thickness of the gate oxide layer is 100 Å to 1200 Å, the thickness of the thick oxide layer is 700 Å to 2000 Å, and the top surface of the first polysilicon layer is 0.1 μm to 1 μm higher than the interface between the N-type layer and the P-type layer.

15. The method for fabricating a power device according to claim 12, characterized in that: The thickness of the source, gate, and drain is 0.5μm to 8μm, and the top surface height of the source, gate, and drain is the same.

16. The method for fabricating a power device according to claim 12, characterized in that: The width of the P-type layer exposed in the source contact region is 0.1 μm to 20 μm, and the width of the N-type source region exposed in the source contact region is 0.1 μm to 20 μm.

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