Downlink data sending system for space navigation

Abstract

The invention discloses a downlink data sending system for space navigation, which starts from improving the efficiency of a measurement and transmission integrated downlink channel, adopts an FPGA (Field Programmable Gate Array) to realize a data scheduling technology, completes the distribution of downlink caches of five kinds of data according to a data address specified by CPU (Central Processing Unit) software, and opens the real-time read-write address of each cache to the CPU software. And meanwhile, the FPGA provides five data downlink proportion control registers for the CPU software, and the data downlink proportion is controlled by the CPU software, so that the functions of flexible configuration and balanced transmission of telemetering and data transmission downlink are realized, the consumption of a satellite hardware interface on computer FPGA interface resources is reduced, and the utilization rate of a whole satellite downlink channel is improved.

Description

Technical Field

[0001] This invention belongs to the technical field of spacecraft, and particularly relates to a downlink data transmission system for space applications. Background Technology

[0002] In spaceborne electronic products, telemetry downlink and data transmission downlink are essential functions, and the integration requirements for the entire satellite are becoming increasingly stringent. Currently, a "computer + telemetry and control transponder + data transmitter" scheme is commonly used. In this scheme, telemetry downlink is controlled by the telemetry and control transponder, and data transmission downlink is controlled by the data transmitter. Since the telemetry and control transponder and the data transmitter are two separate products with two different control algorithms, an integrated telemetry and data transmission mode cannot be achieved. Furthermore, these two products require two control interfaces, consuming significant computer interface resources, resulting in resource waste and a lack of application flexibility. Summary of the Invention

[0003] The purpose of this invention is to provide a downlink data transmission system for space applications, which can merge the satellite's data transmission channel and telemetry downlink channel into one channel. The specific downlink data can be configured through either onboard autonomous control or ground intervention, enabling the satellite's downlink data configuration to be adjusted in real time and flexibly according to requirements.

[0004] To solve the above problems, the technical solution of the present invention is as follows: A downlink data transmission system for aerospace applications includes: a CPU, an FPGA, an SRAM, a NAND FLASH, and an RS422 interface circuit; the RS422 interface circuit, the CPU, the SRAM, and the NAND FLASH are respectively connected to the FPGA; the NAND FLASH is used to store payload data, and the SRAM is used to cache payload data and various downlink data to be transmitted; The FPGA is used to control the reading, writing and forwarding of SRAM data. The FPGA reads the cache size and downlink data ratio configured by the CPU, reads the data of each cache in sequence according to the downlink data ratio, and sends the data transmission data and telemetry downlink data to the RS422 interface circuit. The RS422 interface circuit converts the TTL clock and data signals sent by the FPGA into RS422 differential levels and sends them outward.

[0005] According to one embodiment of the present invention, the SRAM provides multiple data cache areas for the FPGA, the capacity of each cache area is independently set by the CPU in granularity of 1 KB between 2 KB and 312 KB, and the sum of the capacities of the cache areas does not exceed a preset value.

[0006] According to an embodiment of the present invention, the CPU includes: a cache partitioning module, configured to write a capacity setting value into multiple address registers provided by the FPGA to partition corresponding cache areas in the SRAM; a matching configuration module, configured to write downlink data matching information into the matching control register of the FPGA, wherein the matching information is in units of frames; and a data write-back module, configured to pre-write the data to be sent into the corresponding cache area according to the read cache address fed back by the FPGA in real time, so as to ensure the frame continuity of each type of data.

[0007] According to an embodiment of the present invention, the FPGA includes: a ratio reading module, configured to read the ratio control register at the beginning of each transmission cycle to determine the number of frames to be read sequentially from the plurality of buffers; a data reading module, configured to read cached data sequentially from the plurality of buffers in units of frames according to the ratio information and transmit it downlink; and an address feedback module, configured to provide the CPU with the read address of the buffer currently being read in real time.

[0008] According to one embodiment of the present invention, the ratio control register consists of five groups of 32-bit registers, which correspond to the first to fifth buffer areas in the SRAM respectively. The value in each group of registers represents the number of frames to be sent in the corresponding buffer area during the current transmission cycle.

[0009] According to one embodiment of the present invention, the data write-back module writes the next batch of data to be sent into the subsequent address of the buffer before the read address reaches the end of the corresponding buffer, so as to avoid data interruption.

[0010] According to one embodiment of the present invention, the CPU further includes a monitoring module for periodically reading the read pointer and write pointer provided by the FPGA to monitor the empty / full status of each cache area in real time.

[0011] According to one embodiment of the present invention, the FPGA includes CPU access control logic, registers, SRAM access arbitration logic, SRAM access control logic, NAND FLASH access control logic, and RS422 interface control logic. The CPU access control logic is used to map the CPU address to the SRAM and the internal register storage space of the FPGA, and to achieve timing matching between the SRAM access arbitration logic and the CPU access control logic. The SRAM access control logic is used for timing control of SRAM read and write access; The NAND FLASH access control logic is used for timing control of read and write access to the NAND FLASH. The RS422 interface control logic is used for timing control of the RS422 output; the data transmission control logic is used for switching between high and low data transmission rates, as well as buffer allocation balancing control.

[0012] According to one embodiment of the present invention, the SRAM includes six partitions, namely a fill frame buffer, an image data buffer, a payload data buffer, a delayed telemetry buffer, a real-time telemetry buffer, and other data buffers; The padding frame buffer is used as a buffer for sending padding frames during high-speed data downlink. The image data buffer is used to cache image data read by the FPGA from the NAND FLASH; The payload data buffer is used to cache payload data read by the FPGA from the NAND FLASH; The delayed telemetry buffer is used to cache delayed telemetry data read by the FPGA from the NAND FLASH; The real-time telemetry cache is used to cache engineering telemetry data generated by the CPU in real time. The other data cache area is used for data caching for other logic functions of the FPGA, as well as for cache expansion of temporary CPU data.

[0013] According to one embodiment of the present invention, the NAND FLASH includes three partitions: an engineering telemetry data area, a payload data area, and an image data area. The engineering telemetry data area is used to store engineering telemetry data generated by the CPU in real time. The load data area is used to store the load data received by the system in real time; The image data is used to store the image data received by the system.

[0014] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art: 1) In one embodiment of the present invention, the aerospace downlink data transmission system, starting from improving the efficiency of the integrated telemetry and data transmission downlink channel, adopts FPGA to implement data scheduling technology. The FPGA completes the allocation of downlink buffers for five types of data according to the data address specified by the CPU software, and exposes the real-time read and write addresses of each buffer to the CPU software. At the same time, the FPGA provides the CPU software with a ratio control register for the downlink of five types of data. The CPU software controls the ratio of downlink data, realizing the functions of flexible configuration and balanced transmission of telemetry and data transmission downlink, reducing the consumption of computer FPGA interface resources by the on-board hardware interface, and improving the utilization rate of the entire satellite downlink channel.

[0015] 2) Starting from optimizing downlink data control, the downlink data ratio and the buffer size configuration of each data type are made available to the satellite management software. The FPGA provides the satellite management software with a buffer size configuration register and a downlink data ratio control register. The satellite management software controls the downlink data ratio and buffer size configuration, while the FPGA is responsible for the specific implementation of downlink data transmission, thus realizing the function of real-time and flexible control of the downlink ratio of each type of data.

[0016] 3) Starting from simplifying the underlying data scheduling of the space service software, the FPGA control logic has been optimized. The space service software specifies the SRAM cache address and the NAND FLASH address to be read, and the FPGA automatically completes the NAND FLASH reading and stores the data in the specified SRAM cache area, realizing semi-automatic transfer of underlying data and giving the space service software application flexibility. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a space downlink data transmission system according to an embodiment of the present invention; Figure 2 This is a block diagram of the internal logic of an FPGA according to an embodiment of the present invention; Figure 3 This is a flowchart of FPGA data transmission in one embodiment of the present invention. Detailed Implementation

[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed account of a space-use downlink data transmission system proposed in this invention. The advantages and features of this invention will become more apparent from the following description and claims.

[0019] Please refer to Figure 1 This embodiment provides a downlink data transmission system for aerospace applications, including: a CPU, an FPGA, an SRAM, a NAND FLASH, and an RS422 interface circuit; wherein, the RS422 interface circuit, the CPU, the SRAM, and the NAND FLASH are respectively connected to the FPGA; the NAND FLASH is used to store payload data, and the SRAM is used to cache payload data and various downlink data to be transmitted; the FPGA is used to control the reading, writing, and forwarding of SRAM data. The FPGA reads the cache size and downlink data ratio configured by the CPU, and reads the data of each cache according to the downlink data ratio, and sends the data transmission data and telemetry downlink data to the RS422 interface circuit together; the RS422 interface circuit converts the TTL clock and data signals sent by the FPGA into RS422 differential levels and then transmits them externally.

[0020] In other words, the CPU configures the FPGA's internal registers via the bus interconnecting with the FPGA. The FPGA reads data from the NAND flash memory according to the address specified by the CPU and stores it in the SRAM range specified by the CPU. At the beginning of each interrupt cycle, the FPGA's telemetry downlink control logic reads data from the SRAM partition according to the downlink data ratio configured by the CPU, and sends the data to the RS422 interface via the parallel-to-serial converter module to transmit the data.

[0021] The above system can merge the satellite's data transmission channel and telemetry downlink channel into one channel, realizing flexible configuration and balanced transmission of telemetry and data transmission downlink, reducing the consumption of computer FPGA interface resources by the satellite hardware interface, and improving the utilization rate of the satellite's downlink channel.

[0022] Specifically, the SRAM comprises six partitions: a fill frame buffer, an image data buffer, a payload data buffer, a delay telemetry buffer, a real-time telemetry buffer, and other data buffers. The fill frame buffer is used to transmit fill frames during high-speed downlink data transmission. The image data buffer caches image data read from NAND flash by the FPGA. The payload data buffer caches payload data read from NAND flash by the FPGA. The delay telemetry buffer caches delay telemetry data read from NAND flash by the FPGA. The real-time telemetry buffer caches engineering telemetry data generated in real-time by the CPU. The other data buffers are used for data caching for other logic functions performed by the FPGA, as well as for caching temporary CPU data.

[0023] This SRAM provides multiple data buffers for the FPGA. The capacity of each buffer is independently set by the CPU in 1 KB increments, ranging from 2 KB to 312 KB, and the sum of the capacities of all buffers does not exceed a preset value. For example, the SRAM provides a 320KB data buffer for the FPGA and provides five address registers for configuring the buffer partitioning. The buffer partitioning unit is 1KB, and each of the five buffers has a minimum size of 2KB and a maximum size of 312KB, with the specific size specified by the CPU software.

[0024] The CPU in this embodiment includes: The buffer partitioning module is used to write the capacity setting value into multiple address registers provided by the FPGA to partition the corresponding buffer in SRAM; the matching configuration module is used to write the downlink data matching information into the matching control register of the FPGA, and the matching information is in units of frames; the data write-back module is used to pre-write the data to be sent into the corresponding buffer according to the read buffer address fed back by the FPGA in real time, so as to ensure the frame continuity of each type of data.

[0025] The allocation control register consists of five 32-bit registers, each corresponding to the first to fifth buffers in the SRAM. The value in each register represents the number of frames to be transmitted in the corresponding buffer during the current transmission cycle. The start and end addresses of the first to fifth buffers in the SRAM are jointly determined by the base address register and the capacity register in the five address registers, enabling the FPGA to perform boundary checks based on the start and end addresses to prevent out-of-bounds access.

[0026] Before the read address reaches the end of the corresponding buffer, the data write-back module writes the next batch of data to be sent into the subsequent address of the buffer in advance to avoid data interruption.

[0027] In other words, the CPU can implement downlink data buffer partitioning and transmission ratio control logic. Among them, the transmission control ratio can be flexibly controlled by the CPU software. The FPGA provides the CPU with a downlink data ratio control register, and the CPU software fills the data ratio into the register.

[0028] Furthermore, the CPU also includes a monitoring module for periodically reading the read and write pointers provided by the FPGA to monitor the empty / full status of each buffer in real time. Specifically, after the CPU allocates the buffers, it specifies the data ratio to be transmitted from the FPGA. The FPGA then sequentially retrieves data from the five buffers according to the data ratio specified by the CPU, with a minimum ratio of one frame (one frame corresponds to 1KB) for each data type. The CPU can monitor the FPGA's operating status in real time, obtaining the read / write pointers of the five types of downlink data in SRAM, etc. After obtaining the read address of each buffer sent by the FPGA, the CPU pre-writes the data to be transmitted into the subsequent buffers, ensuring the continuity of frames transmitted for each type of data.

[0029] Accordingly, the FPGA in this embodiment includes: a ratio reading module, used to read the ratio control register at the beginning of each transmission cycle to determine the number of frames to be read sequentially from multiple buffers; a data reading module, used to read cached data from multiple buffers sequentially in units of frames according to the ratio information and transmit it downstream; and an address feedback module, used to provide the CPU with the read address of the currently being read buffer in real time. For example, the read address is transmitted back to the CPU in real time via an AXI-Lite bus.

[0030] For example, before each data transmission cycle, the FPGA reads the configuration register and sequentially reads and transmits data from five buffers according to the data transmission ratio. The total number of data ratios can be 50, meaning the FPGA transmits 50 frames of data per cycle. Each data ratio is at least 1 and at most 46, ensuring that at least one frame of each data type can be transmitted within one cycle.

[0031] Based on the above description, the FPGA in this embodiment includes CPU access control logic, registers, SRAM access arbitration logic, SRAM access control logic, NAND FLASH access control logic, and RS422 interface control logic. Please refer to [link / reference needed]. Figure 2 ; The CPU access control logic is used to map the CPU address to the SRAM and FPGA internal register storage space, and to achieve timing matching between the SRAM access arbitration logic and the CPU access control logic. SRAM access control logic is used for timing control of SRAM read and write access; The NAND FLASH access control logic is used for timing control of NAND FLASH read and write access; The RS422 interface control logic is used for timing control of the RS422 output; the data transmission control logic is used for switching between high and low data transmission rates, as well as buffer allocation balancing control.

[0032] The registers include a control register and a status register. The control register is used to temporarily store and set the downlink ratio configuration of five types of data, as well as the address allocation of various caches in SRAM. The status register is used to characterize the current operating status of the system.

[0033] The RS422 interface circuit includes an RS422 level conversion chip and FPGA control logic. The FPGA control logic is used to control the reading, writing, and forwarding of SRAM data. The FPGA reads the buffer size and downlink data ratio configured by the CPU control algorithm, reads the data of each buffer in sequence according to the downlink data ratio, and sends it to the RS422 level conversion chip. The RS422 level conversion chip converts the TTL clock and data signals sent by the FPGA into RS422 differential levels before sending them out.

[0034] In this embodiment, the NAND FLASH includes three partitions: an engineering telemetry data area, a payload data area, and an image data area. The engineering telemetry data area stores engineering telemetry data generated by the CPU in real time; the payload data area stores payload data received by the system in real time; and the image data area stores image data received by the system. The FPGA automatically reads the NAND FLASH data according to the SRAM cache address and the NAND FLASH address specified by the spacecraft software, storing the data in the designated SRAM cache area. This semi-automatic data transfer at the underlying level enhances the flexibility of the spacecraft software application.

[0035] Please refer to Figure 3In this embodiment, the FPGA takes the ratio of five downlink data types (10:10:10:10:10) as an example to complete one cycle of downlink data transmission, which mainly includes the following steps: S1: The FPGA receives the real-time telemetry data of the entire satellite written by the CPU and writes it into the SRAM. S2: FPGA reads the downlink data ratio configured by the CPU or ground; S3: The FPGA reads the SRAM address space corresponding to the five types of data configured by the CPU or the ground. S4: According to the downlink data ratio, the FPGA reads 10 frames of data sequentially from the corresponding SRAM address space, and sends them while reading, until 50 frames of data are sent. S5: After a data transmission cycle is completed, an interrupt signal is generated to prompt the CPU that it can fill in the data to be sent next.

[0036] In summary, this space-based downlink data transmission system can autonomously modify the telemetry downlink data ratio in real time according to mission requirements while in orbit. It can also complete the onboard telemetry downlink data ratio through ground commands. The system will transmit data according to the downlink data configuration table configured by the satellite crew, achieving efficient utilization of downlink channel resources.

[0037] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A downlink data transmission system for space applications, characterized in that, include: CPU, FPGA, SRAM, NAND FLASH and RS422 interface circuitry; The RS422 interface circuit, the CPU, the SRAM, and the NAND FLASH are respectively connected to the FPGA; the NAND FLASH is used to store payload data, and the SRAM is used to cache payload data and various downlink data to be transmitted; The FPGA is used to control the reading, writing and forwarding of SRAM data. The FPGA reads the cache size and downlink data ratio configured by the CPU, reads the data of each cache in sequence according to the downlink data ratio, and sends the data transmission data and telemetry downlink data to the RS422 interface circuit together. The RS422 interface circuit converts the TTL clock and data signals sent by the FPGA into RS422 differential levels before sending them out.

2. The space downlink data transmission system as described in claim 1, characterized in that, The SRAM provides multiple data cache areas for the FPGA. The capacity of each cache area is independently set by the CPU in 1 KB granularity between 2 KB and 312 KB, and the sum of the capacities of the cache areas does not exceed a preset value.

3. The space downlink data transmission system as described in claim 2, characterized in that, The CPU includes: a cache partitioning module, used to write capacity settings into multiple address registers provided by the FPGA to partition corresponding cache areas in the SRAM; a matching configuration module, used to write downlink data matching information into the matching control register of the FPGA, wherein the matching information is in units of frames; and a data write-back module, used to pre-write the data to be sent into the corresponding cache area according to the read cache address fed back by the FPGA in real time, so as to ensure the frame continuity of each type of data.

4. The space downlink data transmission system as described in claim 3, characterized in that, The FPGA includes: a ratio reading module, used to read the ratio control register at the beginning of each transmission cycle to determine the number of frames to be read sequentially from the multiple buffers; a data reading module, used to read cached data from the multiple buffers sequentially in units of frames according to the ratio information and transmit it downlink; and an address feedback module, used to provide the CPU with the read address of the buffer currently being read in real time.

5. The space downlink data transmission system as described in claim 3, characterized in that, The ratio control register consists of five 32-bit registers, each corresponding to the first to fifth buffers in the SRAM. The value in each register represents the number of frames to be sent in the corresponding buffer during the current transmission cycle.

6. The space downlink data transmission system as described in claim 3, characterized in that, The data write-back module writes the next batch of data to be sent to a subsequent address in the buffer before the read address reaches the end of the corresponding buffer, in order to avoid data interruption.

7. The space downlink data transmission system as described in claim 3, characterized in that, The CPU further includes a monitoring module for periodically reading the read pointer and write pointer provided by the FPGA to monitor the empty / full status of each cache area in real time.

8. The space downlink data transmission system as described in claim 1, characterized in that, The FPGA includes CPU access control logic, registers, SRAM access arbitration logic, SRAM access control logic, NAND FLASH access control logic, and RS422 interface control logic. The CPU access control logic is used to map the CPU address to the SRAM and the internal register storage space of the FPGA, and to achieve timing matching between the SRAM access arbitration logic and the CPU access control logic. The SRAM access control logic is used for timing control of SRAM read and write access; The NAND FLASH access control logic is used for timing control of read and write access to the NAND FLASH. The RS422 interface control logic is used for timing control of the RS422 output; the data transmission control logic is used for switching between high and low data transmission rates, as well as buffer allocation balancing control.

9. The space downlink data transmission system as described in claim 1, characterized in that, The SRAM includes six partitions: a fill frame buffer, an image data buffer, a payload data buffer, a delayed telemetry buffer, a real-time telemetry buffer, and other data buffers. The padding frame buffer is used as a buffer for sending padding frames during high-speed data downlink. The image data buffer is used to cache image data read by the FPGA from the NAND FLASH; The payload data buffer is used to cache payload data read by the FPGA from the NAND FLASH; The delayed telemetry buffer is used to cache delayed telemetry data read by the FPGA from the NAND FLASH; The real-time telemetry cache is used to cache engineering telemetry data generated by the CPU in real time. The other data cache area is used for data caching for other logic functions of the FPGA, as well as for cache expansion of temporary CPU data.

10. The space downlink data transmission system as described in claim 1, characterized in that, The NAND FLASH includes three partitions: engineering telemetry data area, payload data area, and image data area. The engineering telemetry data area is used to store engineering telemetry data generated by the CPU in real time. The load data area is used to store the load data received by the system in real time; The image data is used to store the image data received by the system.

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