Method, device and equipment for multi-resource division of field programmable gate array

Abstract

The invention relates to the technical field of field programmable gate array physical optimization, and discloses a field programmable gate array multi-resource division method, device and equipment, the method comprises the following steps: generating a hypergraph comprising vertexes and hyperedges based on a netlist, the hypergraph comprising one or more types of resources; carrying out first partition division on the hypergraph, and carrying out multi-level vertex combination; partitioning the hypergraph of the maximum merging hierarchy, dividing vertexes in the maximum merging hierarchy to each partition, and carrying out the following processing on the hypergraph of each hierarchy from the maximum merging hierarchy to the minimum merging hierarchy: moving a first vertex between the partitions in the target merging hierarchy, and meeting the multi-resource constraint of the partitions in the moving process; splitting the vertexes in the target merging hierarchy into the vertexes of the previous hierarchy of the target merging hierarchy; until a first hypergraph is obtained; moving a first vertex in the first hypergraph to obtain a first partitioning result; and carrying out partition division again until the position of each functional module is determined.

Description

Technical Field

[0001] This invention relates to the field of field-programmable gate array (FPGA) physical optimization technology, and more specifically to methods, apparatuses, and devices for multi-resource partitioning of FPGAs. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs), as a programmable hardware platform, are characterized by their versatility, flexibility, reconfigurability, and parallel computing capabilities. FPGAs can be programmed to reconfigure hardware logic circuits, making them suitable for different application scenarios and implementing specific digital logic functions.

[0003] As FPGA device size continues to increase and architectural complexity continues to rise, FPGAs have evolved into complex system-level platforms containing various heterogeneous resources, making traditional place-and-route methods difficult to handle. Therefore, the FPGA can be divided into multiple regions using a partitioning algorithm before place-and-route operations, thereby improving the efficiency and performance of place-and-route.

[0004] Partitioning algorithms in related technologies, such as the traditional Partition algorithm, can quickly and efficiently partition ultra-large-scale graphs. However, they can only independently partition and optimize single-type resources, such as logic units, DSP modules, or BRAM memory. They cannot consider the physical coupling relationship and synergistic effect between different types of resources, which can lead to some resources in a single partition being overcrowded while other resources are largely idle; low efficiency in the connection between dedicated computing modules and storage resources; and timing violations on critical paths due to long-distance wiring across resource types. Summary of the Invention

[0005] In view of this, the present invention provides a method, apparatus and device for multi-resource partitioning of field-programmable gate arrays, in order to solve the problem that partitioning algorithms in related technologies cannot take into account the physical coupling relationship and synergistic effect between different types of resources.

[0006] In a first aspect, the present invention provides a method for multi-resource partitioning of a field-programmable gate array (FPGA), the method comprising: generating a hypergraph based on a netlist, the hypergraph including vertices and hyperedges, the hypergraph including one or more types of resources; performing a first partitioning of the hypergraph and multi-level vertex merging to obtain vertices and merging levels in the maximum merging level; partitioning the hypergraph in the maximum merging level, assigning vertices in the hypergraph in the maximum merging level to each partition, and performing the following processing on each level of the hypergraph from the maximum merging level to the minimum merging level: obtaining the movement gain of the first vertex in each target merging level, and based on the movement gain, performing... Between partitions, the first vertex is moved, satisfying the multi-resource constraints of the partition during the movement; vertices in the target merging level are split into vertices of the level preceding the target merging level; until a first hypergraph with no merging vertices is obtained after processing, wherein the first vertex represents a movable vertex; the movement gain of the first vertex in the first hypergraph is obtained, and based on the movement gain of the first vertex in the first hypergraph, the first vertex in the first hypergraph is moved between the partitions to obtain the first partitioning result; based on the first partitioning result, the partitioning is performed again until the position of each vertex is determined, and the placement position of each functional module in the netlist is obtained.

[0007] In one optional implementation, the step of performing multi-level vertex merging to obtain the vertices in the maximum merging level and the merging level includes: in the target merging level, determining whether the number of vertices in the hypergraph meets a preset condition; if the number of vertices in the hypergraph meets the preset condition, calculating the similarity between the target vertex and other vertices, determining the second vertex among the other vertices with the highest similarity to the target vertex, and merging the target vertex with the second vertex; performing vertex merging at the next level until the number of vertices in the hypergraph no longer meets the preset condition, thereby obtaining the vertices in the maximum merging level and the merging level.

[0008] In one optional implementation, the first partitioning of the hypergraph includes: determining at least one physical partition based on preset design constraints, wherein the physical partition includes at least one resource; determining the weight of the vertex based on the type and quantity of resources contained in the vertex; and determining the upper limit of the vertex weight in the physical partition based on the type and quantity of resources contained in the physical partition.

[0009] In one optional implementation, merging the target vertex with the second vertex includes: adding the weights of corresponding type resources in the target vertex and the second vertex, determining the weight of the merged vertex based on the addition result, and modifying the connection relationship between the merged vertex and other vertices.

[0010] In one optional implementation, obtaining the movement gain of the first vertex in each of the target merging levels includes: determining the initial connection complexity of the hypergraph when the first vertex has not moved; determining the first connection complexity of the first vertex movement if the first vertex is moved from the first partition in the target merging level to the second partition in the target merging level; and determining the movement gain based on the difference between the initial connection complexity and the first connection complexity.

[0011] In an optional implementation, the aforementioned method for multi-resource partitioning of a field-programmable gate array further includes: determining the first vertex based on points in the target merging hierarchy that have not been moved and that satisfy the preset design constraints after being moved.

[0012] In one optional implementation, generating a hypergraph based on a netlist includes: mapping each functional module in the netlist to a vertex in the hypergraph; and characterizing the signal connection relationship between the functional modules based on the hyperedges in the hypergraph, wherein the hyperedges connect two or more vertices.

[0013] Secondly, the present invention provides an apparatus for multi-resource partitioning of a field-programmable gate array, the apparatus comprising: The first module is used to generate a hypergraph based on a netlist, the hypergraph including vertices and hyperedges, and the hypergraph including one or more types of resources; The second module is used to perform the first partitioning of the hypergraph and to merge multiple levels of vertices to obtain the vertices and merging levels in the maximum merging level. The third module is used to partition the hypergraph of the maximum merging level, dividing the vertices in the hypergraph of the maximum merging level into various partitions. For each level of the hypergraph from the maximum merging level to the minimum merging level, the following processing is performed: obtaining the movement gain of the first vertex in each target merging level; based on the movement gain, moving the first vertex between the partitions, satisfying the multi-resource constraints of the partition during the movement; splitting the vertices in the target merging level into vertices of the level preceding the target merging level; until a first hypergraph with no merging vertices is obtained after processing, wherein the first vertex represents a movable vertex; The fourth module is used to obtain the movement gain of the first vertex in the first hypergraph, and based on the movement gain of the first vertex in the first hypergraph, to move the first vertex in the first hypergraph between the partitions to obtain the first partitioning result; The fifth module is used to perform the partitioning again based on the first partitioning result, until the position of each vertex is determined, and the placement position of each functional module in the netlist is obtained.

[0014] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method for multi-resource partitioning of a field-programmable gate array as described in the first aspect or any corresponding embodiment thereof.

[0015] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to perform the method for multi-resource partitioning of a field-programmable gate array as described in the first aspect or any corresponding embodiment thereof.

[0016] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the method for multi-resource partitioning of a field-programmable gate array (FPGA) according to the first aspect or any corresponding embodiment described above.

[0017] The method, apparatus, and device for multi-resource partitioning of field-programmable gate arrays provided in this embodiment fully consider the interconnection relationships between various resources when partitioning, merging vertices with closely connected signals into composite vertices to ensure they are assigned to the same partition. This reduces cross-region connections, significantly reduces global wiring length and Manhattan distance between different functional modules, and reduces the proportion of long-distance wiring in the overall wiring. At the same time, the reduction in global wiring length and the reduction in wiring trace length can reduce the occupation of interconnection resources in wiring, thereby reducing global congestion and dynamic power consumption in FPGA design and improving the overall performance of the chip system. In addition, by dynamically adjusting the assignment of the first vertex through motion gain, the rationality of the partitioning result can be guaranteed. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a method for multi-resource partitioning of a field-programmable gate array according to an embodiment of this application is shown. Figure 2 A flowchart illustrating a method for multi-resource partitioning of a field-programmable gate array according to an embodiment of this application is shown. Figure 3A schematic diagram of the structure of an apparatus for multi-resource partitioning of a field-programmable gate array according to an embodiment of this application is shown; Figure 4 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The partitioning algorithms used in related technologies can also lead to inefficient connections between dedicated computing modules, such as digital signal processing (DSPs), and storage resources, such as block random access memory (BRAM); and timing violations on critical paths due to long-distance routing across resource types. In FPGAs containing multiple resource types, partitioning nodes within the FPGA cannot be performed effectively.

[0022] This application provides a method, apparatus, and device for multi-resource partitioning of field-programmable gate arrays. The partitioning takes into account the mutual influence between various types of resources, thereby solving the problem of multi-resource collaborative optimization in partitioning algorithms in related technologies.

[0023] According to an embodiment of the present invention, a method embodiment for multi-resource partitioning of a field-programmable gate array is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0024] This embodiment provides a method for multi-resource partitioning of a field-programmable gate array (FPGA), which can be used in the aforementioned terminal devices, such as mobile phones, tablets, laptops, desktops, or servers. Figure 1 A flowchart illustrating a method for multi-resource partitioning of a field-programmable gate array according to an embodiment of this application is shown, such as... Figure 1 As shown, the process includes the following steps: Step S101: Generate a hypergraph based on the netlist. The hypergraph includes vertices and hyperedges, and includes one or more types of resources.

[0025] In this embodiment, a netlist, or connection list, is used to characterize the way digital circuit connections are described using basic logic gates. A hypergraph is used to characterize an effective tool for modeling complex circuit connections. A hypernode is used to characterize the smallest indivisible element in the hypergraph, which can be a logic unit (such as a register), module, or signal node in the circuit. The hypergraph can include at least one or more types of resources, such as look-up tables (LUTs), flip-flops (FFs), DSPs, and BRAMs.

[0026] In this step, after parsing the netlist file, the components in the circuit can be defined as vertices of the hypergraph, and the signal network can be used as hyperedges connecting multiple components.

[0027] Step S102: Perform the first partitioning of the hypergraph and merge multiple levels of vertices to obtain the vertices and merging levels in the maximum merging level.

[0028] In this step, based on preset design constraints, the hypergraph with multiple resource types is partitioned for the first time to obtain the initial partitioning results. Within each partition, a clustering algorithm can be used to merge vertices at multiple levels. During each level of vertex merging, one or more vertex merging operations can be performed. Through this progressive coarsening, a hypergraph with gradually increasing vertex granularity is generated.

[0029] Step S103: Partition the hypergraph of the maximum merging level, and divide the vertices in the hypergraph of the maximum merging level into each partition. For each level of the hypergraph from the maximum merging level to the minimum merging level, perform the following processing: obtain the movement gain of the first vertex in each target merging level, and based on the movement gain, move the first vertex between partitions, satisfying the multi-resource constraints of the partitions during the movement; split the vertices in the target merging level into vertices of the level before the target merging level; until a first hypergraph with no merging vertices is obtained after processing, wherein the first vertex represents the movable vertex.

[0030] In this step, the movement gain characterizes the reduction in connection complexity (cutSize) when the first vertex moves from the current partition to another partition. If the cutSize of the target first vertex before moving is 'a', and the cutSize after moving to another partition is 'b', then the movement gain of the target first vertex is 'ab'. Merging hypergraphs does not affect the size of partitions, or the types and quantities of resources they can hold.

[0031] A partitioning algorithm can be used to divide the vertices in the maximum merging level into various partitions. During the partitioning process, a multi-resource constraint applies to each partition: the sum of the number of resources of any type for all vertices in each partition cannot exceed the resource quantity constraint of that partition. Starting from the maximum merging level and proceeding downwards, the following processing is performed until the minimum merging level is reached: calculate the movement gain of each first vertex, obtain the first vertices with movement gains greater than zero, and sort the movement gains greater than zero in descending order; based on the sorting order, move each first vertex. This achieves partition optimization at the current processing level.

[0032] The optimized current-level vertices are then uncoarsed into finer-grained vertices from the previous level. This process of moving the first vertex in each merging level is repeated until the smallest merging level is reached, resulting in a first hypergraph without merged vertices, i.e., the original granular hypergraph. The number of vertices in the first hypergraph is the same as the number of vertices before the multi-level vertex merging.

[0033] Step S104: Obtain the movement gain of the first vertex in the first hypergraph. Based on the movement gain of the first vertex in the first hypergraph, move the first vertex in the first hypergraph between partitions to obtain the first partition result.

[0034] In this step, the movement gain for each first vertex is calculated. Based on the movement gain, the first vertices are moved to the target partition, reducing the connection complexity of this partition.

[0035] Step S105: Based on the first partitioning result, perform partitioning again until the position of each vertex is determined, and obtain the placement position of each functional module in the netlist.

[0036] In this step, since a single partitioning is insufficient to fully meet the multi-resource optimization requirements of the FPGA, a second partitioning can be performed based on the first partitioning result to obtain the second partitioning result; based on the second partitioning result, a third partitioning can be performed to obtain the third partitioning result, and the aforementioned iterative partitioning process is repeated until the position of all vertices is determined to obtain the target hypergraph, which is the final multi-resource partitioning scheme.

[0037] Specifically, if the first partitioning result determines the nodes in the upper half and lower half of the hypergraph, then the second partitioning, based on the first partitioning result, determines the nodes in the left and right halves of the upper half of the hypergraph. The third partitioning, based on the second partitioning result, determines the nodes in the left and right halves of the lower half of the hypergraph. The above is merely an illustrative explanation of partitioning.

[0038] Compared to partitioning methods in related technologies that can only partition single resources, the multi-resource partitioning method for FPGAs provided in this embodiment fully considers the interconnection relationships between various resources during partitioning. It merges vertices with closely connected signals into composite vertices, ensuring they are assigned to the same partition. This enables multi-resource collaborative partitioning, reducing cross-region connections, significantly decreasing global routing length and Manhattan distance between different functional modules, and reducing the proportion of long-distance routing in the overall routing. Simultaneously, the reduced global routing length and trace length decrease the occupation of interconnection resources during routing, thereby reducing global congestion and dynamic power consumption in FPGA design, improving FPGA layout partitioning quality, and ultimately enhancing the overall performance of the chip system. Furthermore, by dynamically adjusting the first vertex assignment through gain shifting, the rationality of the partitioning result can be guaranteed.

[0039] This embodiment provides a method for multi-resource partitioning of field-programmable gate arrays (FPGAs), which can be used in the aforementioned terminal devices, such as mobile phones and tablets. Figure 2 A flowchart illustrating a method for multi-resource partitioning of a field-programmable gate array according to an embodiment of this application is shown, such as... Figure 2 As shown, the process includes the following steps: Step S201: Generate a hypergraph based on the netlist. The hypergraph includes vertices and hyperedges, and contains one or more types of resources. See details below. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0040] Step S202: Perform the first partitioning of the hypergraph and multi-level vertex merging (Coarseing) to obtain the vertices and merging levels in the maximum merging level.

[0041] Specifically, step S202 includes: Step S2021: In the target merging level, determine whether the number of vertices in the hypergraph meets the preset conditions.

[0042] In this step, the preset condition can be configured so that the number of vertices in the hypergraph is greater than or equal to a preset number. The preset number can be set to 100 or 200, etc. At each merging level, if the number of vertices in the hypergraph is greater than or equal to the preset number, the vertices in the hypergraph are merged. If the number of vertices in the hypergraph is less than the preset number, the vertices in the hypergraph are not merged.

[0043] Step S2022: If the number of vertices in the hypergraph meets the preset conditions, calculate the similarity between the target vertex and other vertices, determine the second vertex with the highest similarity to the target vertex among the other vertices, and merge the target vertex with the second vertex.

[0044] In this step, if the number of vertices in the hypergraph is greater than or equal to a preset number, the similarity between vertices is calculated, and the target vertex is merged with the vertex with the highest similarity to obtain a composite vertex. If, in the same vertex merging round, the target vertex is the vertex with the highest similarity to a certain vertex, that vertex is merged with the composite vertex.

[0045] Specifically, the similarity between vertices in each partition is calculated. Then, a clustering algorithm is used to merge highly interconnected vertices into virtual composite vertices and merge connected hyperedges. For example, if vertex U is the vertex with the highest similarity to vertex V in the current partition, vertex U and vertex V can be merged. Simultaneously, all hyperedges connecting vertex U can be changed to connect to vertex V.

[0046] Step S2023: Perform vertex merging at the next level until the number of vertices in the hypergraph does not meet the preset condition, and obtain the vertices and merging level in the maximum merging level.

[0047] In this step, if the number of vertices in the hypergraph is 1000 and the preset condition is 200, it is determined whether the number of vertices in the hypergraph meets the preset condition, that is, whether 1000 is greater than or equal to 200. If 1000 is greater than 200, the first level of aggregation is performed, merging each vertex with the vertex with the highest similarity to it, to obtain the result of the first level of vertex merging. It is assumed that the number of vertices after the first level of vertex merging is 500.

[0048] Determine if the number of vertices in the hypergraph after the first-level aggregation is greater than or equal to 200. If 500 is greater than 200, perform the second-level aggregation, merging each vertex with the vertex with the highest similarity to it, to obtain the result of the second-level vertex merging. Assume that the number of vertices after the second-level vertex merging is 300.

[0049] Determine if the number of vertices in the hypergraph after the second-level aggregation is greater than or equal to 200. If 300 is greater than 200, perform the third-level aggregation, merging each vertex with the vertex with the highest similarity to it, to obtain the result of the third-level vertex merging. Assume that the number of vertices after the third-level vertex merging is 150.

[0050] Determine if the number of vertices in the hypergraph after the third-level aggregation is greater than or equal to 200. If 150 is less than 200, that is, the number of vertices in the hypergraph does not meet the preset condition, then obtain 150 vertices in the maximum merging level and the merging level is three.

[0051] The subsequent processing involves each level of the hypergraph from the maximum to the minimum merging level. This could involve partitioning the vertices in the third-level aggregated hypergraph, identifying the first vertex (the free vertex) within it, and calculating the movement gain for each first vertex. If the movement gain is greater than zero, the first vertices are moved from largest to smallest based on their movement gain. After the first vertices are moved, the vertices in the third-level aggregated hypergraph are split into vertices in the second-level aggregated hypergraph. This movement and splitting process is repeated at different merging levels until the original granularity of the hypergraph is reached.

[0052] In this way, by merging vertices at multiple levels, a coarse-grained hypergraph with a number of vertices that meets the preset requirements can be obtained for subsequent resource partitioning.

[0053] Step S203: Partition the hypergraph of the maximum merge level, dividing the vertices in the hypergraph of the maximum merge level into various partitions. For each level of the hypergraph from the maximum merge level to the minimum merge level, perform the following processing: Obtain the movement gain of the first vertex in each target merge level; based on the movement gain, move the first vertex between partitions, satisfying the multi-resource constraints of the partitions during the movement; split the vertices in the target merge level into vertices of the level preceding the target merge level; until a first hypergraph without merging vertices is obtained after processing, where the first vertex represents a movable vertex. For details, please refer to [link to details]. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0054] Step S204: Obtain the movement gain of the first vertex in the first hypergraph. Based on the movement gain of the first vertex in the first hypergraph, move the first vertex in the first hypergraph between partitions to obtain the first partitioning result. See details below. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0055] Step S205: Based on the results of the first partitioning, perform partitioning again until the position of each vertex is determined, thus obtaining the placement position of each functional module in the netlist. For details, please refer to [link to details]. Figure 1 Step S105 of the illustrated embodiment will not be described again here.

[0056] In this way, the controllability of the merging process can be guaranteed by setting preset conditions; at the same time, merging vertices with high similarity, that is, placing specific functional units and related logic nearby, can significantly reduce the global wiring length and Manhattan distance between different units, reducing redundancy and conflicts after merging; in addition, while reducing the complexity of the hypergraph, key connection relationships can be preserved, improving the efficiency of subsequent partitioning algorithms.

[0057] In some optional implementations, step S2022 above includes: Step a1: Add the weights of the corresponding resource types in the target vertex and the second vertex, and determine the weights of the merged vertices based on the addition result.

[0058] In this step, if there are three types of resources in the current partition, and vertex U is the vertex with the highest similarity to vertex V, with a weight of [1,1,0] and a weight of [1,0,3] for vertex V, then the weight of the composite vertex obtained after merging is [2,1,3]. If, in the current vertex merging round, vertex U is still the vertex with the highest similarity to vertex X, with a weight of [2,2,2] for vertex X, then vertex X can be merged with the composite vertex, and the weight of the composite vertex obtained after merging is [4,3,5].

[0059] Step a2: Modify the connection relationship between the merged vertex and other vertices.

[0060] In this step, the hyperedges connecting the vertices before merging are modified to connect the vertices before merging.

[0061] In this way, by summing the resource weights to represent the total resource requirements for merging vertices, resource calculation errors during vertex merging can be avoided. In addition, by modifying the connection relationships, the hypergraph structure can be simplified, key signal paths can be preserved, and partitioning efficiency can be improved.

[0062] In some optional implementations, the hypergraph is first partitioned, including: determining at least one physical partition based on preset design constraints, wherein the physical partition includes at least one resource; determining the weight of a vertex based on the type and quantity of resources contained in the vertex; and determining the upper limit of the vertex weight in the physical partition based on the type and quantity of resources contained in the physical partition.

[0063] In this embodiment, the preset design constraints can be user-defined layout plans or partitioning schemes automatically generated by the tool. Based on the preset design constraints, the hypergraph is divided into multiple physical partitions. The area information of the physical partitions includes: the coordinate range of the partition and the resource configuration within the partition. The resource configuration within the partition includes: the types of resources that can be placed, and the number of resources corresponding to the types of resources that can be placed. Each physical partition can contain one or more types of resources. The types of resources that can be placed can be logical resources, including but not limited to LUTs, FFs, DSPs, and BRAMs.

[0064] Each vertex in a hypergraph can have multiple weights. The number of weights can be determined based on the types of resources in the physical partition. The value of each weight can be determined based on the quantity of each type of resource in the physical partition.

[0065] Specifically, if the resource types that can be placed in a certain physical partition are LUT and FF, and the functional module corresponding to a certain vertex includes a LUT and a FF, then the weight of that vertex can be configured as [1, 1].

[0066] The preset design constraints also include constraints on the number of resources in the target physical partition. Based on these preset design constraints, the upper limit of resource usage for each physical partition can be limited, and the various resources of each physical partition cannot exceed the preset design constraints.

[0067] Specifically, if the upper limit of LUT resources in the target physical partition is 50 and the upper limit of BRAM resources is 20, then the sum of the LUT resource weights corresponding to all vertices in the target physical partition cannot exceed 50, and the sum of the BRAM resource weights corresponding to all vertices cannot exceed 20.

[0068] This approach can proactively avoid physical resource conflicts and ensure that partitioning complies with underlying hardware limitations. At the same time, quantifying the resource requirements of vertices can provide a precise basis for optimizing partitioning algorithms. Furthermore, it can improve the efficiency and determinism of large-scale circuit partitioning and reduce iteration costs.

[0069] In some optional implementations, obtaining the movement gain of the first vertex in each target merging level includes: determining the initial connectivity complexity of the hypergraph when the first vertex is not moved; determining the first connectivity complexity of the first vertex movement if the first vertex is moved from the first partition in the target merging level to the second partition in the target merging level; and determining the movement gain based on the difference between the initial connectivity complexity and the first connectivity complexity.

[0070] In this embodiment, the connectivity complexity of the hypergraph can be used to characterize the degree of hyperedge severance. When vertices on the same hyperedge are assigned to different partitions, the hyperedge is severed. The severance of hyperedges under the current partitioning state is analyzed, the movement of vertices in each partition is simulated, and the connectivity state of the affected hyperedges after the vertex movement is recalculated. Based on the hypergraph connectivity complexity before the first vertex moves, the hypergraph connectivity complexity after the first vertex moves is subtracted to obtain the movement gain of the first vertex.

[0071] Specifically, each partition corresponds to two partitions. Traverse each hyperedge in the hypergraph. If the vertices in the hyperedge are not in one partition, that is, the hyperedge connects two partitions, the connection complexity will increase the weight of the hyperedge.

[0072] This reduces the complexity of the hypergraph connections, which can improve routing delay and enhance FPGA performance.

[0073] In some alternative implementations, the aforementioned method for FPGA multi-resource partitioning further includes: determining a first vertex based on points in the target merging hierarchy that have not been moved and that satisfy preset design constraints after being moved.

[0074] In this embodiment, the first vertex is used to represent a vertex that has not been moved in the current merging level and, if moved to the target physical partition, still satisfies the preset design constraints of the target physical partition. If the FPGA includes LUT resources and DSP resources, the resource weight of vertex A is [2,3]. If vertex A is moved to the target physical partition R, the upper limit of the resources of the target physical partition R is [10,10], and the sum of the resource weights of the existing vertices in the target physical partition R is [6,8]. After vertex A is moved to the target physical partition R, the sum of the resource weights of the target physical partition R is [8,11]. Although vertex A satisfies the LUT resource constraints after being moved, it does not satisfy the DSP resource constraints, so vertex A is not the first vertex, i.e., a free vertex.

[0075] After the first vertex moves, the movement gain of the remaining first vertices needs to be updated.

[0076] In this way, by determining the first vertex, invalid moves and resource conflicts can be avoided; at the same time, the targeting and efficiency of partition adjustments can be improved.

[0077] In some alternative implementations, generating a hypergraph based on a netlist includes: mapping each functional module in the netlist to a vertex in the hypergraph; and characterizing the signal connection relationships between functional modules based on hyperedges in the hypergraph, wherein a hyperedge connects two or more vertices.

[0078] In this embodiment, the functional modules in the netlist can be units that implement specific circuit functions in the logic or physical design. Examples include LUTs, FFs, or BRAMs. The functional modules in the netlist are mapped to vertices in a hypergraph, where each vertex represents an independent functional unit or hierarchical module. The signal connections between functional modules can be converted into hyperedges in the hypergraph. Each hyperedge can connect multiple vertices, which can better describe the connections of multi-terminal signals or complex logic blocks, thus accurately describing complex interconnect topologies.

[0079] In this way, the one-to-many or many-to-one signal connections between multiple modules can be accurately characterized, effectively avoiding information redundancy or loss.

[0080] This embodiment also provides a device for multi-resource partitioning of a field-programmable gate array (FPGA). This device is used to implement the above embodiments and preferred embodiments, and details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0081] This embodiment provides a device for multi-resource partitioning of a field-programmable gate array (FPGA). Figure 3 A schematic diagram of a device for multi-resource partitioning of a field-programmable gate array (FPGA) according to an embodiment of this application is shown, such as... Figure 3 As shown, it includes: The first module 301 is used to generate a hypergraph based on a netlist. The hypergraph includes vertices and hyperedges, and includes one or more types of resources.

[0082] The second module 302 is used to perform the first partitioning of the hypergraph and to merge multiple levels of vertices to obtain the vertices and merging levels in the maximum merging level.

[0083] The third module 303 is used to partition the hypergraph of the maximum merging level, dividing the vertices in the hypergraph of the maximum merging level into various partitions. For each level of the hypergraph from the maximum merging level to the minimum merging level, the following processing is performed: obtaining the movement gain of the first vertex in each target merging level; based on the movement gain, moving the first vertex between partitions, satisfying the multi-resource constraints of the partitions during the movement; splitting the vertices in the target merging level into vertices of the level before the target merging level; until a first hypergraph with no merging vertices is obtained after processing, wherein the first vertex represents the movable vertex.

[0084] The fourth module 304 is used to obtain the movement gain of the first vertex in the first hypergraph. Based on the movement gain of the first vertex in the first hypergraph, the first vertex in the first hypergraph is moved between partitions to obtain the first partition result.

[0085] The fifth module 305 is used to perform partitioning again based on the first partitioning result, until the position of each vertex is determined, and the placement position of each functional module in the netlist is obtained.

[0086] In some alternative implementations, the second module 302 includes: The first unit of the second module is used to determine whether the number of vertices in the hypergraph meets the preset conditions in the target merging level; if the number of vertices in the hypergraph meets the preset conditions, the similarity between the target vertex and other vertices is calculated, the second vertex with the highest similarity to the target vertex is determined among the other vertices, and the target vertex is merged with the second vertex; the next level of vertex merging is carried out until the number of vertices in the hypergraph does not meet the preset conditions, and the vertices and merging level in the maximum merging level are obtained.

[0087] In some alternative implementations, the second module 302 further includes: The second module, second unit, is used to determine at least one physical partition based on preset design constraints, wherein the physical partition includes at least one resource; to determine the weight of a vertex based on the type and quantity of resources contained in the vertex; and to determine the upper limit of the vertex weight in the physical partition based on the type and quantity of resources contained in the physical partition.

[0088] In some alternative implementations, the second module, second unit, includes: The second module, second unit subunit, is used to add the weights of the target vertex and the corresponding type of resources in the second vertex, determine the weight of the merged vertex based on the addition result, and modify the connection relationship between the merged vertex and other vertices.

[0089] In some alternative implementations, the third module 303 includes: The first unit of the third module is used to determine the initial connectivity complexity of the hypergraph when the first vertex has not been moved; if the first vertex is moved from the first partition in the target merging level to the second partition in the target merging level, the first connectivity complexity of the first vertex movement is determined; and the movement gain is determined based on the difference between the initial connectivity complexity and the first connectivity complexity.

[0090] In some alternative implementations, the aforementioned apparatus for multi-resource partitioning of a field-programmable gate array further includes: The sixth module is used to determine the first vertex based on the points in the target merging hierarchy that have not been moved, and the points that satisfy the preset design constraints after being moved.

[0091] In some alternative implementations, the first module 301 includes: The first module, first unit, is used to map each functional module in the netlist to a vertex in the hypergraph; based on the hyperedges in the hypergraph, the signal connection relationship between functional modules is represented, and the hyperedges connect two or more vertices.

[0092] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0093] In this embodiment, the device for multi-resource partitioning of field-programmable gate arrays is presented in the form of functional units. Here, a unit refers to an application-specific integrated circuit (ASIC) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0094] This invention also provides a computer device having the above-described features. Figure 3 The device shown is for multi-resource partitioning of a field-programmable gate array.

[0095] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 4 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a graphical user interface on an external input / output device (such as a display device coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4 Take a processor 10 as an example.

[0096] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0097] The aforementioned memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0098] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0099] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0100] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0101] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., light-emitting diodes), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0102] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0103] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0104] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for multi-resource partitioning of a field-programmable gate array (FPGA), characterized in that, The method includes: Generate a hypergraph based on a netlist, wherein the hypergraph includes vertices and hyperedges, and the hypergraph includes one or more types of resources; The hypergraph is partitioned for the first time, and multi-level vertex merging is performed to obtain the vertices and merging levels in the maximum merging level; The hypergraph of the maximum merging level is partitioned, and the vertices in the hypergraph of the maximum merging level are divided into various partitions. For each level of the hypergraph from the maximum merging level to the minimum merging level, the following processing is performed: the movement gain of the first vertex in each target merging level is obtained; based on the movement gain, the first vertex is moved between the partitions, satisfying the multi-resource constraints of the partition during the movement; the vertices in the target merging level are split into vertices of the level preceding the target merging level; until a first hypergraph with no merging vertices is obtained after processing, wherein the first vertex represents a movable vertex; Obtain the movement gain of the first vertex in the first hypergraph. Based on the movement gain of the first vertex in the first hypergraph, move the first vertex in the first hypergraph between the partitions to obtain the first partitioning result. Based on the first partitioning result, the partitioning is performed again until the position of each vertex is determined, thus obtaining the placement position of each functional module in the netlist.

2. The method according to claim 1, characterized in that, The process of merging multiple levels of vertices to obtain the vertices and merging levels at the maximum merging level includes: In the target merging level, it is determined whether the number of vertices in the hypergraph meets a preset condition; If the number of vertices in the hypergraph meets a preset condition, the similarity between the target vertex and other vertices is calculated, the second vertex with the highest similarity to the target vertex among the other vertices is determined, and the target vertex and the second vertex are merged. The process continues until the number of vertices in the hypergraph no longer meets the preset condition, thus obtaining the vertices in the maximum merging level and the merging level.

3. The method according to claim 1, characterized in that, The generation of a hypergraph based on a netlist includes: Map each functional module in the netlist to a vertex in the hypergraph; The hyperedges in the hypergraph represent the signal connection relationships between the functional modules, and the hyperedges connect two or more vertices.

4. The method according to claim 2, characterized in that, The first partitioning of the hypergraph includes: Based on preset design constraints, at least one physical partition is determined, wherein the physical partition includes at least one resource; The weight of a vertex is determined based on the types and quantities of resources it contains. Based on the types and quantities of resources contained in the physical partition, the upper limit of vertex weight in the physical partition is determined.

5. The method according to claim 4, characterized in that, The step of merging the target vertex with the second vertex includes: The weights of the target vertex and the corresponding type of resources in the second vertex are added together, and the weights of the merging vertices are determined based on the addition result. Modify the connection relationship between the merged vertex and other vertices.

6. The method according to claim 1, characterized in that, The step of obtaining the movement gain of the first vertex in each of the target merging levels includes: Determine the initial connection complexity of the hypergraph if the first vertex has not moved; If the first vertex is moved from the first partition in the target merging hierarchy to the second partition in the target merging hierarchy, the first connection complexity of the first vertex movement is determined. The mobility gain is determined based on the difference between the initial connection complexity and the first connection complexity.

7. The method according to claim 4, characterized in that, The method further includes: The first vertex is determined based on the points that have not been moved in the target merging hierarchy and those that satisfy the preset design constraints after being moved.

8. A device for multi-resource partitioning of a field-programmable gate array, characterized in that, The device includes: The first module is used to generate a hypergraph based on a netlist, the hypergraph including vertices and hyperedges, and the hypergraph including one or more types of resources; The second module is used to perform the first partitioning of the hypergraph and to merge multiple levels of vertices to obtain the vertices and merging levels in the maximum merging level. The third module is used to partition the hypergraph of the maximum merging level, dividing the vertices in the hypergraph of the maximum merging level into various partitions. For each level of the hypergraph from the maximum merging level to the minimum merging level, the following processing is performed: obtaining the movement gain of the first vertex in each target merging level; based on the movement gain, moving the first vertex between the partitions, satisfying the multi-resource constraints of the partition during the movement; splitting the vertices in the target merging level into vertices of the level preceding the target merging level; until a first hypergraph with no merging vertices is obtained after processing, wherein the first vertex represents a movable vertex; The fourth module is used to obtain the movement gain of the first vertex in the first hypergraph, and based on the movement gain of the first vertex in the first hypergraph, to move the first vertex in the first hypergraph between the partitions to obtain the first partitioning result; The fifth module is used to perform the partitioning again based on the first partitioning result, until the position of each vertex is determined, and the placement position of each functional module in the netlist is obtained.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the method for multi-resource partitioning of a field-programmable gate array as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method for multi-resource partitioning of a field-programmable gate array as described in any one of claims 1 to 7.

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