Charge pump, phase-locked loop and DCDC converter

Abstract

The invention discloses a charge pump, a phase-locked loop and a DCDC converter. The charge pump comprises a first upper current source, a first lower current source, a first switch group, a charging and discharging unit, a control unit, a first current generation unit and a second current generation unit. The charging and discharging unit detects the frequency of a reference clock signal in real time in a charging and discharging mode, and the control unit generates a corresponding control signal based on frequency detection so as to control the first current generation unit and the second current generation unit to change the current of the charge pump. According to the charge pump, the phase-locked loop and the DCDC converter provided by the invention, the phase difference between the reference clock signal and the switch clock signal under the high frequency of the reference clock signal is reduced while the loop stability under the low frequency of the reference clock signal is ensured, the frequency establishment stabilization time is reduced, and the performance of the phase-locked loop is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a charge pump, a phase-locked loop and a DCDC converter. BACKGROUND

[0002] In a switching power supply, sometimes a phase-locked loop containing a charge pump is used to synchronize an external reference clock signal to generate a switching clock signal, and the system has certain requirements for the phase difference between the switching clock signal and the reference clock signal. Since the input clock signal frequency usually varies from tens of kHz to several MHz, the phase-locked loop needs to synchronize the input clock signal in a wide input frequency range. When the loop filter of the phase-locked loop is implemented on-chip, in order to meet the loop stability requirement at a low input frequency under a small on-chip capacitance, the charge pump current of the phase-locked loop is usually small, and too small current will increase the influence of parasitic injected charge at a high input frequency, resulting in an increase in the phase difference between the reference clock signal and the switching clock signal, and also increasing the frequency establishment time.

[0003] The information disclosed in this Background section is only for the purpose of increasing the understanding of the general background of the application and should not be taken as an acknowledgement or any form of suggestion that this information forms prior art with regard to the natural person skilled in the art. SUMMARY

[0004] The application aims to provide a charge pump, a phase-locked loop and a DCDC converter, which can detect the frequency of a reference clock signal in real time, change the size of the charge pump current at different frequencies, and ensure the loop stability at a low frequency of the reference clock signal while reducing the phase difference between the reference clock signal and the switching clock signal at a high frequency of the reference clock signal and reducing the frequency establishment time.

[0005] To achieve the above-mentioned purpose, a specific embodiment of the application provides a technical solution as follows: a charge pump, comprising:

[0006] A first upper current source for injecting an upper current into an output end of the charge pump;

[0007] A first lower current source for extracting a lower current from the output end of the charge pump;

[0008] A first switch group for controlling the on-off between the first upper current source and the output end of the charge pump and the on-off between the first lower current source and the output end of the charge pump;

[0009] A charge and discharge unit for generating a characteristic signal based on the control of the reference clock signal;

[0010] A control unit for generating a corresponding control signal based on the size of the characteristic signal;

[0011] a first current generating unit for being turned on or off based on a control of a corresponding control signal and generating a first regulating current when being turned on, the first current generating unit being connected with the first upper current source to increase or decrease the current injected to the output terminal of the charge pump by the first regulating current cooperating with the first upper current source;

[0012] a second current generating unit for being turned on or off based on a control of a corresponding control signal and generating a second regulating current when being turned on, the second current generating unit being connected with the first lower current source to increase or decrease the current extracted from the output terminal of the charge pump by the second regulating current cooperating with the first lower current source.

[0013] In one or more embodiments of the present application, the charging and discharging unit comprises a pulse circuit and a charging and discharging module, the pulse circuit is used to convert the reference clock signal into a pulse signal, and the charging and discharging module is used to generate a characteristic signal based on the control of the pulse signal.

[0014] In one or more embodiments of the present application, the charging and discharging module comprises a current source, a first switch and a capacitor, a first end of the current source is connected with a first end of the capacitor and a first end of the first switch to output the characteristic signal, a second end of the capacitor and a second end of the first switch are connected with a reference voltage, and a control end of the first switch is used to receive the pulse signal.

[0015] In one or more embodiments of the present application, the control unit comprises a comparator and a logic unit, a first input end of the comparator is used to receive the characteristic signal, a second input end of the comparator is used to receive a reference voltage, the comparator is used to compare the characteristic signal with the reference voltage to generate a result signal, and the logic unit is used to generate a group of control signals based on the result signal to simultaneously turn on the first current generating unit and the second current generating unit or to simultaneously turn off the first current generating unit and the second current generating unit.

[0016] In one or more embodiments of the present application, the logic unit comprises a D flip-flop, a D input end of the D flip-flop is used to receive the result signal, a clock input end of the D flip-flop is used to receive the pulse signal or the reference clock signal, and a Q output end and a QN output end of the D flip-flop are used to output the group of control signals.

[0017] In one or more embodiments of the present application, the control unit further comprises a first switching unit, the first switching unit is connected with the second input end of the comparator and a first reference voltage and a second reference voltage, and the first switching unit is used to switch the second input end of the comparator to be connected with the first reference voltage or the second input end of the comparator to be connected with the second reference voltage based on the control of the group of control signals.

[0018] In one or more embodiments of the present invention, the first current generating unit includes a second switching unit and a second current source. A first terminal of the second current source is connected to a first terminal of the first current source, and a second terminal of the second current source is connected to a second terminal of the first current source. A control terminal of the second current source is connected to the second switching unit. The second switching unit is simultaneously connected to a first bias voltage and a power supply voltage. The second switching unit is used to switch the connection of the control terminal of the second current source to the first bias voltage or the connection of the control terminal of the second current source to the power supply voltage based on a set of control signals; and / or

[0019] The second current generating unit includes a third switching unit and a second lower current source. The first terminal of the second lower current source is connected to the first terminal of the first lower current source, and the second terminal of the second lower current source is connected to the second terminal of the first lower current source. The control terminal of the second lower current source is connected to the third switching unit. The third switching unit is simultaneously connected to a second bias voltage and a reference voltage. The third switching unit is used to switch the connection between the control terminal of the second lower current source and the second bias voltage or the control terminal of the second lower current source and the reference voltage based on a set of control signals.

[0020] In one or more embodiments of the present invention, the charge pump further includes a second switch group and an operational amplifier. The second switch group is connected to a first upper current source, a first lower current source, and a first input terminal of the operational amplifier. The second switch group is used to control the on / off connection between the first upper current source and the first input terminal of the operational amplifier, and the on / off connection between the first lower current source and the first input terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the first input terminal of the operational amplifier, and the second input terminal of the operational amplifier is connected to the output terminal of the charge pump; and / or

[0021] The charge pump also includes a virtual tube group, which is connected between the first switch group and the output terminal of the charge pump.

[0022] The present invention also discloses a phase-locked loop, comprising a frequency and phase detector connected together, the charge pump, the filter, and a voltage-controlled oscillator.

[0023] The present invention also discloses a DC-DC converter, including a dead time generation circuit, a drive circuit, and the phase-locked loop (PLL). The dead time generation circuit is connected to the PLL to receive the switching clock signal generated by the PLL and generate a drive signal. The drive circuit is connected to the dead time generation circuit to receive the drive signal.

[0024] Compared with existing technologies, the charge pump, phase-locked loop, and DC-DC converter of this invention detect the frequency of the reference clock signal in real time through a charging and discharging unit. The control unit generates corresponding control signals based on the frequency detection to control the first and second current generating units, thereby changing the magnitude of the charge pump current. This invention can implement the circuit function with a smaller area, ensuring loop stability at low frequencies of the reference clock signal while reducing the phase difference between the reference clock signal and the switching clock signal at high frequencies, reducing the frequency settling time, and improving the performance of the phase-locked loop. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a circuit diagram of a charge pump according to an embodiment of the present invention.

[0027] Figure 2 This is a circuit diagram of the charging / discharging unit and the control unit in one embodiment of the present invention.

[0028] Figure 3 This is a circuit diagram of the first current generating unit and the second current generating unit in one embodiment of the present invention.

[0029] Figure 4 This is a waveform diagram showing the changes of various signals of the charge pump with the frequency of the reference clock signal in one embodiment of the present invention.

[0030] Figure 5 This is a system diagram of a phase-locked loop and a DC-DC converter according to an embodiment of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0032] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0033] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0034] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0035] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0036] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0037] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0038] like Figure 1As shown, a charge pump according to one embodiment of the present invention includes: a first upper current source, a first lower current source, a first switch group, a virtual transistor group, a second switch group, an operational amplifier AMP, a charge / discharge unit, a control unit, a first current generating unit, and a second current generating unit.

[0039] The first upper current source is used to inject an upper current ICP_UP into the output terminal UP_OUT of the charge pump, the first lower current source is used to draw a lower current ICP_DN from the output terminal UP_OUT of the charge pump, and the first switch group is used to control the connection and disconnection between the first upper current source and the output terminal UP_OUT of the charge pump, as well as the connection and disconnection between the first lower current source and the output terminal UP_OUT of the charge pump.

[0040] The charging and discharging unit is used to generate a characterization signal VC by charging and discharging based on the reference clock signal CLK_IN; the control unit is used to generate a corresponding control signal based on the magnitude of the characterization signal VC.

[0041] The first current generating unit is used to turn on or off based on the control of the corresponding control signal, and generates a first regulating current I1 when it is turned on. The first current generating unit is connected to the first upper current source so that the first regulating current I1 cooperates with the first upper current source to increase or decrease the current injected into the output terminal UP_OUT of the charge pump.

[0042] The second current generating unit is used to turn on or off based on the control of the corresponding control signal, and generates a second regulating current I2 when it is turned on. The second current generating unit is connected to the first lower current source so that the second regulating current I2 cooperates with the first lower current source to increase or decrease the current drawn from the output terminal UP_OUT of the charge pump.

[0043] The second switch group is connected to the first upper current source, the first lower current source and the first input terminal of the operational amplifier AMP. The second switch group is used to control the on / off connection between the first upper current source and the first input terminal of the operational amplifier AMP, as well as the on / off connection between the first lower current source and the first input terminal of the operational amplifier AMP. The output terminal of the operational amplifier AMP is connected to the first input terminal of the operational amplifier AMP, and the second input terminal of the operational amplifier AMP is connected to the output terminal UP_OUT of the charge pump.

[0044] The second switch group is used to provide a bias branch to the first upper current source or the first lower current source when the first upper current source is disconnected from the output terminal UP_OUT of the charge pump or when the first lower current source is disconnected from the output terminal UP_OUT of the charge pump. This prevents a large charge injection into or from the output terminal UP_OUT from the output terminal due to voltage fluctuations when the first upper current source is connected to the output terminal UP_OUT of the charge pump or when the first lower current source is connected to the output terminal UP_OUT of the charge pump.

[0045] In one embodiment, the first input terminal of the operational amplifier AMP is a negative input terminal, and the second input terminal of the operational amplifier AMP is a positive input terminal. In other embodiments, the second input terminal of the operational amplifier AMP is a negative input terminal, and the first input terminal of the operational amplifier AMP is a positive input terminal.

[0046] The virtual transistor group is connected between the first switch group and the output terminal UP_OUT of the charge pump. The virtual transistor group is used to eliminate the channel charge injection effect of the transistor as much as possible.

[0047] Specifically, the first upper current source includes the first transistor PM1, the first lower current source includes the second transistor NM1, the first switch group includes the third transistor SWP1 and the fourth transistor SWN1, the virtual transistor group includes the fifth transistor DMP and the sixth transistor DMN, and the second switch group includes the seventh transistor SWP2 and the eighth transistor SWN2.

[0048] The first transistor PM1, the third transistor SWP1, the fifth transistor DMP, and the seventh transistor SWP2 are P-channel MOSFETs. The second transistor NM1, the fourth transistor SWN1, the sixth transistor DMN, and the eighth transistor SWN2 are N-channel MOSFETs. The first terminal of the first transistor PM1, the first terminal of the third transistor SWP1, the first terminal of the fifth transistor DMP, the first terminal of the seventh transistor SWP2, the first terminal of the second transistor NM1, the first terminal of the fourth transistor SWN1, the first terminal of the sixth transistor DMN, and the first terminal of the eighth transistor SWN2 are the sources. The second terminals of the first transistor PM1, the third transistor SWP1, the fifth transistor DMP, the seventh transistor SWP2, the second transistor NM1, the fourth transistor SWN1, the sixth transistor DMN, and the eighth transistor SWN2 are the drains. The control terminals of the first transistor PM1, the third transistor SWP1, the fifth transistor DMP, the seventh transistor SWP2, the second transistor NM1, the fourth transistor SWN1, the sixth transistor DMN, and the eighth transistor SWN2 are the gates.

[0049] The first terminal of the first transistor PM1 is connected to the power supply voltage AVCC. The control terminal of the first transistor PM1 is used to receive the first bias voltage PBIAS_CP. The second terminal of the first transistor PM1 is connected to the first current generation unit, the first terminal of the third transistor SWP1, and the first terminal of the seventh transistor SWP2. The second terminal of the third transistor SWP1 is connected to the first terminal of the fifth transistor DMP. The first terminal of the fifth transistor DMP is connected to the second terminal of the fifth transistor DMP. The second terminal of the fifth transistor DMP is connected to the second terminal of the sixth transistor DMN to form the output terminal UP_OUT of the charge pump. The second terminal of the sixth transistor DMN is connected to the first terminal of the sixth transistor DMN. The first terminal of the sixth transistor DMN is connected to the second terminal of the fourth transistor SWN1. The first terminal of the fourth transistor SWN1 is connected to the second current generation unit, the second terminal of the second transistor NM1, and the first terminal of the eighth transistor SWN2. The second terminal of the seventh transistor SWP2 is connected to the second terminal of the eighth transistor SWN2 and the first input terminal of the operational amplifier AMP. The first terminal of the second transistor NM1 is connected to the reference voltage. In one embodiment, the reference voltage is the ground voltage AGND. The control terminal of the second transistor NM1 is connected to the second bias voltage NBIAS_CP.

[0050] The control terminals of the fifth transistor DMP and the seventh transistor SWP2 receive the first control signal UP; the control terminal of the third transistor SWP1 receives the second control signal UPB; the control terminals of the sixth transistor DMN and the eighth transistor SWN2 receive the third control signal UNB; and the control terminal of the fourth transistor SWN1 receives the fourth control signal DN. The first control signal UP and the second control signal UPB are a pair of inverted signals, and the third control signal UNB and the fourth control signal DN are also a pair of inverted signals. The third transistor SWP1 and the fourth transistor SWN1 are alternately activated.

[0051] The seventh transistor, SWP2, provides a bias branch to the first upper current source when the third transistor, SWP1, is off. This prevents a large charge injection into the output terminal UP_OUT due to a sudden change in the drain voltage of the first transistor, PM1, when the third transistor, SWP1, is on. The eighth transistor, SWN2, provides a bias branch to the first lower current source when the fourth transistor, SWN1, is off. This prevents a large charge from being drawn from the output terminal UP_OUT due to a sudden change in the drain voltage of the second transistor, NM1, when the fourth transistor, SWN1, is on.

[0052] like Figure 2As shown, the charging / discharging unit includes a pulse circuit and a charging / discharging module. The pulse circuit converts the reference clock signal CLK_IN into a pulse signal ONESHOT. The charging / discharging module generates a characterization signal VC based on the control of the pulse signal ONESHOT. In one embodiment, the pulse circuit is a square wave to pulse circuit.

[0053] The charging and discharging module includes a current source A1, a first switch SW1, and a capacitor C1. The first terminal of the current source A1 is connected to the first terminal of the capacitor C1 and the first terminal of the first switch SW1 to output a characterization signal VC. The second terminal of the current source A1 is connected to the power supply voltage AVCC. The second terminal of the capacitor C1 and the second terminal of the first switch SW1 are connected to the reference voltage. The control terminal of the first switch SW1 is used to receive the pulse signal ONESHOT.

[0054] like Figure 2 As shown, the control unit includes a comparator CMP and a logic unit. The first input of the comparator CMP receives a characterization signal VC, and the second input receives a reference voltage. The comparator CMP compares the characterization signal VC with the reference voltage to generate a result signal DIN. The logic unit generates a set of control signals ICP_SEL and ICP_SELB based on the result signal DIN, simultaneously enabling and disabling the first and second current generation units. In one embodiment, the first input of the comparator CMP is a positive input, and the second input is a negative input. In other embodiments, the first input of the comparator CMP is a negative input, and the second input is a positive input.

[0055] In one embodiment, the logic unit includes a D flip-flop DC. The D input of the D flip-flop DC receives a result signal DIN, the clock input receives a pulse signal ONESHOT, the reset input SN receives a reset signal RSTN, and the Q and QN outputs of the D flip-flop DC output a set of inverted control signals ICP_SEL and ICP_SELB. In other embodiments, the clock input of the D flip-flop DC can receive a reference clock signal CLK_IN.

[0056] like Figure 2 As shown, in one embodiment, the control unit further includes a first switching unit, which is connected to the second input terminal of the comparator CMP and the first reference voltage VREFH and the second reference voltage VREFL. The first switching unit is used to switch the connection of the second input terminal of the comparator CMP to the first reference voltage or the connection of the second input terminal of the comparator CMP to the second reference voltage based on a set of control signals.

[0057] Specifically, the first switching unit includes a second switch SW2 and a third switch SW3. The first terminals of the second switch SW2 and the third switch SW3 are connected to the second input terminal of the comparator CMP. The second terminal of the second switch SW2 is connected to the first reference voltage VREFH, and the second terminal of the third switch SW3 is connected to the second reference voltage VREFL. The control terminal of the second switch SW2 receives the control signal ICP_SELB, and the control terminal of the third switch SW3 receives the control signal ICP_SEL. In one embodiment, the first reference voltage VREFH and the second reference voltage VREFL are voltage signals of different magnitudes, and the first reference voltage VREFH can be greater than the second reference voltage VREFL.

[0058] like Figure 3 As shown, the first current generating unit includes a second switching unit and a second current source. The first terminal of the second current source is connected to the first terminal of the first current source, and the second terminal of the second current source is connected to the second terminal of the first current source. The control terminal of the second current source is connected to the second switching unit. The second switching unit is simultaneously connected to the first bias voltage PBIAS_CP and the power supply voltage. The second switching unit is used to switch the connection between the control terminal of the second current source and the first bias voltage PBIAS_CP or the connection between the control terminal of the second current source and the power supply voltage based on a set of control signals.

[0059] Specifically, the second switching unit includes a fourth switch SW4 and a fifth switch SW5, and the second current source includes a ninth transistor PM2. The first terminals of the fourth switch SW4 and the fifth switch SW5 are connected to the control terminal of the ninth transistor PM2. The second terminal of the fourth switch SW4 is connected to the first bias voltage PBIAS_CP, and the second terminal of the fifth switch SW5 is connected to the power supply voltage AVCC. The control terminal of the fourth switch SW4 is used to receive the control signal ICP_SELB, and the control terminal of the fifth switch SW5 is used to receive the control signal ICP_SEL. The first terminal of the ninth transistor PM2 is connected to the power supply voltage AVCC, and the second terminal of the ninth transistor PM2 is used to output the first regulating current I1.

[0060] like Figure 3 As shown, the second current generating unit includes a third switching unit and a second lower current source. The first terminal of the second lower current source is connected to the first terminal of the first lower current source, and the second terminal of the second lower current source is connected to the second terminal of the first lower current source. The control terminal of the second lower current source is connected to the third switching unit. The third switching unit is simultaneously connected to the second bias voltage NBIAS_CP and the reference voltage. The third switching unit is used to switch the connection between the control terminal of the second lower current source and the second bias voltage NBIAS_CP or the connection between the control terminal of the second lower current source and the reference voltage based on a set of control signals.

[0061] Specifically, the second switching unit includes a sixth switch SW6 and a seventh switch SW7, and the second current source includes a tenth transistor NM2. The first terminals of the sixth switch SW6 and the seventh switch SW7 are connected to the control terminal of the tenth transistor NM2. The second terminal of the sixth switch SW6 is connected to a reference voltage, and the second terminal of the seventh switch SW7 is connected to a second bias voltage NBIAS_CP. The control terminal of the sixth switch SW6 is used to receive the control signal ICP_SEL, and the control terminal of the seventh switch SW7 is used to receive the control signal ICP_SELB. The first terminal of the tenth transistor NM2 is connected to the reference voltage, and the second terminal of the tenth transistor NM2 is used to draw the second regulating current I2.

[0062] The ninth transistor PM2 is a P-channel MOSFET. The tenth transistor NM2 is an N-channel MOSFET. The first terminal of the ninth transistor PM2 and the first terminal of the tenth transistor NM2 are the sources, the second terminal of the ninth transistor PM2 and the second terminal of the tenth transistor NM2 are the drains, and the control terminal of the ninth transistor PM2 and the control terminal of the tenth transistor NM2 are the gates.

[0063] Combination Figure 2 , Figure 3 and Figure 4 During the initial power-on phase, the DC flip-flop is reset via the reset signal RSTN, causing the control signal ICP_SEL to be high and the control signal ICP_SELB to be low. In this state, the third switch SW3 is turned on, the second switch SW2 is turned off, and the second reference voltage VREFL is connected to the negative input of the comparator CMP as a reference voltage signal. Simultaneously, the fifth switch SW5 and the sixth switch SW6 are turned on, and the fourth switch SW4 and the seventh switch SW7 are turned off. The gates of the ninth transistor PM2 and the tenth transistor NM2 are connected to the power supply voltage AVCC and the ground voltage AGND, respectively, so the ninth transistor PM2 and the tenth transistor NM2 are in a non-operating state. The gates of the first transistor PM1 and the second transistor NM1 are connected to the first bias voltage PBIAS_CP and the second bias voltage NBIAS_CP, respectively, which enable them to operate normally. The first transistor PM1 generates an upward current ICP_UP, and the second transistor NM1 generates a downward current ICP_DN. At this time, the charge pump current is in a low-current operating state.

[0064] When a reference clock signal CLK_IN is input, the pulse circuit first converts the reference clock signal CLK_IN into a high-level, nanosecond-level pulse signal ONESHOT at the same frequency. Simultaneously, current source A1 charges capacitor C1 at the frequency of the reference clock signal CLK_IN. When reset, during the charging cycle, the voltage across capacitor C1 (characterizing the signal VC) can be expressed as:

[0065]

[0066] The characterization signal VC is compared with the second reference voltage VREFL in real time, and the frequency of the reference clock signal CLK_IN is... When the voltage is small, the characterization signal VC is greater than the second reference voltage VREFL before being reset. The comparator CMP outputs a high-level result signal DIN. When the pulse signal ONESHOT arrives, since the D input of the D flip-flop DC receives the high-level result signal DIN, the Q output of the D flip-flop DC outputs a high-level control signal ICP_SEL and the QN output outputs a low-level control signal ICP_SELB. The charge pump current remains in a low-current operating state.

[0067] When the frequency of the reference clock signal CLK_IN When the voltage is increased, so that the characterization signal VC is always less than the second reference voltage VREFL before being reset, the comparator CMP outputs a low-level result signal DIN. When the pulse signal ONESHOT arrives, since the D input of the D flip-flop receives the low-level result signal DIN, the Q output of the D flip-flop DC outputs a low-level control signal ICP_SEL and the QN output outputs a high-level control signal ICP_SELB. At this time, the fifth switch SW5 and the sixth switch SW6 are open, the fourth switch SW4 and the seventh switch SW7 are open, and the gates of the ninth transistor PM2 and the tenth transistor NM2 are connected to the first bias voltage PBIAS_CP and the second bias voltage NBIAS_CP, respectively. The ninth transistor PM2 and the tenth transistor NM2 work normally, and the charge pump current increases.

[0068] At the same time, the third switch SW3 is open and the second switch SW2 is open. The first reference voltage VREFH is connected to the negative input terminal of the comparator CMP as a reference voltage signal, forming a frequency hysteresis. The output of the comparator CMP will only flip when the frequency of the reference clock signal CLK_IN is lower than the frequency corresponding to the first reference voltage VREFH, thus enhancing the robustness of the circuit.

[0069] Similarly, when the frequency of the reference clock signal CLK_IN changes from high to low, causing the output of the comparator CMP to change from low to high again, the negative input of the comparator CMP is reconnected to the second reference voltage VREFL as a reference signal. Therefore, the frequency of the reference clock signal CLK_IN needs to be higher than the frequency of the second reference voltage VREFL to flip, which also forms frequency hysteresis.

[0070] like Figure 5As shown, the present invention also discloses a phase-locked loop, including a frequency and phase detector connected together, a charge pump, a filter, and a voltage-controlled oscillator (VCO). The VCO outputs a switching clock signal CLK_OUT, and the frequency and phase detector generates a first control signal UP, a second control signal UPB, a third control signal UNB, and a fourth control signal DN based on a reference clock signal CLK_IN and a feedback signal output by the VCO.

[0071] The filter is used to filter the output signal of the charge pump. In one embodiment, the filter is a low-pass filter, including a first resistor Rp1, a first capacitor Cp1 and a second capacitor Cp2. The first end of the first resistor Rp1 and the first end of the second capacitor Cp2 are connected to the output terminal UP_OUT of the charge pump and the input terminal of the voltage-controlled oscillator. The second end of the first resistor Rp1 is connected to the first end of the first capacitor Cp1. The second end of the first capacitor Cp1 and the second end of the second capacitor Cp2 are connected to the ground voltage.

[0072] When the charge pump switching control signals output by the frequency and phase detector—first control signal UP, second control signal UPB, third control signal UNB, and fourth control signal DN—flip, due to the parasitic capacitance on the signal lines, charge flows through the parasitic capacitance between the gate and drain of the third transistor SWP1 and the fourth transistor SWN1. Coupled to the output terminal UP_OUT, the coupled charge Size can be represented as: U is the parasitic capacitance The voltage on it.

[0073] When comparing the phase of the reference clock signal CLK_IN with the switching clock signal CLK_OUT, excess charge needs to be compensated by the charge pump through additional turn-on time, resulting in phase error. It can be represented as: I CP This refers to the current of the charge pump;

[0074] The phase error caused by different reference clock signals CLK_IN can be expressed as:

[0075]

[0076] When the charge pump current is fixed, the frequency of the reference clock signal CLK_IN The larger the value, the greater the resulting phase error. Therefore, the phase error can be reduced by changing the magnitude of the charge pump current.

[0077] like Figure 5As shown, this invention also discloses a DC-DC converter, including a dead-time generation circuit, a driving circuit, and the aforementioned phase-locked loop (PLL). The dead-time generation circuit is connected to the PLL to receive the switching clock signal CLK_OUT generated by the PLL and generate a driving signal. The driving circuit is connected to the dead-time generation circuit to receive the driving signal. In one embodiment, the dead-time generation circuit uses the switching clock signal CLK_OUT as its operating clock signal to output a driving signal CLK_DRV_UG for the high-side switch driving of the driving circuit and a driving signal CLK_DRV_LG for the low-side switch driving of the driving circuit. In other embodiments, the aforementioned PLL can also be applied to other scenarios.

[0078] The present invention also discloses a chip comprising the above-described charge pump and / or phase-locked loop and / or DC-DC converter.

[0079] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0080] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A charge pump, characterized in that, include: The first current source is used to inject current into the output terminal of the charge pump; The first current source is used to draw current from the output of the charge pump. The first switch group is used to control the connection and disconnection between the first upper current source and the output terminal of the charge pump, and the connection and disconnection between the first lower current source and the output terminal of the charge pump. A charging / discharging unit is used to generate characterization signals based on a reference clock signal. The control unit is used to generate corresponding control signals based on the magnitude of the characterizing signal; The first current generating unit is used to turn on or off based on the control of a corresponding control signal and to generate a first regulating current when it is turned on. The first current generating unit is connected to a first upper current source so that the first regulating current cooperates with the first upper current source to increase or decrease the current injected into the output terminal of the charge pump. The second current generating unit is used to turn on or off based on the control of a corresponding control signal, and to generate a second regulating current when it is turned on. The second current generating unit is connected to the first lower current source so that the second regulating current cooperates with the first lower current source to increase or decrease the current drawn from the output terminal of the charge pump.

2. The charge pump according to claim 1, characterized in that, The charging and discharging unit includes a pulse circuit and a charging and discharging module. The pulse circuit is used to convert a reference clock signal into a pulse signal, and the charging and discharging module generates a characterization signal by charging and discharging based on the control of the pulse signal.

3. The charge pump according to claim 2, characterized in that, The charging and discharging module includes a current source, a first switch, and a capacitor. The first end of the current source is connected to the first end of the capacitor and the first end of the first switch to output a characterizing signal. The second end of the capacitor and the second end of the first switch are connected to a reference voltage. The control terminal of the first switch is used to receive pulse signals.

4. The charge pump according to claim 2, characterized in that, The control unit includes a comparator and a logic unit. The first input terminal of the comparator is used to receive a characterization signal, and the second input terminal of the comparator is used to receive a reference voltage. The comparator is used to compare the characterization signal with the reference voltage to generate a result signal. The logic unit generates a set of control signals based on the result signal to simultaneously turn on the first current generating unit and the second current generating unit and simultaneously turn off the first current generating unit and the second current generating unit.

5. The charge pump according to claim 4, characterized in that, The logic unit includes a D flip-flop, the D input of which is used to receive a result signal, the clock input of which is used to receive a pulse signal or a reference clock signal, and the Q output and QN output of which are used to output a set of control signals.

6. The charge pump according to claim 4, characterized in that, The control unit further includes a first switching unit, which is connected to the second input terminal of the comparator and the first reference voltage and the second reference voltage. The first switching unit is used to switch the connection between the second input terminal of the comparator and the first reference voltage or the connection between the second input terminal of the comparator and the second reference voltage based on a set of control signals.

7. The charge pump according to claim 1, characterized in that, The first current generating unit includes a second switching unit and a second current source. A first terminal of the second current source is connected to a first terminal of a first current source, and a second terminal of the second current source is connected to a second terminal of the first current source. A control terminal of the second current source is connected to the second switching unit. The second switching unit is simultaneously connected to a first bias voltage and a power supply voltage. The second switching unit is used to switch the connection between the control terminal of the second current source and the first bias voltage or the control terminal of the second current source and the power supply voltage based on a set of control signals; and / or The second current generating unit includes a third switching unit and a second lower current source. The first terminal of the second lower current source is connected to the first terminal of the first lower current source, and the second terminal of the second lower current source is connected to the second terminal of the first lower current source. The control terminal of the second lower current source is connected to the third switching unit. The third switching unit is simultaneously connected to a second bias voltage and a reference voltage. The third switching unit is used to switch the connection between the control terminal of the second lower current source and the second bias voltage or the control terminal of the second lower current source and the reference voltage based on a set of control signals.

8. The charge pump according to claim 1, characterized in that, The charge pump further includes a second switching group and an operational amplifier. The second switching group is connected to a first upper current source, a first lower current source, and a first input terminal of the operational amplifier. The second switching group is used to control the on / off connection between the first upper current source and the first input terminal of the operational amplifier, and the on / off connection between the first lower current source and the first input terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the first input terminal of the operational amplifier, and the second input terminal of the operational amplifier is connected to the output terminal of the charge pump; and / or The charge pump also includes a virtual tube group, which is connected between the first switch group and the output terminal of the charge pump.

9. A phase-locked loop, characterized in that, It includes a connected frequency and phase detector, a charge pump as described in any one of claims 1 to 8, a filter, and a voltage-controlled oscillator.

10. A DC-DC converter, characterized in that, It includes a dead time generation circuit, a drive circuit, and a phase-locked loop as described in claim 9. The dead time generation circuit is connected to the phase-locked loop to receive the switching clock signal generated by the phase-locked loop and generate a drive signal. The drive circuit is connected to the dead time generation circuit to receive the drive signal.

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