Simulation verification system and method supporting multiple verification scenarios

Abstract

The application discloses a simulation verification system and method supporting multiple verification scenes, and relates to the technical field of chip design verification.The system comprises: a unified verification environment, which is constructed based on the same verification methodology, is connected with design code through an interface, and provides test excitation; a mode configuration module, which is used for receiving user instructions, controls the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate level simulation mode and gate level post-simulation mode with timing reverse markers, and realizes mode switching through predefined macro definition; an environment reuse module, which is used for reusing the verification environment and test cases in different simulation modes; and a result analysis and comparison module, which is used for collecting and comparing simulation results in different simulation modes.The application can integrate multiple simulation modes, realize seamless switching and high reuse of the verification environment, simultaneously consider simulation speed and timing accuracy, and significantly improve the verification efficiency and quality of complex chip design.

Description

Technical Field

[0001] This invention relates to the field of chip design verification technology, and in particular to a simulation verification system and method that supports multiple verification scenarios. Background Technology

[0002] As the complexity of integrated circuit design continues to increase, especially in the design of Very Large Scale Integration Circuits (VLSI) and System on Chip (SoC), the demand for verifying the functional correctness and timing reliability of chips is growing stronger. In order to meet project cycle requirements and ensure product quality, chip verification processes are constantly evolving, gradually shifting from the traditional single simulation mode to multi-mode joint simulation verification.

[0003] Currently, the simulation verification methods widely used in the field of integrated circuit design verification mainly include the following: Register Transfer Level (RTL) functional simulation, Zero-delay Gate-level Simulation, and Gate-level Simulation with SDF Annotation. Register Transfer Level (RTL) functional simulation uses RTL code for functional simulation in the early stages of design. This method is relatively fast, convenient for debugging, and can quickly locate logic design errors, but it cannot accurately reflect the actual timing behavior of the circuit after physical implementation, and its coverage of timing-related errors is limited. Zero-delay Gate-level simulation is performed after logic synthesis to generate a gate-level netlist, with all gate and net delays set to zero. This method is mainly used to verify whether the synthesized netlist is consistent with the RTL design in terms of logic function, i.e., to perform structural equivalence checks, but it also does not contain real timing information and lacks coverage of timing-related issues. Gate-level simulation with SDF Annotation uses a gate-level netlist containing actual delay information after placement and routing, and performs timing back-annotation using a standard delay format file. This method is currently the main means of performing accurate timing verification. It can realistically simulate the timing behavior of chips under specific process, voltage, and temperature conditions, and discover timing violations such as setup time and hold time. However, the simulation speed is extremely slow, the debugging is difficult, the resource consumption is high, and it is usually difficult to perform large-scale regression testing.

[0004] In actual chip development, design teams typically need to switch between different simulation models and tools at different stages, quickly transitioning to fine-grained timing analysis after functional verification. For example, in the early stages of development, RTL functional simulation is mainly relied upon for functional development and verification; after synthesis, zero-latency gate-level simulation is introduced for logic equivalence checks; and after physical implementation, gate-level post-simulation with timing back-annotation is used for verification. However, this verification method with multiple simulation modes coexisting has problems in practical applications. Due to the inconsistency and fragmentation of different simulation models, problems arise such as poor reusability of the verification environment, poor cross-tool compatibility, difficulty in migrating simulation data, and the difficulty in balancing timing accuracy and simulation speed.

[0005] Therefore, a simulation verification system and method supporting multiple verification scenarios is proposed. It can integrate multiple simulation modes, achieve seamless switching and high reuse of verification environments, and support result comparison and analysis across toolchains and simulation levels, thereby significantly improving the verification efficiency and quality of complex chip designs. Summary of the Invention

[0006] To address some or all of the technical problems existing in the prior art, this invention provides a simulation verification system and method that supports multiple verification scenarios. It can integrate multiple simulation modes, achieve seamless switching and high reuse of verification environments, and support result comparison and analysis across toolchains and simulation levels, thereby significantly improving the verification efficiency and quality of complex chip designs.

[0007] The technical solution of the present invention is as follows:

[0008] Firstly, a simulation verification system supporting multiple verification scenarios is provided, including:

[0009] A unified verification environment, built on the same verification methodology, is used to connect with design code through an interface and provide test incentives;

[0010] The mode configuration module is used to receive user instructions and control the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate-level simulation mode and gate-level post-simulation mode with timing back-annotation. The mode configuration module realizes mode switching through predefined macro definitions. The macro definitions include a first macro definition for enabling the zero-delay gate-level simulation mode and a second macro definition for enabling the gate-level post-simulation mode with timing back-annotation.

[0011] The environment reuse module is used to reuse the verification environment and test cases in different simulation modes;

[0012] The results analysis and comparison module is used to collect and compare simulation results under different simulation modes.

[0013] Furthermore, in some embodiments, the unified verification environment includes a master device UVC and a slave device UVC, wherein the master device UVC is used to actively initiate transactions and the slave device UVC is used to passively respond to transactions, thereby forming a closed-loop verification environment.

[0014] Furthermore, in some implementations, when switching from register-transfer-level functional simulation mode to zero-latency gate-level simulation mode, the environment multiplexing module replaces the design code of register-transfer-level functional simulation with a gate-level netlist, thereby reducing all gate-level latency to zero.

[0015] When switching from register-transfer level function simulation mode to gate-level post-simulation mode with timing back-annotation, the environment multiplexing module uses the synthesized netlist and loads a standard delay format file for timing back-annotation.

[0016] Furthermore, in some embodiments, the result analysis and comparison module is also used to classify timing violations generated in the gate-level post-simulation mode with timing back-annotation. The timing violations include at least one of setup time violations, hold time violations, clock skew problems, and output driver content delay errors.

[0017] Furthermore, in some embodiments, the system further includes a tool adapter interface that is compatible with at least one simulation tool among Synopsys VCS, Cadence Xcelium, and Verilator through configurable compilation and simulation scripts.

[0018] Secondly, a simulation verification method is also provided. This method is used in a simulation verification system supporting multiple verification scenarios as described above to achieve register transfer level functional simulation. The method includes the following steps:

[0019] Develop a verification plan based on the design code;

[0020] Construct a register-transfer-level functional simulation and verification environment;

[0021] Construct an initialization sequence and, based on the functional points in the defined verification scheme, construct verification items covering all functional points;

[0022] Use a script to regress all validation items and collect coverage;

[0023] Determine if the coverage rate has reached 100%. If yes, collect the simulation results and generate a simulation report. If no, repeat the steps "Construct initialization sequence and construct verification items to cover all functional points according to the functional points in the established verification scheme" and "Use scripts to regress all verification items and collect coverage rate" until the coverage rate reaches 100%. Then, collect the simulation results and generate a simulation report.

[0024] Thirdly, a simulation verification method is also provided. This method is used in a simulation verification system supporting multiple verification scenarios as described above to achieve zero-latency gate-level simulation. The method includes the following steps:

[0025] Check the simulation results of the register transfer stage function;

[0026] Replace the design code for register-transfer-level functional simulation with a gate-level netlist, reduce all gate-level delays to zero, and build a zero-delay gate-level simulation environment;

[0027] The verification items of the multiplexed register transfer level function simulation are used as verification items of the zero-latency gate-level simulation to construct zero-latency verification items;

[0028] Add the first macro definition ZERO_GATE_SIM to the simulation command to switch the simulation mode to zero-delay gate-level simulation mode;

[0029] Regression zero-latency validation term;

[0030] Collect simulation results.

[0031] Fourthly, a simulation verification method is also provided. This method is used in a simulation verification system supporting multiple verification scenarios as described above to achieve a gate-level post-simulation mode with timing back-annotation. The method includes the following steps:

[0032] Check the simulation results of the register transfer stage function;

[0033] A gate-level post-simulation environment is constructed by using a synthesized netlist and loading a standard delay format file for timing inversion.

[0034] The verification items of the multiplexed register transfer level function simulation are used as the verification items of the gate-level post-simulation to construct the post-simulation verification items;

[0035] Add a second macro definition POST_SIM to the simulation command to switch the simulation mode to gate-level post-simulation mode with timing back-annotation;

[0036] Post-regression simulation validation items;

[0037] Investigate all timing violations;

[0038] Collect simulation results.

[0039] The main advantages of the technical solution of this invention are as follows:

[0040] The simulation verification system and method of this invention, supporting multiple verification scenarios, unifies register-transfer level functional simulation, zero-latency gate-level simulation, and gate-level post-simulation with timing back-annotation into a single verification architecture. This integrates multiple simulation modes, allowing users to flexibly switch between modes at different design stages. It achieves seamless switching and high reuse of the verification environment, enabling a smooth transition between early-stage rapid functional verification and later-stage high-precision timing verification, maintaining high simulation speed while ensuring timing accuracy. The environment reuse module reuses test cases and verification environments across different simulation modes, avoiding redundant development, reducing the workload of verification engineers, and improving verification efficiency. The result analysis and comparison module performs data comparison and violation classification, quickly identifying whether a problem stems from a functional error or a timing issue, significantly shortening the debugging cycle. It supports cross-toolchain and cross-simulation level result comparison analysis, thereby significantly improving the verification efficiency and quality of complex chip designs. Attached Figure Description

[0041] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0042] Figure 1 This is a schematic diagram of the structure of a simulation verification system supporting multiple verification scenarios, provided in an embodiment of the present invention.

[0043] Figure 2 A schematic diagram of a unified verification environment provided for an embodiment of the present invention is shown, which also illustrates the design of the circuit under test.

[0044] Figure 3 A flowchart illustrating a simulation verification method provided in an embodiment of the present invention;

[0045] Figure 4 A flowchart illustrating another simulation verification method provided in an embodiment of the present invention;

[0046] Figure 5 This is a flowchart illustrating another simulation verification method provided in an embodiment of the present invention. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0048] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] refer to Figure 1 In a first aspect, embodiments of the present invention provide a simulation verification system supporting multiple verification scenarios, including:

[0050] A unified verification environment, built on the same Universal Verification Methodology (UVM), is used to connect with design code through an interface and provide test incentives.

[0051] The mode configuration module is used to receive user instructions and control the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate-level simulation mode, and gate-level post-simulation mode with timing back-annotation.

[0052] The environment reuse module is used to reuse the verification environment and test cases in different simulation modes;

[0053] The results analysis and comparison module is used to collect and compare simulation results under different simulation modes.

[0054] In this embodiment of the invention, the design code is also the design under test (DUT) in the simulation verification process.

[0055] In this embodiment of the invention, the circuit design under test further includes a corresponding netlist, a Standard Delay Format (SDF) file, a model file, a macro definition file, an initialization file, and a library file.

[0056] In this embodiment of the invention, the netlist, standard delayed format file, model file, macro definition file, initialization file, and library file can be called by the mode configuration module as needed.

[0057] In this embodiment of the invention, the mode configuration module implements mode switching through predefined macro definitions, wherein the predefined macro definitions include a first macro definition ZERO_GATE_SIM for enabling zero-latency gate-level simulation mode, and a second macro definition POST_SIM for enabling gate-level post-simulation mode with timing back-annotation.

[0058] In this embodiment of the invention, the result analysis and comparison module collects simulation logs, coverage and timing violation information, and performs cross-mode consistency comparison and generates structured reports.

[0059] The simulation verification system and method provided in this invention, supporting multiple verification scenarios, unifies register-transfer level functional simulation, zero-latency gate-level simulation, and gate-level post-simulation with timing back-annotation into a single verification architecture. This integrates multiple simulation modes, allowing users to flexibly switch between modes at different design stages, achieving seamless switching and high reuse of the verification environment. It enables a smooth transition between early-stage rapid functional verification and later-stage high-precision timing verification, maintaining high simulation speed while ensuring timing accuracy. The environment reuse module reuses test cases and verification environments in different simulation modes, avoiding redundant development, reducing the workload of verification engineers, and improving verification efficiency. The result analysis and comparison module performs data comparison and violation classification, quickly identifying whether a problem stems from a functional error or a timing issue, significantly shortening the debugging cycle. It supports cross-toolchain and cross-simulation level result comparison analysis, thereby significantly improving the verification efficiency and quality of complex chip designs.

[0060] refer to Figure 2 Furthermore, in this embodiment of the invention, the unified verification environment includes a master device UVC (UVMVerification Component) and a slave device UVC. The master device UVC is used to actively initiate transactions, and the slave device UVC is used to passively respond to transactions, so as to form a closed-loop verification environment.

[0061] refer to Figure 2 In this embodiment of the invention, the master device UVC includes: a first read master agent, a first read sequence generator, a first read driver, a first write master agent, a first write sequence generator, a first write driver, a first monitor, a UVC configuration object, a first read response component, and a first write response component; the first read response component includes: a first predictive response, a first wait DPI (Direct Programming Interface) response unit, and a first wait response FIFO (First-In-First-Out); the first write response component includes: a second predictive response, a second wait DPI response unit, and a second wait response FIFO;

[0062] The slave device UVC includes: a second read master agent, a second read sequence generator, a second read driver, a second write master agent, a second write sequence generator, a second write driver, a second monitor, a UVC configuration object, a second read response component, and a second write response component; the second read response component includes: a first input request analysis unit, a first input request FIFO, and local memory; the second write response component includes: a second input request analysis unit and a second input request FIFO.

[0063] In this embodiment of the invention, the read master agent is responsible for simulating the behavior of a master device actively initiating read operations; the read sequence generator is responsible for generating and managing specific read operation transaction sequences; the read driver is responsible for converting abstract read transaction requests into specific signal timings conforming to the interface protocol; the write master agent is responsible for simulating the behavior of a master device actively initiating write operations; the write sequence generator is responsible for generating and managing specific write operation transaction sequences; the write driver is responsible for converting abstract write transaction requests into specific signal timings conforming to the interface protocol; the monitor is responsible for monitoring and recording all signals on the read and write interfaces; the UVC configuration object is a data structure used to centrally configure various parameters of the verification environment, such as interface address, data width, and whether certain functions are enabled, so that the entire environment can be flexibly adjusted without modifying the code; the read response component is used to process and check the read response data returned by the circuit design under test; the write response component is used to process and check the write response returned by the circuit design under test; the predicted response is a reference model. The calculated correct output of the circuit design under test (DUT) under given input serves as the "standard answer" for judging whether the DUT's behavior is correct. The DPI response waiting unit handles complex response calculations or interacts with higher-level models by calling external functions and waits for the results. The response waiting FIFO is a first-in-first-out buffer used to temporarily store sent request transactions. After the monitor captures the DUT's response, the corresponding request is retrieved from the FIFO for comparison. The input request analysis unit analyzes the input requests and generates expected responses based on this. The input request FIFO is also a first-in-first-out buffer used to buffer request transactions sent from the master device UVC, ensuring that transactions are processed in an orderly and smooth manner, preventing data loss or congestion. The local memory is a simulated memory model in the verification environment used to simulate the behavior of storage devices in the slave device UVC and compare it with the output of the DUT.

[0064] It should be noted that, in the appendix Figure 2In this context, Rd_seqr represents the read sequence generator, Rd_drv represents the read driver, Rd_master_agent represents the read master agent, Wr_drv represents the write driver, Wr_seqr represents the write sequence generator, Wr_master_agent represents the write master agent, Monitor represents the monitor, Uvc_config represents the UVC configuration object, Rd respcomponent represents the read response component, Wr resp component represents the write response component, Predicted resp represents the predicted response, Wait_dpi_resp represents the wait-for-DPI response unit, Wait_resp_fifo represents the wait-for-response FIFO, In_req_axp represents the input request analysis unit, Inreq_fifo represents the input request FIFO, and Local Memory represents the local memory.

[0065] Furthermore, in this embodiment of the invention, when the environment reuse module switches from register-transfer-level functional simulation mode to zero-latency gate-level simulation mode, it replaces the design code of register-transfer-level functional simulation with a gate-level netlist and sets all gate-level delays to zero; when the register-transfer-level functional simulation mode switches to gate-level post-simulation mode with timing back-annotation, it uses the synthesized netlist and loads a standard delay format file for timing back-annotation.

[0066] Furthermore, in this embodiment of the invention, the result analysis and comparison module is also used to classify timing violations generated in the gate-level post-simulation mode with timing back-annotation. The timing violations include at least one of setup violation, hold violation, clock skew problem, and output driver content delay error.

[0067] Furthermore, in this embodiment of the invention, the system further includes: a tool adapter interface, which is compatible with at least one simulation tool among Synopsys VCS, Cadence Xcelium, and Verilator through configurable compilation and simulation scripts.

[0068] In this embodiment of the invention, the mode configuration module is implemented using a Makefile, a configuration parsing script, and a YAML / JSON configuration file. The Makefile is the configuration file used to automate the project build process and serves as the top-level control file. The environment reuse module is implemented using a UVM configuration mechanism, configurable UVM components, and a file list management script. The result analysis and comparison module is implemented using a log parsing script, a result comparison script, and a report generation template.

[0069] refer to Figure 3 Secondly, embodiments of the present invention also provide a simulation verification method for the aforementioned simulation verification system supporting multiple verification scenarios, to achieve register transfer level functional simulation. The method includes the following steps:

[0070] Step 11: Develop a verification plan based on the design code;

[0071] Step 12: Construct a register-transfer-level functional simulation and verification environment;

[0072] Step 13: Construct an initialization sequence and, based on the functional points in the established verification scheme, construct verification items covering all functional points;

[0073] Step 14: Use a script to regress all validation items and collect coverage.

[0074] Step 15: Determine if the coverage rate has reached 100%. If yes, proceed to step 16; otherwise, return to step 13.

[0075] Step 16: Collect simulation results and generate a simulation report.

[0076] In this embodiment of the invention, in step 11, when formulating a verification plan based on the design code, the functional characteristics, interface protocols, and timing requirements of the design code are analyzed. Based on the analysis results, a strategy covering the complete verification objectives is formulated, the UVM verification system is adopted, and a simulation tool is selected.

[0077] In this embodiment of the invention, during step 12, when building the register transfer level functional simulation verification environment, the corresponding interface is generated in the top-level file according to the required interface protocol, and the required VIP (Verification Intellectual Property) is instantiated into the system. When in use, the component under test is bound to the unified verification environment through the interface, thus completing the reset and clock generation modules, as well as the reference model and other hardware modules in the system. Alternatively, a model from an external model file can be used as a reference model.

[0078] In this embodiment of the invention, in step 14, a simulation tool is selected for simulation, and a script is used to regress all verification items. Since the simulation verification system supports multiple simulation tools and provides corresponding Makefile files, the path to the sim.mk file contained in the Makefile under the sim file can be directly modified to switch between multiple simulation tools. The collection coverage is controlled by the cov parameter in the script, and the coverage merging is controlled by the cov_merge parameter in the script. The sim file serves as the "script and command center" for the verification project, storing all files related to the simulation process; sim.mk is a more specific rule and variable definition file contained in the Makefile.

[0079] In this embodiment of the invention, in step 15, when determining whether the coverage reaches 100%, both code coverage and functional coverage are required to reach 100%.

[0080] In this embodiment of the invention, in step 16, the simulation results are included in the log file. After the regression is completed, the system prints the regression results. The result information includes, but is not limited to, the number of simulation items, the number of items that passed, and the number of items that failed, thereby enabling rapid problem localization. The log file is a text output file generated during the simulation process, recording detailed information about the entire simulation process, and is the primary source of information for problem localization and result analysis.

[0081] refer to Figure 4 Thirdly, embodiments of the present invention also provide a simulation verification method for the aforementioned simulation verification system supporting multiple verification scenarios, to achieve zero-latency gate-level simulation. The method includes the following steps:

[0082] Step 21: Check the simulation results of the register transfer level function;

[0083] Step 22: Replace the design code for register-transfer-level functional simulation with a gate-level netlist, reduce all gate-level delays to zero, and build a zero-delay gate-level simulation environment;

[0084] Step 23: Use the verification items of the register transfer level function simulation as the verification items of the zero-latency gate-level simulation to construct the zero-latency verification items;

[0085] Step 24: Add the first macro definition ZERO_GATE_SIM to the simulation command to switch the simulation mode to zero-delay gate-level simulation mode.

[0086] Step 25, Regress the zero-latency verification item;

[0087] Step 26: Collect simulation results.

[0088] In this embodiment of the invention, before performing zero-latency gate-level simulation, it is necessary to ensure that the current register-transfer-level functional simulation has been completed and verify the correctness of its simulation results to provide a reference benchmark for subsequent comparisons. Therefore, before constructing the zero-latency gate-level simulation environment, the register-transfer-level functional simulation results are checked first.

[0089] In this embodiment of the invention, zero-delay gate-level simulation uses a gate-level netlist model to set all gate-level delays to zero for structural and logical functional consistency verification. Therefore, in step 22, when constructing the zero-delay gate-level simulation environment, the design code for register-transfer-level functional simulation is replaced with a gate-level netlist. The Makefile specifies `+delay_mode_zero`, and checks whether the module ports in the netlist match the unified verification environment. Here, `+delay_mode_zero` is a dedicated simulator instruction used to command the simulator to ignore all timing delay information in the netlist and standard delay format files when running gate-level netlist simulation, forcing the delays of all gates and connections to zero.

[0090] In this embodiment of the invention, in step 23, the verification items of the zero-delay gate-level simulation directly reuse the verification items of the register transfer level functional simulation. At the same time, verification items such as inversion path test, reset signal fan-out test, and clock gating logic verification can be further developed according to actual needs.

[0091] In this embodiment of the invention, in step 24, the simulation mode is switched from register transfer level function simulation mode to zero-delay gate-level simulation mode by adding the first macro definition ZERO_GATE_SIM to the simulation command; wherein, the parameters (options) and files required for the zero-delay gate-level simulation mode are controlled by the macro definition ZERO_GATE_SIM.

[0092] In this embodiment of the invention, in step 25, all zero-delay simulation items are executed to verify whether the logic function remains consistent in the gate-level netlist.

[0093] In this embodiment of the invention, in step 26, the simulation results are included in the log file. After the regression is completed, the system prints the regression results. The result information includes, but is not limited to, the number of simulation items, the number of items that passed, and the number of items that failed, so that the problem can be quickly located.

[0094] refer to Figure 5 Fourthly, embodiments of the present invention also provide a simulation verification method for the aforementioned simulation verification system supporting multiple verification scenarios, to achieve a gate-level post-simulation mode with timing back-annotation, comprising the following steps:

[0095] Step 31: Check the simulation results of the register transfer level function;

[0096] Step 32: Use the synthesized netlist and load the standard delay format file to perform timing inversion annotation and build the gate-level post-simulation environment;

[0097] Step 33: Multiplex the verification items of the register transfer level function simulation as the verification items of the gate-level post-simulation to construct the post-simulation verification items;

[0098] Step 34: Add the second macro definition POST_SIM to the simulation command to switch the simulation mode to the gate-level post-simulation mode with timing back-annotation;

[0099] Step 35, Post-regression simulation verification items;

[0100] Step 36: Check for all timing violations;

[0101] Step 37: Collect simulation results.

[0102] In this embodiment of the invention, before performing gate-level post-simulation with timing back-annotation, it is necessary to ensure that the current register-transfer-level functional simulation has been completed and verify the correctness of its simulation results to provide a reference benchmark for subsequent comparisons. Therefore, before constructing the gate-level post-simulation environment, the register-transfer-level functional simulation results are checked first.

[0103] In this embodiment of the invention, in step 32, a post-synthesis netlist is used in conjunction with a standard delay format file for timing inversion to construct a gate-level post-simulation environment. The path to the standard delay format file must match the module structure in the netlist, and necessary library files must be added.

[0104] In this embodiment of the invention, in step 33, the verification items of the gate-level post-simulation directly reuse the verification items of the register transfer level functional simulation. At the same time, critical path test items can also be constructed, such as setup / hold critical paths, latch paths, clock-gated paths, asynchronous domain cross-clock domain interaction paths, etc.

[0105] In this embodiment of the invention, in step 34, the simulation mode is switched from register transfer level function simulation mode to gate-level post-simulation mode with timing back-annotation by adding a second macro definition POST_SIM to the simulation command; wherein, the parameters (options) and files required for gate-level post-simulation mode with timing back-annotation are controlled by the macro definition POST_SIM.

[0106] In this embodiment of the invention, in step 35, all post-simulation simulation items are executed, and the system will print out the back-annotation rate and all un-back-annotated cases. Through the functional regression result set, simulation waveforms, and violation records provided by the system, the cause of the problem can be quickly located.

[0107] In this embodiment of the invention, in step 36, the violation records are classified. Violation categories include setup time violations, hold time violations, clock skew problems, output driver content delay errors, etc. All violations are eliminated in conjunction with waveforms to ensure that they do not affect the simulation results.

[0108] In this embodiment of the invention, in step 37, the simulation results are included in the log file. After the regression is completed, the system prints the regression results. The result information includes, but is not limited to, the number of simulation items, the number of items that passed, and the number of items that failed, so that the problem can be quickly located.

[0109] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Additionally, the terms "front," "back," "left," "right," "upper," and "lower" in this document refer to the placement shown in the accompanying drawings.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A simulation verification system supporting multiple verification scenarios, characterized in that, include: A unified verification environment, built on the same verification methodology, is used to connect with design code through an interface and provide test incentives; The mode configuration module is used to receive user instructions and control the simulation verification system to switch between register transfer level function simulation mode, zero-delay gate-level simulation mode and gate-level post-simulation mode with timing back-annotation. The mode configuration module realizes mode switching through predefined macro definitions. The macro definitions include a first macro definition for enabling the zero-delay gate-level simulation mode and a second macro definition for enabling the gate-level post-simulation mode with timing back-annotation. The environment reuse module is used to reuse the verification environment and test cases in different simulation modes; The results analysis and comparison module is used to collect and compare simulation results under different simulation modes; Specifically, when switching from register-transfer level functional simulation mode to zero-latency gate-level simulation mode, the design code of register-transfer level functional simulation is replaced with a gate-level netlist, and all gate-level delays are set to zero; when switching from register-transfer level functional simulation mode to gate-level post-simulation mode with timing back-annotation, the synthesized netlist is used and a standard delay format file is loaded for timing back-annotation.

2. The simulation verification system supporting multiple verification scenarios according to claim 1, characterized in that, The unified verification environment includes a master device UVC and a slave device UVC. The master device UVC is used to actively initiate transactions, and the slave device UVC is used to passively respond to transactions, thus forming a closed-loop verification environment.

3. The simulation verification system supporting multiple verification scenarios according to claim 1, characterized in that, When switching from register-transfer-level functional simulation mode to zero-latency gate-level simulation mode, the environment multiplexing module uses a gate-level netlist to replace the design code of register-transfer-level functional simulation, thus reducing all gate-level latency to zero. When switching from register-transfer level function simulation mode to gate-level post-simulation mode with timing back-annotation, the environment multiplexing module uses the synthesized netlist and loads a standard delay format file for timing back-annotation.

4. The simulation verification system supporting multiple verification scenarios according to claim 1, characterized in that, The result analysis and comparison module is also used to classify timing violations generated in the gate-level post-simulation mode with timing back-annotation. Timing violations include at least one of setup time violations, hold time violations, clock skew problems, and output driver content delay errors.

5. The simulation verification system supporting multiple verification scenarios according to claim 1, characterized in that, Also includes: A tool adapter interface that is compatible with at least one of the simulation tools Synopsys VCS, Cadence Xcelium, and Verilator through configurable compilation and simulation scripts.

6. A simulation verification method, characterized in that, The method is used in a simulation verification system supporting multiple verification scenarios as described in any one of claims 1-5 to achieve register transfer level functional simulation. The method includes the following steps: Develop a verification plan based on the design code; Construct a register-transfer-level functional simulation and verification environment; Construct an initialization sequence and, based on the functional points in the defined verification scheme, construct verification items covering all functional points; Use a script to regress all validation items and collect coverage; Determine if the coverage rate has reached 100%. If yes, collect the simulation results and generate a simulation report. If not, repeat the steps "Construct initialization sequence and construct verification items to cover all functional points according to the functional points in the established verification scheme" and "Use scripts to regress all verification items and collect coverage rate" until the coverage rate reaches 100%. Then, collect the simulation results and generate a simulation report.

7. A simulation verification method, characterized in that, The method is used in a simulation verification system supporting multiple verification scenarios as described in any one of claims 1-5 to achieve zero-latency gate-level simulation. The method includes the following steps: Check the simulation results of the register transfer stage function; Replace the design code for register-transfer-level functional simulation with a gate-level netlist, reduce all gate-level delays to zero, and build a zero-delay gate-level simulation environment; The verification items of the multiplexed register transfer level function simulation are used as verification items of the zero-latency gate-level simulation to construct zero-latency verification items; Add the first macro definition ZERO_GATE_SIM to the simulation command to switch the simulation mode to zero-delay gate-level simulation mode; Regression zero-latency validation term; Collect simulation results.

8. A simulation verification method, characterized in that, The method is used in a simulation verification system supporting multiple verification scenarios as described in any one of claims 1-5, to achieve a gate-level post-simulation mode with timing back-annotation. The method includes the following steps: Check the simulation results of the register transfer stage function; A gate-level post-simulation environment is constructed by using a synthesized netlist and loading a standard delay format file for timing inversion. The verification items of the multiplexed register transfer level function simulation are used as the verification items of the gate-level post-simulation to construct the post-simulation verification items; Add a second macro definition POST_SIM to the simulation command to switch the simulation mode to gate-level post-simulation mode with timing back-annotation; Post-regression simulation validation items; Investigate all timing violations; Collect simulation results.

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