High-precision adjustable large-swing-range integrated multi-channel driving circuit

Abstract

The invention discloses a high-precision adjustable large-swing range integrated multi-channel driving circuit, on one hand, a pre-stage gain adjustable circuit is adopted to calibrate gain deviation and realize multi-channel integration, and on the other hand, a post-stage large-swing adjustable output stage circuit is adopted to realize multi-channel integration by combining digital coarse tuning and analog fine tuning functions. And the large-range high-precision adjustment of the output signal amplitude is realized. The driving circuit adopts a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) process, and a pre-stage gain adjustable circuit realizes gain deviation calibration through an improved Gilbert unit circuit structure and is compatible with a multi-channel integration function. Besides, a rear-stage large-swing adjustable output stage circuit controls the on-off of a tail current source through a switch, so that the swing range of an output signal reaches 3.0 V, and the tail current source of the current mode logic circuit is continuously adjusted within a certain range by integrating a 14-bit digital-to-analog converter circuit. And the fine adjustment resolution of the output signal amplitude is less than 0.2 mV.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of driving circuit and driving chip design in optical fiber communication and interface circuit system, and particularly relates to a high-precision adjustable large-swing-range integrated multi-channel driving circuit. BACKGROUND

[0002] In recent years, with the rapid development of the fifth generation mobile communication, artificial intelligence, cloud computing and other technologies, the amount of data to be processed has exploded, which has also made the new generation of large data centers a hot spot. In large data centers, the continuous increase in data volume has made people's requirements for data transmission rate higher and higher, and the performance of the interface circuit is one of the important factors restricting the data transmission rate. Serializer / deserializer (SerDes) interface is a high-speed serial interface that was first developed in optical fiber communication. Currently, this type of interface is also widely used in high-speed transmission design of electrical signals and has become a core technology in the field of high-speed communication. The main working mode of SerDes interface is to serialize low-speed parallel signals at the sending end, amplify them through the driving circuit, and then transmit them to the receiving end through the channel. At the receiving end, the high-speed serial data is deserialized to form low-speed parallel data that can be processed by subsequent digital circuits.

[0003] Due to the non-ideal factors such as skin effect, dielectric loss and reflection between the sending end and the receiving end, the quality of the signal reaching the receiving end is severely distorted, causing problems such as increased system bit error rate. With the increase in data transmission rate, these non-ideal factors become more and more serious. To meet the requirements of high-speed and long-distance transmission, the driver circuit at the sending end needs to achieve a large output signal range and higher precision adjustable and calibratable performance. In addition, the development trend of multi-functional integration of integrated circuit systems also puts forward higher requirements for the multi-channel integration characteristics of the driving circuit. SUMMARY

[0004] The present application aims to provide a high-precision adjustable large-swing-range integrated multi-channel driving circuit. On the one hand, it adopts a front-stage gain adjustable circuit to calibrate gain deviation and realize multi-channel integration function. On the other hand, it adopts a rear-stage large-swing adjustable output stage circuit to realize large-range high-precision adjustment of output signal swing through a mechanism combining digital coarse adjustment and analog fine adjustment. It has the advantages of large output swing, high adjustable precision, gain calibrability and multi-channel integration, to solve the technical problems mentioned in the background art.

[0005] To solve the above technical problems, the specific technical solutions of the present application are as follows:

[0006] The application discloses a high-precision adjustable large-swing-range integrated multi-channel drive circuit.

[0007] The front-stage gain-adjustable circuit is used for calibrating gain deviation and realizing multi-channel integration function, and is composed of a cross-coupled gain adjusting module and one or more input-stage units connected in series.

[0008] The cross-coupled gain adjusting module is composed of transistors and load resistors, wherein two groups of parallel transistors form a cross-coupled structure and are connected in series with a pair of parallel load resistors.

[0009] The calibration function control signal controls the gain of the cross-coupled gain adjusting module, thereby realizing the gain deviation calibration function.

[0010] The input-stage unit is composed of transistors, resistors and capacitors, wherein the resistors and capacitors are connected in parallel and are connected across a group of parallel transistor differential pairs and are connected in series with a tail current source transistor.

[0011] The front-stage gain-adjustable circuit is composed of a cross-coupled gain adjusting module and a plurality of input-stage units connected in series.

[0012] The routing switch control signal controls the on-off of the transistors, thereby realizing the channel selection function.

[0013] The rear-stage large-swing-adjustable output-stage circuit is used for realizing large-range high-precision adjustment of the swing of an output signal, and is composed of a pair of parallel resistors and one or more current-mode logic output-stage units connected in series.

[0014] The current-mode logic output-stage unit is composed of transistors, wherein the transistors are connected in parallel to form a differential pair structure and are connected in series with a tail current source transistor.

[0015] The input signal input terminals OUT1P and OUT1N are connected with the output signal output terminals of the front-stage gain-adjustable circuit; the external coarse adjustment control signal controls the on-off of the transistors, thereby realizing coarse adjustment of the swing of the output signal in a large range; the external fine adjustment control signal Vdm is provided by an external digital-to-analog converter circuit; and the fine adjustment control signal Vdm controls the opening degree of the tail current transistor, thereby realizing fine adjustment of the swing of the output signal.

[0016] Further, the cross-coupled gain adjusting module is composed of a transistor QG1, a transistor QG2, a transistor QG3, a transistor QG4, a resistor RL1 and a resistor RL2.

[0017] The base of the transistor QG1 is connected with the calibration function control signal input end VcN and the base of the transistor QG4 respectively, the collector of the transistor QG1 is connected with the output signal output end OUT1N, the collector of the transistor QG3 and the first end of the resistor RL1 respectively, and the emitter of the transistor QG1 is connected with the emitter of the transistor QG2, the collector of the transistor Q1, the collector of the transistor Q3, the collector of the transistor Q5 and the collector of the transistor Q2n-1 respectively, wherein n is the number of the input stage units, and n is not less than 1;

[0018] The base of the transistor QG2 is connected with the calibration function control signal input end VcP and the base of the transistor QG3 respectively, and the collector of the transistor QG2 is connected with the output signal output end OUT1P, the collector of the transistor QG4 and the first end of the resistor RL2 respectively.

[0019] The emitter of the transistor QG3 is connected with the emitter of the transistor QG4, the collector of the transistor Q2, the emitter of the transistor QG4, the collector of the transistor Q4, the collector of the transistor Q6 and the collector of the transistor Q2n respectively, wherein n is not less than 1.

[0020] The input stage unit is composed of the transistor Q1, the transistor Q2, the transistor M1, the transistor M2, the transistor Mb1, the transistor Mb2, the transistor Mb3, the capacitor C1 and the resistor R1, and specifically comprises:

[0021] The base of the transistor Q1 is connected with the input signal input end IN_CH1P of the channel one, the emitter of the transistor Q1 is connected with the first end of the capacitor C1, the first end of the resistor R1 and the drain of the transistor M1 respectively, and the collector of the transistor Q1 is connected with the emitter of the transistor QG1, the emitter of the transistor QG2, the collector of the transistor Q3, the collector of the transistor Q5 and the collector of the transistor Q2n-1 respectively, and n is not less than 1.

[0022] The base of the transistor Q2 is connected with the input signal input end IN_CH1N of the channel one, the emitter of the transistor Q2 is connected with the second end of the capacitor C1, the second end of the resistor R1 and the drain of the transistor M2 respectively, and the collector of the transistor Q2 is connected with the emitter of the transistor QG3, the emitter of the transistor QG4, the collector of the transistor Q4, the collector of the transistor Q6 and the collector of the transistor Q2n respectively, wherein n is not less than 1.

[0023] The gate of the transistor M1 is connected with the routing control signal Vch1 and the gate of the transistor M2 respectively, the gate of the transistor M3 is connected with the routing control signal Vch2 and the gate of the transistor M4 respectively, the gate of the transistor M2n-1 is connected with the routing control signal Vchn and the gate of the transistor M2n respectively, and the source of the transistor M1 is connected with the drain of the transistor Mb2.

[0024] The source of the transistor M2 is connected with the drain of the transistor Mb3;

[0025] The base of the transistor Q3 is connected with the input signal input end IN_CH2P of the channel two, and the emitter of the transistor Q3 is connected with the first end of the capacitor C2, the first end of the resistor R2 and the drain of the transistor M3 respectively;

[0026] The base of the transistor Q4 is connected with the input signal input end IN_CH2N of the channel two, and the emitter of the transistor Q4 is connected with the second end of the capacitor C2, the second end of the resistor R2 and the drain of the transistor M4 respectively;

[0027] The source of the transistor M3 is connected with the drain of the transistor Mb5;

[0028] The source of the transistor M4 is connected with the drain of the transistor Mb6;

[0029] The base of the transistor Q2n-1 is connected with the input signal input end IN_CHnP of the channel n, and the emitter of the transistor Q2n-1 is connected with the first end of the capacitor Cn, the first end of the resistor Rn and the drain of the transistor M2n-1 respectively, wherein n is not less than 1;

[0030] The base of the transistor Q2n is connected with the input signal input end IN_CHnN of the channel n, and the emitter of the transistor Q2n is connected with the second end of the capacitor Cn, the second end of the resistor Rn and the drain of the transistor M2n respectively, wherein n is not less than 1;

[0031] The source of the transistor M2n-1 is connected with the drain of the transistor Mb3n-1, wherein n is not less than 1;

[0032] The source of the transistor M2n is connected with the drain of the transistor Mb3n, wherein n is not less than 1;

[0033] The gate of the transistor Mb1 is connected with the drain of the transistor Mb1, the bias current input end I1, the gate of the transistor Mb2 and the gate of the transistor Mb3 respectively, the gate of the transistor Mb4 is connected with the drain of the transistor Mb4, the bias current input end I2, the gate of the transistor Mb5 and the gate of the transistor Mb6 respectively, and the gate of the transistor Mb3n-2 is connected with the drain of the transistor Mb3n-2, the bias current input end In, the gate of the transistor Mb3n-1 and the gate of the transistor Mb3n respectively;

[0034] The source of the transistor Mb1 is connected with the negative power voltage input end VEE, the source of the transistor Mb2, the source of the transistor Mb3 and the source of the transistor Mb3n respectively;

[0035] The second end of the resistor RL1 is connected with the first end of the inductor L1;

[0036] The second end of the resistor RL2 is connected with the first end of the inductor L2;

[0037] The second end of the inductor L1 is connected with the positive power voltage input end VDD and the second end of the inductor L2 respectively;

[0038] The values of the capacitors C1, C2 to C2n are adjustable, which are used for the weighting effect of different gears.

[0039] Further, the current mode logic output stage unit comprises a transistor B1, a transistor B2, a transistor Ms1, a transistor Ms2 and a transistor Md1, and specifically comprises:

[0040] The base of the transistor B1 is connected with the input signal input end OUT1P, the base of the transistor B3, the base of the transistor B5 to the base of the transistor B2m-1 respectively, wherein m is the number of the current mode logic output stage units, and m is not less than 1, the emitter of the transistor B1 is connected with the emitter of the transistor B2 and the drain of the transistor Md1 respectively, and the collector of the transistor B1 is connected with the source of the transistor Ms1;

[0041] The base of the transistor B2 is connected with the input signal input end OUT1N, the base of the transistor B4, the base of the transistor B6 to the base of the transistor B2m respectively, wherein m is not less than 1, and the collector of the transistor B2 is connected with the source of the transistor Ms2;

[0042] The gate of the transistor Ms1 is connected with the coarse adjustment control signal Vsw1 and the gate of the transistor Ms2 respectively, the gate of the transistor Ms3 is connected with the coarse adjustment control signal Vsw2 and the gate of the transistor Ms4 respectively, the gate of the transistor Ms2m-1 is connected with the coarse adjustment control signal Vswm and the gate of the transistor Ms2m respectively, wherein m is not less than 1;

[0043] The drain of the transistor Ms1 is connected with the output signal output end OUTN, the drain of the transistor Ms3, the drain of the transistor Ms5 to the drain of the transistor Ms2m-1 and the first end of the resistor RL3 respectively, wherein m is not less than 1;

[0044] The drain of the transistor Ms2 is connected with the output signal output end OUTP, the drain of the transistor Ms4, the drain of the transistor Ms6 to the drain of the transistor Ms2m and the first end of the resistor RL4 respectively, wherein m is not less than 1;

[0045] The emitter of the transistor B3 is connected with the emitter of the transistor B4 and the drain of the transistor Md2 respectively, and the collector of the transistor B3 is connected with the source of the transistor Ms3;

[0046] The collector of the transistor B4 is connected with the source of the transistor Ms4;

[0047] The emitter of the transistor B2m-1 is connected with the emitter of the transistor B2m and the drain of the transistor Mdm respectively, and the collector of the transistor B2m-1 is connected with the source of the transistor Ms2m-1, wherein m is not less than 1;

[0048] The collector of the transistor B2m is connected with the source of the transistor Ms2m, wherein m is not less than 1;

[0049] The source of the transistor Md1 is connected with the negative power voltage input terminal VEE, the source of the transistor Md2, the source of the transistor Md3 and the source of the transistor Mdm respectively, wherein m is not less than 1;

[0050] The second end of the resistor RL3 is connected with the first end of the inductor L3;

[0051] The second end of the resistor RL4 is connected with the first end of the inductor L4;

[0052] The second end of the inductor L3 is connected with the positive power voltage input terminal VDD and the second end of the inductor L4 respectively;

[0053] The gate of the transistor Md1 is connected with the fine adjustment control signal Vd1, the gate of the transistor Md2 is connected with the fine adjustment control signal Vd2, the gate of the transistor Mdm is connected with the fine adjustment control signal Vdm, and the fine adjustment control signal Vdm is provided externally.

[0054] Further, the traditional Gilbert cell circuit structure is improved, the calibration function control signal input terminals VcP and VcN realize the adjustment of the circuit gain by controlling the transconductance of the transistors QG1, QG2, QG3 and QG4, thereby realizing the gain deviation calibration function;

[0055] Further, the base of the transistor Q1 and the base of the transistor Q2 are used as the input terminals of the differential input signal of the channel, and the improved Gilbert structure can realize the function of integrated multi-channel input; that is, the transistors Q2n-1, Q2n, M2n-1, M2n, Mb3n-2, Mb3n-1, Mb3n, Cn and Rn form an input stage unit, wherein n is not less than 1, the front-stage gain adjustable circuit comprises at least one input stage unit, and the routing switch control signal Vchn realizes the channel selection function by controlling the switch, wherein n is not less than 1.

[0056] Further, the capacitors C1, C2, …, Cn are used to introduce capacitive negative feedback in the differential amplifier, so that the effective transconductance is increased at high frequencies to compensate for the high-frequency attenuation caused by the pole at the output node. The capacitor degeneration technique introduces a zero in the circuit to cancel the pole at the output node, thereby increasing the circuit bandwidth.

[0057] Further, the resistors R1, R2, …, Rn and the capacitors C1, C2, …, Cn are used to form a feedback circuit to achieve pre-emphasis, expand the bandwidth, and improve the linearity.

[0058] Further, the inductors L1 and L2 are used to introduce an additional zero in the circuit, thereby increasing the bandwidth of the circuit. The advantage of this bandwidth expansion structure is that it only needs to be set on the load resistor, without the need to increase the complexity of the structure.

[0059] Further, the inductors L3 and L4 are used to introduce an additional zero in the circuit, thereby increasing the bandwidth of the circuit. The advantage of this bandwidth expansion structure is that it only needs to be set on the load resistor, without the need to increase the complexity of the structure in the driving unit, which is more suitable for the later-stage large-swing adjustable output stage circuit designed in this article.

[0060] Further, the transistors B2m-1, B2m, Mdm, Ms2m-1, and Ms2m form an output stage unit, where m is not less than 1, and the later-stage large-swing adjustable output stage circuit includes at least one of the output stage units.

[0061] When the transistor B2m-1 is in the amplification region, its collector current I C is:

[0062]

[0063] where I S is a constant used to describe the transistor transmission characteristics in the forward amplification region, V BE is the transistor base-emitter voltage, V T is the transistor threshold voltage, and thus the transconductance of the transistor B2m-1 is:

[0064]

[0065] where α is the transistor amplification factor, and it can be seen that the transistor transconductance g m is proportional to the emitter current I EThe output signal swing is linearly related to the total tail current of the turned-on output stage unit in the post-stage large swing adjustable output stage circuit.

[0066] The two ways of adjusting the total tail current, coarse adjustment and fine adjustment, jointly determine the number of bits of the output signal swing adjustment, that is, the number of bits of the output signal swing adjustment of the high-precision adjustable large swing range integrated multi-channel drive circuit is equal to the sum of the coarse adjustment bits and the fine adjustment bits of the post-stage large swing adjustable output stage circuit.

[0067] Further, the output signal swing coarse adjustment of the post-stage large swing adjustable output stage circuit is realized by controlling the on-off of the transistor through the coarse adjustment switch control signal Vswm, where m is not less than 1, and the value of the coarse adjustment bit q is the floor of log2m.

[0068] Further, the circuit is realized by using the BiCMOS process.

[0069] The high-precision adjustable large swing range integrated multi-channel drive circuit has the following advantages:

[0070] (1) The present application utilizes the characteristics of the BiCMOS process, adopts high-voltage transistors B1 and B2, and provides a coarse adjustment control signal Vswm externally, so that the range of the output signal swing reaches 3.0V;

[0071] (2) The present application integrates a 14-bit digital-to-analog converter circuit and uses the fine adjustment control signal Vdm provided by the digital-to-analog converter circuit to realize fine adjustment of the output signal swing with a resolution less than 0.2mV;

[0072] (3) The present application realizes the compatibility of gain deviation calibration function and multi-channel integration function through the cross-coupled gain adjustment module;

[0073] (4) The present application realizes the expansion of the driver bandwidth by introducing the capacitor degeneration technology through capacitors C1, C2…Cn;

[0074] (5) The present application realizes the optimization of the driver linearity by introducing the first-stage negative feedback resistance through resistors R1, R2…Rn. BRIEF DESCRIPTION OF DRAWINGS

[0075] Figure 1 is a structural schematic diagram of a high-precision adjustable large swing range integrated multi-channel drive circuit of the present application;

[0076] Figure 2 is a structural schematic diagram of a pre-stage gain adjustable circuit of the present application;

[0077] Figure 3 Figure 1 is a structural schematic diagram of a post-stage large swing adjustable output stage circuit according to the present application. DETAILED DESCRIPTION

[0078] In order to better understand the purpose, structure and function of the present application, a high-precision adjustable large swing range integrated multi-channel drive circuit according to the present application is described in further detail below in combination with the drawings.

[0079] As shown in Figure 1, a high-precision adjustable large swing range integrated multi-channel drive circuit according to the present application includes a pre-stage gain adjustable circuit and a post-stage large swing adjustable output stage circuit. Figure 1 As shown in Figure 1, a high-precision adjustable large swing range integrated multi-channel drive circuit according to the present application includes a pre-stage gain adjustable circuit and a post-stage large swing adjustable output stage circuit.

[0080] The pre-stage gain adjustable circuit is used for calibrating gain deviation and realizing multi-channel integration function, and includes a positive power supply voltage input terminal VDD, a negative power supply voltage input terminal VEE, input signal input terminals IN_CHnP and IN_CHnN, a bias current input terminal In, calibration function control signal input terminals VcP and VcN, routing control signal input terminals Vchn, and output signal output terminals OUT1P and OUT1N. The pre-stage gain adjustable circuit is used for calibrating gain deviation and realizing multi-channel integration function, and includes a cross-coupled gain adjustment module and an input stage unit. The cross-coupled gain adjustment module is composed of transistors and load resistors, wherein two sets of parallel transistors form a cross-coupled structure and are connected in series with a pair of parallel resistors to form the cross-coupled gain adjustment module. The calibration function control signal controls the gain of the cross-coupled gain adjustment module to realize the gain deviation calibration function. The input stage unit is composed of transistors, resistors and capacitors, wherein the resistors and capacitors are connected in parallel and are connected across a set of parallel transistor differential pairs and are connected in series with a tail current source transistor to form the input stage unit. The pre-stage gain adjustable circuit includes at least one input stage unit to realize the multi-channel integration function. The pre-stage gain adjustable circuit is composed of the cross-coupled gain adjustment module and a plurality of parallel input stage units connected in series. The routing switch control signal controls the on-off of the transistors to realize the channel selection function. The output signal output terminals OUT1P and OUT1N are connected to the input signal input terminals of the post-stage large swing adjustable output stage circuit.

[0081] The large-swing adjustable output stage circuit is used to achieve a wide range of high-precision adjustment of the output signal swing. It includes a positive power supply voltage input terminal VDD, a negative power supply voltage input terminal VEE, input signal input terminals OUT1P and OUT1N, a coarse adjustment control signal input terminal Vswm, a fine adjustment control signal input terminal Vdm, and output signal output terminals OUTP and OUTN. The large-swing adjustable output stage circuit includes a current-mode logic output stage unit and resistors. The current-mode logic output stage unit is composed of transistors, wherein the transistors are connected in parallel to form a differential pair structure and connected in series with the tail current source transistor to form the current-mode logic output stage unit. The large-swing adjustable output stage circuit includes at least one output stage unit to achieve coarse adjustment of the output signal swing. The large-swing adjustable output stage circuit is composed of a pair of parallel resistors connected in series with multiple parallel current-mode logic output stage units. The input signal input terminals OUT1P and OUT1N are connected to the output signal output terminals of the pre-stage gain-adjustable circuit. The coarse adjustment control signal controls the switching on and off of transistors to achieve coarse adjustment of the output signal swing over a wide range. The fine adjustment control signal Vdm is provided externally. The fine adjustment control signal Vdm controls the on / off state of the tail current transistor to achieve fine adjustment of the output signal swing.

[0082] like Figure 2 The diagram shown is a circuit diagram of an embodiment of the adjustable gain preamplifier circuit of the present invention. Specifically, the detailed connection methods of each component are as follows:

[0083] The cross-coupling gain adjustment module consists of transistors QG1, QG2, QG3, and QG4, resistors RL1 and RL2, and specifically includes:

[0084] The base of transistor QG1 is connected to the calibration function control signal input terminal VcN and the base of transistor QG4, respectively. The collector of transistor QG1 is connected to the output signal output terminal OUT1N, the collector of transistor QG3 and the first terminal of resistor RL1, respectively. The emitter of transistor QG1 is connected to the emitter of transistor QG2, the collector of transistor Q1, the collector of transistor Q3, the collector of transistor Q5 up to the collector of transistor Q2n-1, where n is the number of input stage units and n is not less than 1.

[0085] The base of transistor QG2 is connected to the calibration function control signal input terminal VcP and the base of transistor QG3, respectively. The collector of transistor QG2 is connected to the output signal output terminal OUT1P, the collector of transistor QG4 and the first terminal of resistor RL2, respectively.

[0086] The emitter of the transistor QG3 is connected with the emitter of the transistor QG4, the collector of the transistor Q2, the emitter of the transistor QG4, the collector of the transistor Q4, the collector of the transistor Q6 and the collector of the transistor Q2n respectively, wherein n is not less than 1;

[0087] The input stage unit is composed of the transistor Q1, the transistor Q2, the transistor M1, the transistor M2, the transistor Mb1, the transistor Mb2, the transistor Mb3, the capacitor C1 and the resistor R1, and specifically comprises:

[0088] The base of the transistor Q1 is connected with the input signal input end IN_CH1P of the channel one, the emitter of the transistor Q1 is connected with the first end of the capacitor C1, the first end of the resistor R1 and the drain of the transistor M1 respectively, and the collector of the transistor Q1 is connected with the emitter of the transistor QG1, the emitter of the transistor QG2, the collector of the transistor Q3, the collector of the transistor Q5 and the collector of the transistor Q2n-1 respectively, wherein n is the number of the input stage unit, and n is not less than 1;

[0089] The base of the transistor Q2 is connected with the input signal input end IN_CH1N of the channel one, the emitter of the transistor Q2 is connected with the second end of the capacitor C1, the second end of the resistor R1 and the drain of the transistor M2 respectively, and the collector of the transistor Q2 is connected with the emitter of the transistor QG3, the emitter of the transistor QG4, the collector of the transistor Q4, the collector of the transistor Q6 and the collector of the transistor Q2n respectively, wherein n is not less than 1;

[0090] The gate of the transistor M1 is connected with the routing control signal Vch1 and the gate of the transistor M2 respectively, the gate of the transistor M3 is connected with the routing control signal Vch2 and the gate of the transistor M4 respectively, the gate of the transistor M2n-1 is connected with the routing control signal Vchn and the gate of the transistor M2n respectively, and the source of the transistor M1 is connected with the drain of the transistor Mb2;

[0091] The source of the transistor M2 is connected with the drain of the transistor Mb3;

[0092] The base of the transistor Q3 is connected with the input signal input end IN_CH2P of the channel two, and the emitter of the transistor Q3 is connected with the first end of the capacitor C2, the first end of the resistor R2 and the drain of the transistor M3 respectively;

[0093] The base of the transistor Q4 is connected with the input signal input end IN_CH2N of the channel two, and the emitter of the transistor Q4 is connected with the second end of the capacitor C2, the second end of the resistor R2 and the drain of the transistor M4 respectively;

[0094] The source of the transistor M3 is connected with the drain of the transistor Mb5;

[0095] The source of the transistor M4 is connected with the drain of the transistor Mb6;

[0096] The base of the transistor Q2n-1 is connected with the input signal input end IN_CHnP of the channel n, and the emitter of the transistor Q2n-1 is connected with the first end of the capacitor Cn, the first end of the resistor Rn and the drain of the transistor M2n-1 respectively, wherein n is not less than 1;

[0097] The base of the transistor Q2n is connected with the input signal input end IN_CHnN of the channel n, and the emitter of the transistor Q2n is connected with the second end of the capacitor Cn, the second end of the resistor Rn and the drain of the transistor M2n respectively, wherein n is not less than 1;

[0098] The source of the transistor M2n-1 is connected with the drain of the transistor Mb3n-1, wherein n is not less than 1;

[0099] The source of the transistor M2n is connected with the drain of the transistor Mb3n, wherein n is not less than 1;

[0100] The gate of the transistor Mb1 is connected with the drain of the transistor Mb1, the bias current input end I1, the gate of the transistor Mb2 and the gate of the transistor Mb3 respectively, the gate of the transistor Mb4 is connected with the drain of the transistor Mb4, the bias current input end I2, the gate of the transistor Mb5 and the gate of the transistor Mb6 respectively, and the gate of the transistor Mb3n-2 is connected with the drain of the transistor Mb3n-2, the bias current input end In, the gate of the transistor Mb3n-1 and the gate of the transistor Mb3n respectively;

[0101] The source of the transistor Mb1 is connected with the negative power voltage input end VEE, the source of the transistor Mb2, the source of the transistor Mb3 and the source of the transistor Mb3n respectively;

[0102] The second end of the resistor RL1 is connected with the first end of the inductor L1;

[0103] The second end of the resistor RL2 is connected with the first end of the inductor L2;

[0104] The second end of the inductor L1 is connected with the positive power voltage input end VDD and the second end of the inductor L2 respectively;

[0105] The values of the capacitor C1, the capacitor C2 and the capacitor C2n are adjustable, which are used for the weighting effect of different gears.

[0106] Further, the traditional Gilbert unit circuit structure is improved, the calibration function control signal input ends VcP and VcN realize the adjustment of the circuit gain by controlling the transconductance of the transistor QG1, the transistor QG2, the transistor QG3 and the transistor QG4, and then realize the gain deviation calibration function.

[0107] Further, the base of the transistor Q1 and the base of the transistor Q2 are used as the input end of the channel differential input signal, and the improved Gilbert structure can realize the function of integrated multi-channel input; that is, the transistor Q2n-1, the transistor Q2n, the transistor M2n-1, the transistor M2n, the transistor Mb3n-2, the transistor Mb3n-1, the transistor Mb3n, the capacitor Cn and the resistor Rn form an input stage unit, wherein n is not less than 1, the front-stage gain-adjustable circuit comprises at least one input stage unit, and the routing switch control signal Vchn realizes the channel selection function through the switch.

[0108] Further, the capacitive feedback is introduced in the transistor differential amplifier through the capacitors C1, C2,..., Cn, so that the effective transconductance is improved at a high frequency, and the high-frequency attenuation caused by the pole at the output node is compensated.

[0109] Further, the pre-emphasis function is realized by the feedback circuit formed by the resistors R1, R2,..., Rn and the capacitors C1, C2,..., Cn in parallel, the bandwidth is expanded, and the linearity is improved.

[0110] Further, an additional zero point is introduced in the circuit through the inductors L1 and L2, so that the bandwidth of the circuit is improved. The advantage is that the bandwidth expansion structure only needs to be arranged on the load resistor, without increasing the complexity of the structure.

[0111] As shown in Figure 3 FIG. 1 is a circuit diagram of a front-stage gain-adjustable input stage circuit according to the present application, and the detailed connection mode of each component is as follows:

[0112] The current-mode logic output stage unit comprises the transistor B1, the transistor B2, the transistor Ms1, the transistor Ms2 and the transistor Md1, and specifically comprises:

[0113] The base of the transistor B1 is connected with the input signal input end OUT1P, the base of the transistor B3, the base of the transistor B5 and the base of the transistor B2m-1 respectively, wherein m is the number of the current-mode logic output stage units, and m is not less than 1, the emitter of the transistor B1 is connected with the emitter of the transistor B2 and the drain of the transistor Md1, and the collector of the transistor B1 is connected with the source of the transistor Ms1;

[0114] The base of the transistor B2 is connected with the input signal input terminal OUT1N, the base of the transistor B4, the base of the transistor B6, and the base of the transistor B2m, respectively, wherein m is not less than 1, and the collector of the transistor B2 is connected with the source of the transistor Ms2;

[0115] The gate of the transistor Ms1 is connected with the coarse adjustment control signal Vsw1 and the gate of the transistor Ms2, respectively, the gate of the transistor Ms3 is connected with the coarse adjustment control signal Vsw2 and the gate of the transistor Ms4, respectively, and the gate of the transistor Ms2m-1 is connected with the coarse adjustment control signal Vswm and the gate of the transistor Ms2m, respectively, wherein m is not less than 1;

[0116] The drain of the transistor Ms1 is connected with the output signal output terminal OUTN, the drain of the transistor Ms3, the drain of the transistor Ms5, the drain of the transistor Ms2m-1, and the first end of the resistor RL3, respectively, wherein m is not less than 1;

[0117] The drain of the transistor Ms2 is connected with the output signal output terminal OUTP, the drain of the transistor Ms4, the drain of the transistor Ms6, the drain of the transistor Ms2m, and the first end of the resistor RL4, respectively, wherein m is not less than 1;

[0118] The emitter of the transistor B3 is connected with the emitter of the transistor B4 and the drain of the transistor Md2, respectively, and the collector of the transistor B3 is connected with the source of the transistor Ms3;

[0119] The collector of the transistor B4 is connected with the source of the transistor Ms4;

[0120] The emitter of the transistor B2m-1 is connected with the emitter of the transistor B2m and the drain of the transistor Mdm, respectively, and the collector of the transistor B2m-1 is connected with the source of the transistor Ms2m-1, wherein m is not less than 1;

[0121] The collector of the transistor B2m is connected with the source of the transistor Ms2m, wherein m is not less than 1;

[0122] The source of the transistor Md1 is connected with the negative power voltage input terminal VEE, the source of the transistor Md2, the source of the transistor Md3, and the source of the transistor Mdm, respectively, wherein m is not less than 1;

[0123] The second end of the resistor RL3 is connected with the first end of the inductor L3;

[0124] The second end of the resistor RL4 is connected with the first end of the inductor L4;

[0125] The second end of the inductor L3 is connected with the positive power voltage input terminal VDD and the second end of the inductor L4, respectively;

[0126] The gate of transistor Md1 is connected with fine control signal Vd1, the gate of transistor Md2 is connected with fine control signal Vd2, and the gate of transistor Mdm is connected with fine control signal Vdm, which is provided externally.

[0127] An additional zero point is introduced in the circuit through the inductors L3 and L4, thereby improving the bandwidth of the circuit. The advantage is that the bandwidth expansion structure only needs to be arranged on the load resistor, without adding complex structures in the driving unit, which is more suitable for the large-swing adjustable output stage circuit designed in the present application.

[0128] Further, the transistors B2m-1, B2m, Mdm, Ms2m-1 and Ms2m form an output stage unit, where m is not less than 1, and the large-swing adjustable output stage circuit comprises at least one output stage unit.

[0129] When the transistor B2m-1 is in the amplification zone, its collector current I C is:

[0130]

[0131] where I S is a constant used to describe the transmission characteristics of the transistor in the forward amplification zone, V BE is the base-emitter voltage of the transistor, and V T is the threshold voltage of the transistor. Thus, the transconductance of the transistor B2m-1 can be derived as:

[0132]

[0133] where α is the amplification factor of the transistor. It can be seen that the transistor transconductance g m is proportional to the emitter current I E , and the gain of the output stage unit is proportional to the transistor transconductance. Therefore, when the output signal swing is adjusted by adjusting the size of the tail current source transistor Mdm current to adjust the gain of the output stage unit and then adjust the output signal swing, the output signal swing is linearly related to the total tail current size of the output stage unit turned on in the large-swing adjustable output stage circuit.

[0134] As the two ways to adjust the total tail current size, coarse and fine adjustment jointly determine the number of bits of the output signal swing adjustment, i.e. the number of bits of the output signal swing adjustment of the high-precision adjustable large-swing range integrated multi-channel driving circuit is equal to the sum of the coarse adjustment bits and the fine adjustment bits of the large-swing adjustable output stage circuit.

[0135] The output signal swing coarse adjustment of the rear-stage large swing adjustable output stage circuit is realized by the on-off control of the control transistor through the coarse adjustment switch control signal Vswm, wherein m is not less than 1, and the value of the coarse adjustment bit number q is the floor of log2m.

[0136] The high-precision adjustable large swing range integrated multi-channel drive circuit adopts a BiCMOS process, wherein the front-stage gain adjustable circuit realizes gain deviation calibration through an improved Gilbert cell circuit structure, and is compatible with multi-channel integration function. In addition, the rear-stage large swing adjustable output stage circuit realizes an output signal swing range of 3.0V through a current mode logic circuit that controls the on-off of the tail current source through a switch, and realizes the fine adjustment resolution of the output signal swing to be less than 0.2mV through the continuous adjustment of the tail current source of the current mode logic circuit within a certain range by an integrated 14bit digital-to-analog converter circuit. The high-precision adjustable large swing range integrated multi-channel drive circuit has the advantages of large output swing, high adjustable precision, calibratable gain and multi-channel integration. Meanwhile, the circuit uses inductance peaking technology and capacitance degeneration technology to expand the bandwidth, and can be applied to high-speed and high-precision systems.

[0137] It can be understood that the present application is described through some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the present application without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.

Claims

1. A high-precision adjustable large swing range integrated multi-channel drive circuit, characterized in that, include: Pre-amplifier gain adjustable circuit and post-amplifier large swing adjustable output stage circuit; The adjustable gain circuit is used to calibrate gain deviation and realize multi-channel integration function. The adjustable gain circuit is composed of a cross-coupled gain adjustment module connected in series with one or more parallel input stage units. The cross-coupled gain adjustment module consists of transistors and load resistors. Two sets of parallel differential pairs of transistors form a cross-coupled structure and are connected in series with a pair of parallel load resistors. The calibration function control signal controls the gain of the cross-coupled gain adjustment module to achieve the gain deviation calibration function; The input stage unit consists of transistors, resistors, and capacitors, wherein the resistors and capacitors are connected in parallel and across a set of parallel differential pairs of transistors, and are connected in series with the tail current source transistor. The pre-stage gain adjustable circuit is composed of a cross-coupled gain adjustment module connected in series with multiple parallel input stage units; The channel selection switch control signal controls the on / off state of the transistor to achieve the channel selection function; the output signal terminals OUT1P and OUT1N of the pre-stage gain adjustable circuit are connected to the input signal terminals of the subsequent large swing adjustable output stage circuit. The large-swing adjustable output stage circuit is used to realize a wide range of high-precision adjustable output signal swing. The large-swing adjustable output stage circuit is composed of a pair of parallel resistors connected in series with one or more parallel current-mode logic output stage units. The current-mode logic output stage unit is composed of transistors, in which transistors are connected in parallel to form a differential pair structure and connected in series with the tail current source transistor. The input signal input terminals OUT1P and OUT1N are connected to the output signal output terminals of the pre-amplifier gain adjustable circuit; the external coarse adjustment control signal controls the on / off state of the transistor to achieve coarse adjustment of the output signal swing over a wide range; the external fine adjustment control signal Vdm is provided by the external digital-to-analog converter circuit; the fine adjustment control signal Vdm controls the on / off state of the tail current transistor to achieve fine adjustment of the output signal swing.

2. The high-precision adjustable large swing range integrated multi-channel drive circuit according to claim 1, characterized in that, The cross-coupled gain adjustment module consists of transistors QG1, QG2, QG3, and QG4, as well as resistors RL1 and RL2. The base of transistor QG1 is connected to the calibration function control signal input terminal VcN and the base of transistor QG4, respectively. The collector of transistor QG1 is connected to the output signal output terminal OUT1N, the collector of transistor QG3 and the first terminal of resistor RL1, respectively. The emitter of transistor QG1 is connected to the emitter of transistor QG2, the collector of transistor Q1, the collector of transistor Q3, the collector of transistor Q5 up to the collector of transistor Q2n-1, where n is the number of input stage units and n is not less than 1. The base of transistor QG2 is connected to the calibration function control signal input terminal VcP and the base of transistor QG3, respectively. The collector of transistor QG2 is connected to the output signal output terminal OUT1P, the collector of transistor QG4 and the first terminal of resistor RL2, respectively. The emitter of transistor QG3 is connected to the emitter of transistor QG4, the collector of transistor Q2, the emitter of transistor QG4, the collector of transistor Q4, the collector of transistor Q6, and finally the collector of transistor Q2n, where n is not less than 1. The input stage unit consists of transistors Q1, Q2, M1, M2, Mb1, Mb2, Mb3, capacitor C1, and resistor R1, specifically including: The base of transistor Q1 is connected to the input signal input terminal IN_CH1P of channel one. The emitter of transistor Q1 is connected to the first terminal of capacitor C1, the first terminal of resistor R1, and the drain of transistor M1. The collector of transistor Q1 is connected to the emitter of transistor QG1, the emitter of transistor QG2, the collector of transistor Q3, the collector of transistor Q5, and so on up to the collector of transistor Q2n-1, where n is not less than 1. The base of transistor Q2 is connected to the input signal input terminal IN_CH1N of channel one. The emitter of transistor Q2 is connected to the second terminal of capacitor C1, the second terminal of resistor R1, and the drain of transistor M2. The collector of transistor Q2 is connected to the emitter of transistor QG3, the emitter of transistor QG4, the collector of transistor Q4, the collector of transistor Q6, and finally the collector of transistor Q2n, where n is not less than 1. The gate of transistor M1 is connected to the selection control signal Vch1 and the gate of transistor M2, respectively. The gate of transistor M3 is connected to the selection control signal Vch2 and the gate of transistor M4, respectively. The gate of transistor M2n-1 is connected to the selection control signal Vchn and the gate of transistor M2n, respectively. The source of transistor M1 is connected to the drain of transistor Mb2. The source of transistor M2 is connected to the drain of transistor Mb3; The base of transistor Q3 is connected to the input signal terminal IN_CH2P of channel 2, and the emitter of transistor Q3 is connected to the first terminal of capacitor C2, the first terminal of resistor R2, and the drain of transistor M3, respectively. The base of transistor Q4 is connected to the input signal terminal IN_CH2N of channel 2, and the emitter of transistor Q4 is connected to the second terminal of capacitor C2, the second terminal of resistor R2, and the drain of transistor M4, respectively. The source of transistor M3 is connected to the drain of transistor Mb5; The source of transistor M4 is connected to the drain of transistor Mb6; The base of transistor Q2n-1 is connected to the input signal input terminal IN_CHnP of channel n. The emitter of transistor Q2n-1 is connected to the first terminal of capacitor Cn, the first terminal of resistor Rn and the drain of transistor M2n-1, respectively, where n is not less than 1. The base of transistor Q2n is connected to the input signal input terminal IN_CHnN of channel n, and the emitter of transistor Q2n is connected to the second terminal of capacitor Cn, the second terminal of resistor Rn and the drain of transistor M2n, respectively, where n is not less than 1; The source of transistor M2n-1 is connected to the drain of transistor Mb3n-1, where n is not less than 1; The source of transistor M2n is connected to the drain of transistor Mb3n, where n is not less than 1; The gate of transistor Mb1 is connected to the drain of transistor Mb1, the bias current input terminal I1, the gate of transistor Mb2, and the gate of transistor Mb3, respectively. The gate of transistor Mb4 is connected to the drain of transistor Mb4, the bias current input terminal I2, the gate of transistor Mb5, and the gate of transistor Mb6, respectively. The gate of transistor Mb3n-2 is connected to the drain of transistor Mb3n-2, the bias current input terminal In, the gate of transistor Mb3n-1, and the gate of transistor Mb3n, respectively. The source of transistor Mb1 is connected to the negative power supply voltage input terminal VEE, the source of transistor Mb2, the source of transistor Mb3, and finally the source of transistor Mb3n. The second terminal of resistor RL1 is connected to the first terminal of inductor L1; The second terminal of resistor RL2 is connected to the first terminal of inductor L2; The second terminal of inductor L1 is connected to the positive power supply voltage input terminal VDD and the second terminal of inductor L2, respectively. The values ​​of capacitors C1, C2, and up to C2n are adjustable to provide different levels of emphasis.

3. The high-precision adjustable large swing range integrated multi-channel drive circuit according to claim 1, characterized in that, The current-mode logic output stage unit includes transistors B1, B2, Ms1, Ms2, and Md1, specifically comprising: The base of transistor B1 is connected to the input signal input terminal OUT1P, the base of transistor B3, the base of transistor B5, and the base of transistor B2m-1, respectively, where m is the number of current-mode logic output stage units and m is not less than 1. The emitter of transistor B1 is connected to the emitter of transistor B2 and the drain of transistor Md1, respectively, and the collector of transistor B1 is connected to the source of transistor Ms1. The base of transistor B2 is connected to the input signal input terminal OUT1N, the base of transistor B4, the base of transistor B6 and up to the base of transistor B2m, where m is not less than 1. The collector of transistor B2 is connected to the source of transistor Ms2. The gate of transistor Ms1 is connected to the coarse adjustment control signal Vsw1 and the gate of transistor Ms2, respectively. The gate of transistor Ms3 is connected to the coarse adjustment control signal Vsw2 and the gate of transistor Ms4, respectively. The gate of transistor Ms2m-1 is connected to the coarse adjustment control signal Vswm and the gate of transistor Ms2m, respectively, where m is not less than 1. The drain of transistor Ms1 is connected to the output signal output terminal OUTN, the drain of transistor Ms3, the drain of transistor Ms5, up to the drain of transistor Ms2m-1, and the first terminal of resistor RL3, where m is not less than 1. The drain of transistor Ms2 is connected to the output signal output terminal OUTP, the drain of transistor Ms4, the drain of transistor Ms6, up to the drain of transistor Ms2m, and the first terminal of resistor RL4, where m is not less than 1. The emitter of transistor B3 is connected to the emitter of transistor B4 and the drain of transistor Md2, respectively, and the collector of transistor B3 is connected to the source of transistor Ms3. The collector of transistor B4 is connected to the source of transistor Ms4; The emitter of transistor B2m-1 is connected to the emitter of transistor B2m and the drain of transistor Mdm, respectively, and the collector of transistor B2m-1 is connected to the source of transistor Ms2m-1, where m is not less than 1. The collector of transistor B2m is connected to the source of transistor Ms2m, where m is not less than 1; The source of transistor Md1 is connected to the negative power supply voltage input terminal VEE, the source of transistor Md2, the source of transistor Md3, and finally the source of transistor Mdm, where m is not less than 1. The second terminal of resistor RL3 is connected to the first terminal of inductor L3; The second terminal of resistor RL4 is connected to the first terminal of inductor L4; The second terminal of inductor L3 is connected to the positive power supply voltage input terminal VDD and the second terminal of inductor L4, respectively. The gate of transistor Md1 is connected to the fine-tuning control signal Vd1, the gate of transistor Md2 is connected to the fine-tuning control signal Vd2, and the gate of transistor Mdm is connected to the fine-tuning control signal Vdm, which is provided externally.

4. The high-precision adjustable large swing range integrated multi-channel drive circuit according to claim 1, characterized in that, The high-precision adjustable large swing range integrated multi-channel drive circuit is implemented using BiCMOS technology.

5. The high-precision adjustable large swing range integrated multi-channel drive circuit according to claim 3, characterized in that, When transistor B2m-1 is in the amplification region, its collector current I C for: Among them, I S V is a constant used to describe the transfer characteristics of a transistor in the forward amplification region. BE V is the base-emitter voltage of the transistor. T Given the threshold voltage of the transistor, the transconductance of transistor B2m-1 is derived as follows: Where α is the transistor amplification factor, and g is the transistor transconductance. m With emitter current I E The gain of the output stage unit is directly proportional to the transconductance of the transistor. Therefore, when the gain of the output stage unit is adjusted by adjusting the magnitude of the tail current source transistor Mdm, and thus the output signal swing is adjusted, the output signal swing is linearly related to the magnitude of the total tail current of the output stage unit in the subsequent large-swing adjustable output stage circuit. The high-precision adjustable large swing range integrated multi-channel drive circuit has an output signal swing that is adjustable in number of bits, which is equal to the sum of the coarse adjustment bits and fine adjustment bits of the subsequent large swing adjustable output stage circuit.

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