Double-loop digital LDO circuit
By designing a dual-loop digital LDO circuit, and utilizing a combination of coarse and fine adjustment loops for dynamic adjustment and a segmented binary method, the response speed and voltage stability issues of traditional digital LDO circuits under load changes are solved, achieving fast and stable output voltage control.
Patent Information
- Application Number
- CN202511184751.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-22
- Publication Date
- 2025-11-25
AI Technical Summary
Traditional digital LDO circuits cannot respond quickly to sudden load changes, resulting in output voltage overshoot or undershoot, and increasing the load capacitance will increase the circuit area cost.
It adopts a dual-loop structure, including a coarse adjustment loop and a fine adjustment loop. It monitors voltage fluctuations in real time through a comparator array and uses a digital logic controller for dynamic adjustment and a segmented binary method to quickly respond to load changes and stabilize the output voltage.
It achieves fast transient response and stable output voltage, avoids overshoot and dive problems, and reduces circuit area cost.
Smart Images
Figure CN121008646A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit power management technology, and specifically to a dual-loop digital LDO circuit. Background Technology
[0002] Power management chips are a key component of System-on-Chips (SoCs), primarily responsible for providing stable DC voltages to various functional modules. As the operating frequency of SoC chips continues to increase, the requirements for transient response in power modules are also gradually increasing.
[0003] Low dropout regulators (LDOs) are an important power management solution widely used in portable electronic devices. Traditional analog LDOs offer fast transient response and high power supply rejection ratio (PSRR), but in low-voltage operating environments, the gain-bandwidth performance of the analog LDO error amplifier drops sharply, failing to meet the requirements of low-voltage designs. Therefore, digital LDO circuits, as a new technology, use a voltage quantizer to convert the error between the reference voltage and the output voltage into a digital signal, and use this signal to adjust the operating state of the power transistor switches, thereby achieving a stable output voltage.
[0004] Transient response speed and transient boost are two important performance indicators of digital LDO circuits, reflecting their ability to respond to sudden load changes. Transient recovery time is mainly affected by the power transistor control method and clock frequency. Traditional digital LDO circuits typically use a single-step linear adjustment method, adjusting the conduction state of only one power transistor per clock cycle. To achieve faster transient response, a higher frequency clock signal is often required. However, the magnitude of the transient voltage is mainly affected by the load capacitance and the sudden change in load current. When the load current changes drastically, the power transistor may fail to respond in time, leading to rapid discharge or accumulation of charge on the load capacitor, resulting in voltage overshoot or dip. This phenomenon can adversely affect subsequent circuits. Although increasing the load capacitance can effectively suppress transient voltage fluctuations, large-capacity capacitors are not suitable for integration into the chip, and increasing external capacitance significantly increases the circuit's area cost. Therefore, achieving a shorter transient recovery time and effectively suppressing the amplitude of transient voltage remains a major challenge in the design of integrated digital LDO circuits. Summary of the Invention
[0005] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a dual-loop digital LDO circuit, including a comparator array, a digital logic controller, a power transistor group, and a multi-stage current mirror circuit; wherein, the comparator array quantizes the error between the reference voltage and the output voltage into a digital signal, and detects the fluctuation of the output voltage relative to the reference voltage; based on the fluctuation, it is determined whether the dual-loop digital LDO circuit is in transient adjustment mode. If it is in transient adjustment mode, the coarse adjustment loop and the fine adjustment loop in the digital logic controller are triggered sequentially to control the output voltage to stabilize; the power transistor group includes two sets of PMOS switches, which are respectively set in the coarse adjustment loop and the fine adjustment loop; the multi-stage current mirror circuit replicates the changing load current and activates the power transistors in the coarse adjustment loop according to the fluctuation of the output voltage relative to the reference voltage, and the size of each current mirror is the same as the size of the power transistors in the coarse adjustment loop.
[0006] Preferably, the dual-loop digital LDO circuit of the present invention improves the response speed of the system-on-chip (SoC) under sudden load changes through reasonable structural design, and effectively reduces the fluctuation of output voltage, thereby achieving more stable performance.
[0007] The comparator array includes comparators A, B, C, D, and E connected in parallel. The negative inputs of comparators A, B, C, D, and E are connected to the output voltage VOUT of the dual-loop digital LDO circuit, respectively. Their positive inputs are connected to reference voltages V1, V2, V3, V4, and V5, respectively. Their clock inputs are connected to the sampling clock CLK.
[0008] Comparators A, B, and C employ a cascode structure to provide high-precision voltage comparison. Through this high-precision current and voltage monitoring structure, comparators A and B can accurately reflect the voltage fluctuations of the dual-loop digital LDO circuit and provide feedback information to the control logic to determine whether to open or close the coarse adjustment loop. Comparator C also needs to provide feedback information to the digital logic controller to determine whether the fine adjustment loop is open.
[0009] The D and E comparators use a common-source amplifier (NMOS). The common-source structure uses the output signals of the D comparator and the E comparator as the outputs during fine-tuning loop adjustments. These signals are closely connected to the digital logic controller, further improving voltage detection accuracy and response speed. Through the cooperation of these comparators, the dual-loop digital LDO circuit can perform precise voltage adjustments during transient changes.
[0010] Preferably, the comparator array in this invention can help the dual-loop digital LDO circuit monitor and quantify the error between the output voltage VOUT and each reference voltage in real time, and convert the error between the voltages into a digital signal, thereby controlling the output voltage of the dual-loop digital LDO circuit and ensuring output stability.
[0011] Digital logic controllers include shift registers, coarse control controllers, and fine control controllers.
[0012] The power transistor group includes two sets of PMOS switches. The first set of PMOS switches is located in the coarse adjustment loop and consists of four PMOS switches connected in parallel. The second set of PMOS switches is located in the fine adjustment loop and consists of sixteen PMOS switches connected in parallel.
[0013] Preferably, the output signals of the comparator array are input to a shift register and a coarse adjustment controller, respectively. One output terminal of the shift register is connected to the input terminal of the fine adjustment controller, and the signal input terminals of the second set of PMOS switches are connected to the output terminal of the fine adjustment controller. The input terminal of the coarse adjustment controller is connected to comparators A and B to determine whether to turn the coarse adjustment controller on or off. The signal input terminal of the first set of PMOS switches is connected to the output terminal of the coarse adjustment controller to control the power transistor in the coarse adjustment loop.
[0014] The control signals of the digital logic controller include N control bits (N is an integer greater than 1), which are mainly used to fine-tune the loop by adjusting the number of PMOS switches in the second group using a segmented binary method. Specifically, the entire digital logic controller determines whether to enter transient adjustment mode based on the output voltage fluctuation information fed back by the comparator array, and switches between coarse and fine adjustment to control the output voltage to recover to the predetermined stable value.
[0015] The coarse adjustment loop responds to load current changes dynamically and pre-determines whether to turn on or off the first group of PMOS switches based on load current changes to control the output voltage within a specified range. The fine adjustment loop, building upon the coarse adjustment loop, uses a segmented binary method to control the number of PMOS switches in the second group to finely adjust the voltage and output a stable voltage.
[0016] Preferably, in the fine-tuning loop of this invention, the source terminal of each PMOS switch is connected to the input voltage Vin of the dual-loop digital LDO circuit, and the drain terminal is connected to the output voltage VOUT, which enables rapid feedback adjustment at the end of the coarse-tuning loop; the size ratio of the power transistor group in the coarse-tuning loop is 128:64:32:16, with one of each size in total, and four power transistor groups in the fine-tuning loop with a size ratio of 1 in each size, totaling 16.
[0017] In the dual-loop digital LDO circuit, when the dual-loop digital LDO circuit is in the fine-tuning loop reference voltage range, only the fine-tuning loop is working; when the dual-loop digital LDO circuit enters the transient adjustment mode, after the coarse-tuning loop finishes working preferentially, the fine-tuning loop starts to work again; when the dual-loop digital LDO circuit completely returns to the steady state mode, all PMOS switches will be turned off.
[0018] The working principle of the dual-loop digital LDO circuit is that, under normal conditions, the digital logic controller will monitor the change of the output voltage in real time through the shift register and the control logic. When the load changes suddenly, the output voltage VOUT will fluctuate greatly and may exceed the predetermined voltage range (V5 < VOUT < V3), where V3 and V5 are reference voltages. At this time, the dual-loop digital LDO circuit enters the transient adjustment mode to activate the coarse-tuning loop. First, the logic controller quickly determines the number of PMOS switches to be turned on through the coarse-tuning loop, and selects a large step size to adjust the conduction number of the PMOS switches according to the change amplitude of the load current (ΔIload), so as to quickly return the output voltage to the stable range (V5 < VOUT < V3).
[0019] After the coarse-tuning loop completes the preliminary adjustment, the system-on-chip SoC will enter the fine-tuning loop and perform fine adjustment through the segmented dichotomy method. The fine-tuning controller gradually adjusts the conduction number of the PMOS switches according to the difference between the output voltage VOUT and the target voltage V4, and precisely restores the voltage to the target value. If the output voltage VOUT is lower than the target value, the fine-tuning controller will increase the conduction number of the PMOS switches; if the output voltage VOUT is higher than the target value, the fine-tuning controller will reduce the conduction number of the PMOS switches. Through this detailed step-by-step adjustment, the output voltage is finally stabilized near the set target value.
[0020] When the load changes suddenly, the coarse-tuning loop will determine the number of power transistors in the coarse-tuning loop to be turned on according to the copied load current, and this adjustment process is dynamic. When there is a mutation, the dual-loop digital LDO circuit can quickly respond by using the dynamic segmented adjustment method. The coarse-tuning loop provides a large step size adjustment to quickly restore the voltage, while the fine-tuning loop ensures the stability of the voltage through fine adjustment. Combining these two adjustment methods, the dual-loop digital LDO circuit can quickly return to stability in the transient response, maintain good steady-state performance, avoid the secondary dive of the output voltage, and ensure the stable operation of the system-on-chip SoC when the load changes suddenly.
[0021] This invention proposes a dual-loop digital LDO circuit design, including a coarse adjustment loop and a fine adjustment loop. This design enables rapid response to load changes through the coarse adjustment loop, immediately adjusting the switching state of the power transistors during sudden load changes. The fine adjustment loop further refines the adjustment using a segmented binary method, ensuring precise and stable output voltage. This dual-loop structure effectively solves the problems of slow transient response and excessive transient voltage amplitude, allowing the dual-loop digital LDO circuit to stabilize the output voltage more quickly and accurately under drastic load changes, avoiding overshoot and undershoot issues found in traditional designs.
[0022] Compared with the prior art, the present invention has the following advantages: (1) The present invention adopts a hybrid scheme of segmented binary method and dynamic adjustment method as the core control scheme of dual-loop digital LDO circuit. After the load changes suddenly, the logic controller can control the number of PMOS switches that are currently turned on, quickly determine the current load range, and then make fine adjustments. It has the advantages of fewer adjustment steps and shorter transient response time.
[0023] (2) The present invention adopts a multi-stage current mirror circuit. The size of each current mirror is the same as the size of the power transistor in the coarse adjustment loop to ensure that when the load current changes, the replicated current will not have a large error, thereby causing the power transistor to turn on or off incorrectly. The ability to improve transient response by replicating the load current can effectively reduce the amplitude of the output voltage drop. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the transient enhancement dual-loop digital LDO circuit in the embodiment; Figure 2 This is a schematic diagram of the current mirror circuit structure of the coarse adjustment loop in the embodiment; Figure 3 This is a schematic diagram of the segmented binary adjustment process in the embodiment; Figure 4 The above are comparison curves of the load transient response characteristics of the dual-loop digital LDO circuit in this embodiment. Detailed Implementation
[0025] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0026] The following detailed description is exemplary and intended to provide further detailed explanation of the invention. Unless otherwise specified, all technical terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this invention is for describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention.
[0027] This embodiment provides a dual-loop digital LDO circuit, such as Figure 1 As shown, it includes a comparator array, a digital logic controller, a power transistor bank, and a multi-stage current mirror circuit. The comparator array quantizes the error between the reference voltage and the output voltage into a digital signal, detecting the fluctuation of the output voltage relative to the reference voltage. Based on the fluctuation, it determines whether the dual-loop digital LDO circuit is in transient adjustment mode. If it is in transient adjustment mode, the coarse adjustment loop and fine adjustment loop in the digital logic controller are triggered sequentially to stabilize the output voltage. The power transistor bank includes two sets of PMOS switches, respectively located in the coarse adjustment loop and the fine adjustment loop. Figure 2 As shown, the multi-stage current mirror circuit activates the power transistors in the coarse adjustment loop according to the changes in the replicated load current. The size of each current mirror is the same as the size of the power transistors in the coarse adjustment loop.
[0028] The comparator array includes comparators A, B, C, D, and E connected in parallel. The negative inputs of comparators A, B, C, D, and E are connected to the output voltage VOUT of the dual-loop digital LDO circuit, respectively. Their positive inputs are connected to reference voltages V1, V2, V3, V4, and V5, respectively, and their clock inputs are connected to the sampling clock. The comparators quantize the error between the reference voltages V1, V2, V3, V4, and V5 and the output voltage VOUT into digital signals, thereby controlling the output voltage of the dual-loop digital LDO circuit.
[0029] Comparators A, B, and C use a cascode structure, while comparators D and E use a common-source NMOS structure.
[0030] The digital logic controller includes a shift register, a coarse-tuning controller, and a fine-tuning controller. The output of the fine-tuning controller is connected to the signal input of the fine-tuning loop power transistor group, while the output of the coarse-tuning controller is connected to the signal input of the coarse-tuning loop power transistor.
[0031] The coarse adjustment loop responds to load current changes through dynamic adjustment and pre-determines whether to start or stop the switch based on load current changes to control the output voltage within a specified range. For example... Figure 4As shown in the figure, specifically, the coarse-tuning controller adopts the dynamic adjustment method. It predicts the number of switches to be turned on or off in the coarse-tuning loop according to the change of the load current, and dynamically controls the turn-off of the power transistors in the coarse-tuning loop to ensure that no power transistor to be turned off is still on during segmented adjustment. Thus, the conduction number of PMOS switches is dynamically adjusted to achieve fast transient response.
[0032] Based on the adjustment of the coarse-tuning loop, the fine-tuning loop uses the segmented binary search method to control the conduction number of PMOS switches to finely adjust the voltage and output a stable voltage. Specifically, the fine-tuning controller continues to use the segmented binary search method to finely adjust the voltage output. Among them, comparator A and comparator B are connected to the coarse-tuning controller. The output signals of comparator C, comparator D, and comparator E are respectively connected to the input terminals of the shift register. One output terminal Y[15:0] of the shift register is connected to the input terminal of the fine-tuning controller. The output terminal G[15:0] of the fine-tuning controller is connected to the signal input terminals of the power transistor group in the fine-tuning loop.
[0033] The power transistor group includes two groups of PMOS switches. The first group of PMOS switches in the coarse-tuning loop consists of 4 parallel PMOS switches, and the second group of fine-tuning loops consists of 16 parallel PMOS switches. Among them, the gates of the first group of power transistors are connected to the output terminal of the coarse-tuning controller in the digital logic control, and the gates of the second group of power transistors are connected to the output terminal of the fine-tuning controller. The sources of the first group of power transistors are connected to the input terminal of the current mirror, and the sources of the second group of power transistors are directly connected to Vin. The drains of the first group of power transistors are connected to the load and then grounded, and the drains of the second group of power transistors are grounded.
[0034] In the dual-loop digital LDO circuit, when the dual-loop digital LDO circuit is in the fine-tuning loop reference voltage range, only the fine-tuning loop is working; when the dual-loop digital LDO circuit enters the transient adjustment mode, after the coarse-tuning loop works preferentially and ends, the fine-tuning loop starts to work again; when the dual-loop digital LDO circuit completely returns to the steady-state mode, all PMOS switches will be turned off.
[0035] The working principle of the dual-loop digital LDO circuit is that when the dual-loop digital LDO circuit is working, the coarse-tuning controller in the digital logic controller enters the working state preferentially, judges whether there is a replicated current that can activate the power transistors in the coarse-tuning loop. After the coarse-tuning loop finishes working, it pulls the output voltage into the range of V5 < VOUT < V3. Only n-bit control signals in the fine-tuning controller are in the active state, where n is an integer less than 16, and the remaining bit control signals are in the high-level turn-off state; when only the fine-tuning loop of the dual-loop digital LDO circuit is working, at this time it is in the range of V5 < VOUT < V3. In each clock cycle, the least significant bit of the n-bit control signal performs addition and subtraction operations, and the fluctuation amplitude of the output voltage VOUT is the voltage amplitude generated by the PMOS switch corresponding to the least significant bit. Finally, the output voltage is adjusted to the target voltage V4.
[0036] During the operation of the dual-loop digital LDO circuit, the comparator detects the fluctuation of the output voltage VOUT relative to the reference voltage: If the output voltage V2 < VOUT < V1, where V1 and V2 are reference voltages, the output signals of the comparator arrays A and B activate the coarse-tuning loop, indicating that the digital LDO is in the transient adjustment mode. At this time, the digital logic controller triggers the dynamic adjustment method in the coarse-tuning loop. By copying the change of the load current through the current mirror and combining with the coarse-tuning controller to predict in advance the number of switches to be turned on or off in the coarse-tuning loop, the conduction number of the PMOS switches in the coarse-tuning loop is quickly changed; then it switches to the fine-tuning loop and still uses the segmented binary search method for adjustment to quickly achieve voltage stabilization.
[0037] Device selection for the coarse-tuning loop: In the coarse-tuning loop, a PMOS switch array with a size ratio of 128:64:32:16 times that of the fine-tuning loop is used to adjust the switch state of the coarse-tuning loop. The coarse-tuning loop uses the dynamic adjustment method to pre-judge the conduction of starting or closing the switch according to the change of the load current, and quickly responds to the load change. The switch array in the coarse-tuning loop uses high-power metal-oxide-semiconductor field-effect transistors MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) to handle larger currents. These switches dynamically adjust the number according to the change of the load, and these switches do not work simultaneously with the switches in the fine-tuning loop.
[0038] When the transient adjustment mode occurs and the output voltage is within the range of V2 < VOUT < V1, the comparator at this time will feedback the signal to the coarse-tuning controller in the digital logic controller. The power transistors in the coarse-tuning loop judge which power transistor to open first according to the load current copied by the current mirror. The set value of V1 is less than or equal to the sum of the voltages provided by the four power transistors, ensuring that the maximum adjustment range will not be exceeded. Therefore, when the coarse-tuning loop is activated, after the power transistor with a size of 128 is turned on, the remaining power transistors will all be turned on. Similarly, after the large-size power transistors are turned on, the smaller-size power transistors will also be turned on synchronously. And so on until the current copied by the current mirror is not enough to turn on the power transistor with the smallest size of 16 in the coarse-tuning loop, and then the operation of the coarse-tuning loop ends. The voltage enters the range of V5 < VOUT < V3, and the C comparator, D comparator, and E comparator activate the fine-loop controller. Subsequently, the fine-tuning controller and the shift register start to work and activate the fine-tuning loop.
[0039] The fine-tuning loop continues to use the piecewise binary search method to control the number of turned-on PMOS switches. The fine-tuning controller makes step-by-step adjustments by comparing the difference between the output voltage and the reference voltage. Each binary operation is based on the error between the current output voltage and the target voltage. By gradually increasing or decreasing the number of turned-on PMOS switches, the voltage is finely adjusted to ensure the stability of the output voltage.
[0040] When the circuit enters the fine-tuning loop, the piecewise binary search method is used to further finely adjust the control signal to achieve precise output voltage stability. In the initial stage, calculate the initial change in the number of turned-on switches Y = N / 2^i, where N is the total number of power transistors, Y is the change in the number of turned-on power transistors, and i is the step factor. Then, the D comparator is used to judge the magnitude relationship between the output voltage VOUT and the reference voltage V4. If VOUT is less than V4, it means the voltage is too low, and the number of turned-on PMOS switches needs to be increased to raise the output voltage. Conversely, if VOUT is greater than V4, the number of turned-on PMOS switches needs to be reduced to lower the output voltage. After judging the relationship between VOUT and V4, then compare the number of turned-on switches Z with the initial change in the number of turned-on switches Y. If Z - Y>0, it means the current number of turned-on switches Z is greater than the initial change in the number of turned-on switches Y. At this time, reduce Z by Y, that is, reduce the number of turned-on PMOS transistors. If this condition is not met, keep Z unchanged. Next, judge whether the condition for the end of the adjustment has been reached, that is, Z + Y<N. If the condition is met, continue to increase the number of turned-on switches Z and make adjustments until the set condition is reached. After each adjustment, the step factor i increases, that is, i = i + 1. As the step factor increases, each adjustment will be more refined, gradually improving the adjustment accuracy. When i reaches the maximum value the adjustment process ends, and VOUT stabilizes at the expected value, ensuring that the circuit accurately and quickly stabilizes at the target voltage.
[0041] The schematic diagram of the above piecewise binary adjustment process is as Figure 3 shown.
[0042] In this embodiment, the transient response of the digital LDO is optimized to reduce the dive amplitude of the output voltage VOUT. The specific process is as follows: When the digital LDO is in the fine-tuning loop reference voltage range, only the fine-tuning loop is working; but when the LDO just enters the transient adjustment mode, the coarse-tuning loop works first, and the two loops do not work simultaneously, effectively reducing the competition and mutual influence between the two loops. After the dual-loop digital LDO circuit completely returns to the steady-state mode, all PMOS switches are turned off.
[0043] The comparison curve of the load transient response characteristics of the dual-loop digital LDO circuit in this embodiment is as Figure 3As shown in the figure, the middle curve is the transient response curve of the dual-loop digital LDO after adding the hybrid scheme. Compared with the bottom response curve without the hybrid scheme, the undershoot and overshoot voltages of the entire digital LDO are effectively improved, the maximum recovery time is also significantly reduced, and the secondary dip of the input voltage is avoided at the same time. The transient response capability of the entire digital LDO is significantly improved after adding the hybrid scheme.
[0044] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or equivalent to the scope of this invention are included in this invention.
[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A dual-loop digital LDO circuit, characterized in that, The system includes a comparator array, a digital logic controller, a power transistor array, and a multi-stage current mirror circuit. The comparator array quantizes the error between the reference voltage and the output voltage into a digital signal, detecting fluctuations in the output voltage relative to the reference voltage. Based on these fluctuations, it determines whether the dual-loop digital LDO circuit is in transient adjustment mode. If in transient adjustment mode, it sequentially triggers the coarse adjustment loop and the fine adjustment loop in the digital logic controller to stabilize the output voltage. The power transistor array includes two sets of PMOS switches, respectively located in the coarse adjustment loop and the fine adjustment loop. The multi-stage current mirror circuit replicates the changing load current based on the fluctuations in the output voltage relative to the reference voltage and activates the power transistors in the coarse adjustment loop. The size of each current mirror is the same as the size of the power transistors in the coarse adjustment loop.
2. The dual-loop digital LDO circuit according to claim 1, characterized in that, The comparator array includes a parallel array of comparators A, B, C, D, and E.
3. The dual-loop digital LDO circuit according to claim 2, characterized in that, In the comparator array, the negative input terminals of comparators A, B, C, D, and E are respectively connected to the output voltage VOUT of the dual-loop digital LDO circuit, the positive input terminals are respectively connected to the reference voltages V1, V2, V3, V4, and V5, and the clock terminals are respectively connected to the sampling clock.
4. The dual-loop digital LDO circuit according to claim 2 or 3, characterized in that, The comparators A, B, and C adopt a cascode structure, while the comparators D and E adopt a common-source NMOS structure.
5. The dual-loop digital LDO circuit according to claim 1, characterized in that, The digital logic controller includes a shift register, a coarse adjustment controller, and a fine adjustment controller.
6. The dual-loop digital LDO circuit according to claim 1, characterized in that, The power transistor group includes two sets of PMOS switches. The first set of PMOS switches is located in the coarse adjustment loop and consists of four PMOS switches connected in parallel. The second set of PMOS switches is located in the fine adjustment loop and consists of sixteen PMOS switches connected in parallel.
7. The dual-loop digital LDO circuit according to claim 6, characterized in that, The signal input terminals of the first group of PMOS switches are connected to the output terminals of the coarse adjustment controller, and the signal input terminals of the second group of PMOS switches are connected to the output terminals of the fine adjustment controller.
8. The dual-loop digital LDO circuit according to claim 7, characterized in that, The coarse adjustment loop responds to changes in load current through a dynamic adjustment method, and pre-determines whether to turn on or off the first group of PMOS switches based on the changing load current in order to control the output voltage to enter a specified range.
9. The dual-loop digital LDO circuit according to claim 7, characterized in that, The fine-tuning loop, based on the coarse-tuning loop, uses a segmented binary method to control the number of PMOS switches in the second group to finely adjust and output a stable voltage.
10. The dual-loop digital LDO circuit according to claim 1, characterized in that, In the dual-loop digital LDO circuit, when the dual-loop digital LDO circuit is in the fine-tuning loop reference voltage range, only the fine-tuning loop is working; when the dual-loop digital LDO circuit enters the transient adjustment mode, the coarse-tuning loop finishes working first, and then the fine-tuning loop starts working again; when the dual-loop digital LDO circuit completely returns to the steady-state mode, all PMOS switches are turned off.