Method for optimizing virtual NVMe read-write performance through LRU algorithm and virtual NVMe system

Abstract

The invention provides a method for optimizing the read-write performance of a virtual NVMe through an LRU algorithm and a virtual NVMe system. The method comprises the steps that a cache management architecture with a hash table and a double linked list cooperating is constructed, cache nodes corresponding to SSD internal addresses are rapidly positioned through the hash table, and the access sequence of the SSD addresses is managed through the double linked list; when the NVMe performs SSD read-write operation, the LRU algorithm is called firstly, and if the address does not exist in the hash table, file read-write is executed; creating a linked list sequence adjusting thread when the LRU algorithm is initialized, brushing node data which is not accessed for the longest time and is beyond the linked list length to an SSD mirror image file, and deleting nodes; and when the read-write data is larger than the linked list node data, refreshing the Hash mapping. According to the method, the LRU algorithm is combined, the common SSD internal address and the corresponding data block are mapped, the memory is directly operated to read and write common data, the read-write mode of the existing virtual simulation NVMe is optimized, and then the performance of the virtual simulation NVMe in a virtual hardware system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer software, in particular to a method for optimizing virtual NVMe read-write performance through LRU algorithm and a virtual NVMe system. BACKGROUND

[0002] With the development of computer storage technology towards high speed and light weight, NVMe (Non-Volatile Memory Host Controller Interface Specification) has become one of the core technologies in the field of high-performance storage due to its low latency and high bandwidth. In virtualization, cloud computing and embedded simulation scenarios, virtual NVMe as a key component to simulate the function of physical NVMe hardware, its performance directly determines the overall running efficiency of the virtual hardware system, especially in data-intensive tasks (such as database interaction, high-frequency file read-write, virtual machine storage expansion), the requirement for read-write response speed of virtual NVMe is increasingly stringent.

[0003] The current mainstream virtual NVMe simulation technology generally adopts an implementation scheme of "relying on host read-write functions to directly operate SSD image files". The core logic of this scheme is that when the virtual NVMe executes a read-write request, it needs to call the file IO interface (such as read / write system call) of the host to perform data read-write on the pre-created SSD image file (i.e. a file simulating physical SSD storage medium), thereby completing the storage function simulation.

[0004] However, the above existing scheme has significant performance bottlenecks and is difficult to meet the use requirements in high-load scenarios, and the specific defects are as follows: 1. To simulate the storage capacity of a physical SSD, the SSD image file is usually a super large file of GB level or even TB level; in the existing scheme, each read-write request needs to open, operate and close the image file, and the frequent opening / closing operations of the operating system on the super large file will generate a large amount of IO waiting time, directly limiting the read-write response rate of the virtual NVMe.

[0005] 2. Lack of high-frequency data caching mechanism; the existing scheme does not perform special processing on the high-frequency accessed SSD address data, and if the same address data is repeatedly accessed (such as repeatedly reading the same configuration file, frequently updating the same data block), the process of "calling host function-reading image file" still needs to be repeatedly executed, causing redundant consumption of storage resources and further reducing the read-write efficiency.

[0006] 3. System performance is obviously dragged; due to the above two defects, the read and write performance of the existing virtual NVMe is far lower than that of the physical NVMe. In a high-concurrency read-write scenario, it will become a performance short board of the virtual hardware system - for example, in a multi-virtual machine concurrent running, high-frequency data interaction task, the delay of the virtual NVMe will be transmitted to the upper layer application, resulting in a significant decrease in the running efficiency of the whole system, which cannot meet the demand of actual application for storage performance.

[0007] In summary, due to the core design defect of "directly operating the SSD image file", the existing virtual NVMe simulation technology has the problems of obvious performance bottleneck and redundant resource consumption, and a technical solution capable of optimizing the read and write logic and reducing the IO overhead is urgently needed to improve the performance of the virtual NVMe in the virtual hardware system. SUMMARY

[0008] In view of the defects in the prior art, the purpose of the present application is to provide a method for optimizing the read and write performance of a virtual NVMe through an LRU algorithm and a virtual NVMe system.

[0009] According to the method for optimizing the read and write performance of a virtual NVMe through an LRU algorithm provided by the present application, the method comprises the following steps: The LRU algorithm construction step: a cache management architecture of a hash table and a double-linked list is constructed, the cache node corresponding to the internal address of the SSD is quickly located through the hash table, and the access order of the SSD address is managed through the double-linked list; The image read and write optimization step: if the SSD address to be read and written exists in the hash table, the read and write operation is selected to be performed from the cache node or the SSD image file according to the data size in the linked list and the data size of this time read and write; if the address does not exist in the hash table, the read and write operation is directly performed on the SSD image file; The performance optimization step: a linked list order adjustment thread is created when the LRU algorithm is initialized, the node data of the longest non-accessed node exceeding the length of the linked list is flushed to the SSD image file, and then the node is deleted; when the read and write data is greater than the data size of the linked list node, the hash mapping is refreshed.

[0010] Preferably, the data structure of the hash table and the double-linked list in the LRU algorithm construction step comprises: The key value of the hash table is set as the internal address of the SSD to be accessed, and the value is set as the memory pointer of the corresponding node in the double-linked list; each node of the double-linked list stores the internal address value of the SSD, the length of the data corresponding to the address, the memory storage area of the data, and the pointers pointing to the predecessor and successor nodes of the node.

[0011] Preferably, the access order of the SSD address managed through the double-linked list in the LRU algorithm construction step comprises: When the virtual NVMe accesses the SSD address, the address value, data length and corresponding data of the address are stored in the linked list node, independent memory space is allocated for the node, and the predecessor and successor pointers of the node are recorded; if the address is accessed again, the position of the node in the linked list is adjusted through the pointers.

[0012] Preferably, the LRU algorithm construction step further comprises: When the SSD address hits the cache node through the hash table, the node is moved from the current position to the head of the double-linked list, and the position adjustment is completed by modifying the predecessor and successor pointer relationship of the node.

[0013] Preferably, the LRU algorithm construction step further comprises: The maximum number of nodes of the double-linked list is set in advance to avoid high memory occupation or memory leakage; when the number of linked list nodes reaches the upper limit, the least recently accessed node located at the tail of the linked list is deleted, the memory occupied by the node is released, and the key-value pair of the corresponding SSD address in the hash table is deleted.

[0014] Preferably, the mirror read-write optimization step comprises: If the node of the target SSD address exists in the hash table, the relationship between the read-write data size and the node storage data size is judged: If it is a read operation and the required data size is less than or equal to the node storage data size, the corresponding length data is directly cut from the node memory area and returned; If it is a write operation and the required data size is less than or equal to the node storage data size, the data to be written is copied to the node memory area, and the node data is marked as "modified"; If the read-write data size is greater than the node storage data size, skip the cache, and perform read-write operation on the SSD mirror file through the host file IO interface; If the node of the target SSD address does not exist in the hash table, the SSD mirror file is operated through the host file IO interface, the read-write operation is completed, and it is judged whether to create a new node to join the cache according to the access frequency of the address. Only the node of the high-frequency access address is added to the cache.

[0015] Preferably, the performance optimization step comprises: creating an independent background thread when the LRU algorithm is initialized, the thread performs the sequential adjustment of the double-linked list, ensures that the "recently accessed" node is located at the head of the linked list, and the thread running does not affect the main read-write flow of the virtual NVMe.

[0016] Preferably, the performance optimization step further comprises: When the read / write data size is greater than the node storage data size during the image read / write optimization step, a hash mapping refresh is triggered. The hash table key value is kept at the original SSD address value. If it is a read operation, memory is re-allocated to store the complete data read from the file. If it is a write operation, memory is re-allocated to store the complete data to be written, and the node mapping between the hash table and the doubly linked list is updated.

[0017] Preferably, the performance optimization step further includes: A thread synchronization mechanism is set up to avoid data contention caused by background threads and the main read / write thread operating on cache nodes concurrently; at the same time, key read / write operation logs are recorded, which include SSD address values, data lengths and operation times, and are used to recover "modified" data that has not been flushed to disk after a system crash.

[0018] According to the present invention, a virtual NVMe system is provided, wherein the system adopts the method of optimizing virtual NVMe read and write performance through the LRU algorithm.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention combines the LRU algorithm and directly operates memory to read and write frequently used data by mapping commonly used SSD internal addresses and corresponding data blocks, thereby optimizing the existing virtual emulation NVMe read and write method and improving the performance of virtual emulation NVMe in virtual hardware systems.

[0020] 2. Current mainstream NVMe virtual emulation technology typically uses host machine read / write functions to perform read / write operations on the SSD image. This method requires frequently opening and closing the image file, and since these NVMe SSD images are generally very large files, frequent opening and closing of the file severely limits the NVMe's operating speed and significantly reduces the overall hardware system performance. This invention, by incorporating the LRU algorithm, can significantly improve the performance of virtual NVMe emulation. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a flowchart of the read / write process of NVMe after LRU optimization in this invention; Figure 2 This is a structural diagram of the LRU algorithm in this invention. Detailed Implementation

[0022] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0023] This invention discloses a method for optimizing the read / write performance of virtual NVMe using the LRU algorithm, referring to... Figure 1 and Figure 2 As shown, this method includes the following steps: LRU Algorithm Construction Steps: This step constructs a cache management mechanism for high-frequency data through the collaborative design of hash tables and doubly linked lists. The core is to quickly locate and maintain the access order of SSD addresses. The specific process is as follows: Step S1.1: Data Structure Construction; Construct the basic architecture of hash table and doubly linked list—the hash table is used to quickly find the cache node corresponding to the SSD address. Its key is set to the internal address of the SSD to be accessed, and the value is set to the memory pointer of the corresponding node in the doubly linked list; the doubly linked list is used to manage the access order of the address. Each linked list node needs to store four core pieces of information: the currently accessed SSD address value, the length of the data corresponding to the address, the memory storage area of ​​the data itself, and pointers to the predecessor and successor nodes of the node, ensuring that the node order can be quickly adjusted.

[0024] Step S1.2: Access management of doubly linked list; When the virtual NVMe accesses an SSD address, the address value, data length and corresponding data of the address are first stored in the linked list node, and an independent memory space is allocated for the node. At the same time, the predecessor and successor pointers of the node are recorded. For example, when a new address is accessed, it is created as a new node and connected to the linked list through the predecessor / successor pointers. If the address is accessed again later, the position of the node in the linked list can be directly adjusted through the pointers.

[0025] Step S1.3: Fast lookup configuration of hash table; using SSD address values ​​as hash table keys, hash calculation is used to map to the corresponding hash buckets to achieve fast location of linked list nodes; if different addresses are mapped to the same hash bucket (i.e. hash collision), the target address is matched by traversing the linked list within the bucket to ensure efficient execution of the lookup operation and avoid the impact of address lookup time on overall performance.

[0026] Step S1.4: Dynamic update of access order; When an SSD address hits a cache node through the hash table, the node needs to be moved from its current position to the head of the doubly linked list and marked as "recently accessed"; For example, a node that was originally located in the middle of the linked list can be repositioned to the head of the linked list by modifying the pointer relationship between its preceding and following nodes, so as to ensure that it can be obtained first when accessed frequently in the future.

[0027] Step S1.5: Constraint control of linked list length; Pre-set the maximum number of nodes in the doubly linked list (e.g., set it to 512 nodes based on the host machine's memory capacity) to avoid excessive memory usage or memory leaks due to unlimited node increases; If the current number of nodes in the linked list reaches the upper limit, trigger the subsequent node elimination logic.

[0028] Step S1.6: Elimination of the least visited node; When the number of nodes in the linked list exceeds the set limit, the node located at the tail of the linked list (i.e., the least visited) is deleted from the linked list; Before deletion, the memory occupied by the node must be released, and the key-value pair at the corresponding address in the hash table must be deleted simultaneously to ensure that cache resources can be reused.

[0029] Image read / write optimization steps: This step embeds the LRU algorithm into the virtual NVMe read / write process, prioritizing high-frequency data processing through caching to reduce direct I / O operations on the SSD image file, as detailed below: Step S2.1: LRU Algorithm Calling Logic: When the virtual NVMe initiates an SSD read / write request, it first calls the LRU algorithm implemented in the LRU algorithm construction step to perform cache matching on the target SSD address: Step S2.1.1: If the node corresponding to the address exists in the hash table, first determine whether the size of the data read / written this time is consistent with the size of the data stored in the node; Step S2.1.2: If it is a read operation and the required data size is less than or equal to the node's storage data size, directly extract the corresponding length of data from the node's memory area and return it without accessing the SSD image file; Step S2.1.3: If it is a write operation and the required data size is less than or equal to the node's storage data size, directly copy the data to be written to the node's memory area. After the write is completed, mark the node data as "modified". Step S2.1.4: If the size of the data to be read or written is greater than the size of the data stored on the node (e.g., if the request is to read or write 32KB of data, but the node only stores 16KB of data), then skip the cache and directly call the host machine's file operation interface to read and write the SSD image file, thus avoiding performance loss caused by memory reallocation.

[0030] Step S2.2: Handling cache misses; If the target SSD address does not exist in the hash table, the SSD image file is directly operated through the host machine's file I / O interface (e.g., calculate the file offset by address and perform read / write operations). After the read / write is completed, it is determined whether to create a new node and add it to the cache based on the access frequency of the address (e.g., access ≥3 times within 5 minutes) to avoid invalid cache occupation.

[0031] Performance optimization steps; This step further improves the optimization effect through thread scheduling and data consistency protection measures, ensuring that virtual NVMe read / write performance and data integrity are both maintained, as detailed below: Step S3.1: Optimization goals and core principles; while improving read and write performance, ensure the consistency between SSD image data and cached data to avoid data loss or tampering due to cache operations.

[0032] Step S3.2: Creation of background maintenance thread; During LRU algorithm initialization, an independent background thread is created. This thread is specifically responsible for adjusting the order of the doubly linked list (such as periodically sorting the node order to ensure that the "most recently accessed" node is always at the head), and the operation of the thread does not affect the main read and write process of the virtual NVMe, thus avoiding interference with core operations.

[0033] Step S3.3: Asynchronous flushing of dirty data to disk; Before executing node eviction (i.e. step S1.6), the background thread first checks whether the data of the node to be evicted is "modified" (i.e. the node marked in step S2.1.3); if it is "modified", the node data is first written to the address corresponding to the SSD image file, and after the flushing is completed, the node and hash table mapping are deleted to ensure that the modified data is not lost.

[0034] Step S3.4: Dynamic refresh of hash map; When the read / write data size in step S2.1.4 exceeds the node storage size, a hash map refresh operation is triggered: Step S3.4.1: Keep the key values ​​of the hash table the original SSD address values ​​to avoid address mapping confusion; Step S3.4.2: If it is a read operation, reallocate memory, store the complete data and data size read from the SSD image file into the new node, and update the hash table mapping; Step S3.4.3: If it is a write operation, reallocate memory, store the complete data to be written and its size in the new node, and update the hash table mapping; Step S3.4.4: To reduce the impact on the main read / write process, this refresh operation can be executed in a separate thread to ensure the response speed of the main process.

[0035] Step S3.5: Constraint control of data consistency; set up thread synchronization mechanisms (such as mutex locks) to prevent background threads and main read / write threads from operating on cache nodes simultaneously, which could lead to data contention; at the same time, logs of key read / write operations (such as address, data size, and operation time) are recorded. If the system crashes abnormally, the "modified" data that has not been flushed to disk can be recovered through the logs to ensure data integrity.

[0036] The present invention also discloses a virtual NVMe system, which implements the above-described method for optimizing virtual NVMe read and write performance using the LRU algorithm to achieve virtual NVMe read and write performance optimization.

[0037] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0038] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for optimizing the read / write performance of virtual NVMe using the LRU algorithm, characterized in that, include: The LRU algorithm construction steps are as follows: Build a cache management architecture that uses hash tables and doubly linked lists. Use hash tables to quickly locate the cache nodes corresponding to internal addresses of the SSD, and use doubly linked lists to manage the access order of SSD addresses. Image read / write optimization steps: If the SSD address to be read / written exists in the hash table, select to perform the read / write operation from the cache node or the SSD image file based on the size of the corresponding data in the linked list and the size of the data to be read / written this time; if the address does not exist in the hash table, perform the read / write operation directly on the SSD image file. Performance optimization steps: When the LRU algorithm is initialized, a linked list order adjustment thread is created. The node data that has not been accessed for the longest time and exceeds the linked list length is flushed to the SSD image file and then deleted. When the read / write data is greater than the linked list node data size, the hash mapping is refreshed.

2. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 1, characterized in that, The data structures for constructing hash tables and doubly linked lists in the LRU algorithm construction step include: The key of the hash table is set to the internal address of the SSD to be accessed, and the value is set to the memory pointer of the corresponding node in the doubly linked list. Each node of the doubly linked list stores the internal address of the SSD, the length of the data corresponding to the address, the memory storage area of ​​the data, and pointers to the predecessor and successor nodes of the node.

3. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 2, characterized in that, The LRU algorithm construction step, which manages the access order of SSD addresses using a doubly linked list, includes: When the virtual NVMe accesses an SSD address, it stores the address value, data length, and corresponding data into a linked list node, allocates independent memory space for the node, and records the predecessor and successor pointers of the node; if the address is accessed again, the node's position in the linked list is adjusted through the pointers.

4. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 2, characterized in that, The LRU algorithm construction steps also include: When an SSD address hits a cache node through the hash table, the node is moved from its current position to the head of the doubly linked list. The position adjustment is completed by modifying the predecessor and successor pointer relationships of the node.

5. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 2, characterized in that, The LRU algorithm construction steps also include: Pre-set the maximum number of nodes in the doubly linked list to avoid excessive memory usage or memory leaks; when the number of nodes in the linked list reaches the limit, delete the least visited node at the tail of the linked list, release the memory occupied by that node, and delete the key-value pair corresponding to the SSD address in the hash table.

6. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 1, characterized in that, The mirror read / write optimization steps include: If a node with the target SSD address exists in the hash table, determine the relationship between the read / write data size and the node's stored data size: If it is a read operation and the required data size is less than or equal to the node's stored data size, directly extract the corresponding length of data from the node's memory area and return it. If it is a write operation and the required data size is less than or equal to the node's storage data size, copy the data to be written to the node's memory area and mark the node data as "modified". If the size of the read / write data exceeds the size of the node's storage data, skip the cache and perform read / write operations on the SSD image file through the host machine's file I / O interface. If the target SSD address does not exist in the hash table, the SSD image file is operated through the host machine's file I / O interface. After the read and write operations are completed, it is determined whether to create a new node and add it to the cache based on the access frequency of the address. Only nodes with high-frequency access addresses are added to the cache.

7. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 1, characterized in that, The performance optimization steps include: creating an independent background thread during LRU algorithm initialization, which performs order adjustment of the doubly linked list to ensure that the "most recently accessed" node is at the head of the list, and the thread's operation does not affect the main read and write process of the virtual NVMe.

8. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 1, characterized in that, The performance optimization steps also include: When the read / write data size is greater than the node storage data size during the image read / write optimization step, a hash mapping refresh is triggered. The hash table key value is kept at the original SSD address value. If it is a read operation, memory is re-allocated to store the complete data read from the file. If it is a write operation, memory is re-allocated to store the complete data to be written, and the node mapping between the hash table and the doubly linked list is updated.

9. The method for optimizing virtual NVMe read / write performance using the LRU algorithm according to claim 1, characterized in that, The performance optimization steps also include: A thread synchronization mechanism is set up to avoid data contention caused by background threads and the main read / write thread operating on cache nodes concurrently; at the same time, key read / write operation logs are recorded, which include SSD address values, data lengths and operation times, and are used to recover "modified" data that has not been flushed to disk after a system crash.

10. A virtual NVMe system, characterized in that, The system employs the method described in any one of claims 1-9 for optimizing virtual NVMe read / write performance using the LRU algorithm.

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