Method for forming holes in substrate and application of method

Abstract

The invention discloses a method for forming holes in a substrate and application of the method, and belongs to the field of quantum chip manufacturing. The method for forming the holes in the substrate comprises the steps that xenon difluoride and oxygen plasmas are used as working media, and etching is conducted from a target area of the surface of the substrate to the interior under the action of a directional electric field so that part of materials of the substrate can be removed; and carrying out sound wave cleaning on the substrate in the cleaning solution. By implementing the above process, a high quality hole can be formed in a substrate in order to improve the quality of a component fabricated in the hole.

Description

Technical Field

[0001] This application belongs to the field of quantum computing, especially the field of quantum chip manufacturing. In particular, this application relates to a method for creating holes in a substrate and its application. Background Technology

[0002] Through-Silicon Vias (TSVs) are a key technology in 3D integrated systems. Currently, common TSVs typically contain an insulating layer, a barrier layer, and a metal core. Because the materials within each layer of a TSV have different properties, and the quality of the interlayer interfaces has a crucial impact on the performance of the TSV and the reliability of the 3D integrated system, the fabrication of high-quality TSVs is highly desirable. Summary of the Invention

[0003] This application provides an example of a method for creating vias in a substrate and its application. This method can be implemented to create smooth-surfaced vias, which can then be used to fabricate high-quality TSV structures within the vias, thereby improving the signal transmission quality of the 3D packaged chip fabricated based on this method through the TSV structure.

[0004] The solution presented in this application example is implemented through the following steps.

[0005] In a first aspect, the method for creating a hole in a substrate, as exemplified by this application, includes:

[0006] Using xenon difluoride and oxygen plasma as the working fluid, etching is performed from a target area on the substrate surface inwards under the influence of a directional electric field to remove a portion of the substrate material; and

[0007] The substrate is cleaned using acoustic wave cleaning in a cleaning solution.

[0008] According to some examples of this application, the hole is a through hole along the thickness direction of the substrate, and optionally, the aspect ratio of the through hole is greater than 1;

[0009] Alternatively, the hole can be a blind hole along the thickness direction of the substrate, and optionally, the aspect ratio of the blind hole is less than 1.

[0010] According to some examples in this application, the hole is a straight hole or a tapered hole;

[0011] And / or, the etching is anisotropic etching;

[0012] And / or, acoustic cleaning is mega-acoustic cleaning.

[0013] According to some examples of this application, a barrier layer is formed on the substrate surface, and the barrier layer exposes the target area.

[0014] According to some examples of this application, along the thickness direction of the substrate, the barrier layer has an opening in which the projected pattern coincides with the target area, and the barrier layer exposes the target area through the opening.

[0015] According to some examples of this application, the barrier layer is a hard mask layer; alternatively, the barrier layer is silicon dioxide and the substrate is silicon.

[0016] According to some examples of this application, the barrier layer is prepared by selectively oxidizing the substrate, with the selected area avoiding the target area; or, the barrier layer is prepared by plasma-enhanced chemical vapor deposition and etched to expose the target area.

[0017] Optionally, the substrate surface is thinned and planarized before the barrier layer is fabricated.

[0018] According to some examples of this application, during the step of etching from a target area on the substrate surface into the interior, the etching rate is selected as a preset value, and the preset value depends on the quality of the hole being manufactured.

[0019] According to some examples of this application, the method for creating vias in a substrate further includes a substrate thinning operation performed after acoustic cleaning of the substrate in a cleaning solution. Optionally, in the step of etching from a target area on the substrate surface inward, the surface is the front side of the substrate, and the thinning operation is performed from the back side of the chip.

[0020] In a second aspect, the present application presents an example of a method for creating holes in a substrate for use in superconducting quantum chips manufactured by stereolithography.

[0021] In a third aspect, the method for optimizing the manufacturing process of superconducting quantum chips exemplified in this application includes:

[0022] At least a base chip, an insertion layer chip, and an upper layer chip are arranged in a layered manner, and interlayer interconnection is performed by flip-chip bonding to form a flip chip; wherein the manufacturing step of the insertion layer chip includes implementing the method of creating vias in the substrate according to any one of claims 1 to 8 to form vias in the substrate of the insertion layer chip and to form interconnect structures in the vias;

[0023] Flip-chip testing was conducted to evaluate the performance of the interconnect architecture; and

[0024] Based on the evaluation results, the manufacturing steps of the intercalation layer chip were optimized to adjust the etching rate from the target area on the substrate surface to the interior during the implementation of the method for creating vias on the substrate.

[0025] According to some examples of this application, the intercalation layer chip has a target thickness, the substrate used to manufacture the intercalation layer chip has an initial thickness that is greater than the target thickness, and the thickness of the substrate is transformed from the initial thickness to the target thickness through a thinning operation.

[0026] In the above implementation process, the optimization of the process achieves the effect of manufacturing high-quality holes in the substrate; the high quality includes flatter and smoother inner walls of the holes, fewer burrs, and lower local mechanical stress.

[0027] Correspondingly, based on such high-quality holes, the structures manufactured inside the holes, such as conductor pillars, are also of higher quality; for example, the conductor pillars are firmly and stably bonded to the hole walls, resulting in more uniform and denser morphology and composition throughout the pillars.

[0028] Therefore, when the conductor pillars inside the hole are implemented as TSV interconnect structures, the upper and lower surfaces (and the components disposed thereon) in the thickness direction of the substrate can be electrically connected with good connectivity, which also helps to improve the quality of signal transmission. Attached Figure Description

[0029] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.

[0030] Figure 1 This is a schematic diagram of the process for fabricating a barrier layer on the substrate surface, as shown in the example of this disclosure.

[0031] Figure 2 This is a schematic diagram of the process for creating a hole in a liner with a barrier layer on the surface, as shown in the example of this disclosure.

[0032] Figure 3 This is a structural comparison diagram of the surface morphology of a hole in a substrate before and after cleaning, as shown in the example of this disclosure.

[0033] Figure 4 This is a schematic diagram of the process flow for creating a hole in the substrate, as shown in the example of this disclosure.

[0034] Figure 5 This is a schematic diagram illustrating the optimized manufacturing process of a superconducting quantum chip in the examples of this disclosure. Detailed Implementation

[0035] To improve the performance of superconducting quantum computers, the number of superconducting qubits integrated into superconducting quantum chips is constantly increasing. Correspondingly, the size of superconducting quantum chips is also trending towards increasing. Therefore, in order to minimize the manufacturing difficulty of the chip—such as the configuration of each qubit and its corresponding peripheral structure and circuitry—while continuously increasing the number of superconducting qubits, the industry has chosen to change the planar packaging structure of superconducting quantum chips to a three-dimensional packaging structure.

[0036] In practice, the realization of 3D packaging often relies on technologies such as through-silicon vias (TSVs) and flip-chip bonding. Among these, TSVs are one of the key technologies for 3D integrated systems. Currently, common TSVs typically contain an insulating layer, a barrier layer, and a metal core. Due to the different properties of the materials in each layer, the quality of the interlayer interfaces has a crucial impact on the performance of the TSVs and the reliability of the 3D integrated system.

[0037] The example solution in this application mainly relates to the research and development of TSVs. In practice, the inventors have found that during the TSV manufacturing process, after etching to form the original through-silicon vias, the smoothness of the inner wall of the via has a direct and significant impact on the microstructure of the subsequent filling materials within the via and the interlayer interfaces. Therefore, it is desirable to propose an excellent TSV manufacturing technology. In view of this, the example in this application improves the via fabrication method in TSV manufacturing, ensuring a high-quality TSV formed by the subsequent filling material within the via by forming high-quality vias.

[0038] Research has found that:

[0039] BOSCH etching technology is currently the mainstream method for etching through-silicon vias (TSVs). This method uses SF6 as the etchant to etch silicon. After etching for a certain period, C4F8 is used to passivate the sidewalls of the etched hole. By alternating between etching and passivation multiple times, TSVs with steep sidewalls and minimal lateral etching can be achieved.

[0040] However, due to the alternation of etching and passivation, scalloped patterns inevitably form on the inner wall of the through silicon via (TSV). The roughness of the sidewall will have a high-frequency impact on the signal. At the same time, the greater the undulation of the inner wall of the TSV, the higher the average thermomechanical stress will be, and there will be peak stress, the value of which is higher than the average thermal stress level, which will lead to a significant reduction in the reliability of the TSV. Therefore, exploring new deep silicon etching technology is extremely important to achieve a smooth inner wall.

[0041] For the fabrication of high-quality vias, some attempts have opted for alternative non-Bosch etching methods. For example, the rough structure of the TSV sidewalls can be improved or completely removed by depositing oxides on the sidewalls of the via. However, implementing such methods may introduce problems such as lattice mismatch and thermal expansion coefficient mismatch between the oxide and the silicon substrate.

[0042] Other attempts focused on optimizing and improving parameters of the BOSCH etching process. For example, after etching micro-holes in a thicker masking layer on the substrate, the bite effect at the hole opening was eliminated by lowering the substrate temperature, and the etching and passivation times for each cycle were shortened, but the roughness problem could not be completely improved.

[0043] Furthermore, some approaches involve post-processing after hole fabrication to reduce the roughness of the TSV inner wall. For example, after Bosch etching, argon ion cleaning is used to remove etching products. However, the primary purpose of argon ion cleaning is to remove etching products, and it has little effect on reducing the roughness of the hole inner wall.

[0044] In view of the above, this application discloses a method for creating holes in a substrate. This method enables the fabrication of holes with smoother inner walls, fewer burrs, and lower roughness in the substrate, providing favorable conditions for the subsequent fabrication of high-quality TSVs.

[0045] See the example. Figure 4 The method for creating a hole in a substrate includes: using xenon difluoride (XeF2) and oxygen plasma as working fluids, etching from a target area on the substrate surface into the interior under the action of a directional electric field to remove part of the substrate material; and performing acoustic cleaning (such as ultrasonic cleaning, mega-sonic cleaning, etc.) on the substrate in a cleaning solution.

[0046] In particular, it has been found that appropriate movement of the substrate during acoustic cleaning, especially mega-acoustic cleaning, can improve the quality of the manufactured via inner walls (i.e., fewer surface bumps and burrs; or flatter inner walls); this movement can be achieved, for example, by flipping the substrate in a cleaning solution (such as BOE mentioned later). Alternatively, the ultrasonic waves can be directed into the via. In other examples, the cleaning solution can be directed through the vias of the substrate to achieve further improved via quality when using acoustic cleaning.

[0047] For example, as a specific alternative, an inductively coupled plasma (ICP) device is used to etch silicon vias using XeF2 gas while simultaneously oxidizing the vias with oxygen plasma. The vias are then cleaned using BOE, thereby improving the roughness of the TSV inner walls.

[0048] In the above process, the etching and oxidation processes can be fully disclosed through the following description.

[0049] (1) XeF2 etching of silicon

[0050] The reaction of gaseous XeF2 with silicon wafers can be divided into the following steps:

[0051] Step 1: Non-free XeF2 is adsorbed on the silicon surface;

[0052] Step 2: The adsorbed XeF2 decomposes and produces gaseous F2 adsorbed on the silicon surface;

[0053] Step 3: The adsorbed gas F2 reacts with the silicon surface to produce SiF4, which is then adsorbed onto the surface;

[0054] Step 4: The reaction product molecules SiF4 desorb and form gaseous products; the residual gas that does not undergo reaction, namely Xe produced by decomposition, volatilizes from the etched silicon surface. These gases can be pumped out into the reaction chamber.

[0055] Unlike the XeF2 etching method used in the example of this application, the probability of spontaneously occurring step 2 under the same conditions is very small when using etching gases such as CHF3, CF4, and CC14. Therefore, if CHF3, CF4, and CC14 are used as etching gases, plasma technology is required to generate the reactive group F.

[0056] In this application example, XeF2 is used, which allows for high-rate silicon etching without plasma discharge. This etching reaction can be summarized by the following reaction equation: 2XeF2 + Si → 2Xe(q)↑ + SiF4(q)↑

[0057] (2) Oxygen plasma oxidation

[0058] When single-crystal silicon is exposed to air at room temperature, a silicon dioxide layer (which can be described as a "native oxide layer") several atoms thick will form within seconds. At room temperature, the native oxide layer prevents oxygen atoms in the air from reacting further with the silicon. However, in the ICP process, when oxygen plasma is directed by an electric field, it reacts with the etched silicon in the pores to generate silicon dioxide.

[0059] Therefore, by means of the above method, silicon can be etched to form holes, and the inner walls of the holes can be oxidized to form silicon dioxide.

[0060] After the above steps, you can choose to use acoustic cleaning, such as high-frequency megasonic waves, combined with BOE cleaning to remove the silica layer, thereby significantly reducing the burrs and undulating protrusions on the inner wall of the TSV, resulting in a smoother and flatter surface.

[0061] Alternatively, these operations can be performed before the barrier layer mentioned later is manufactured—that is, by thinning and planarizing the substrate surface.

[0062] Advantageously, the method for creating vias on a substrate can also include a substrate thinning operation performed after acoustic cleaning of the substrate in a cleaning solution. Furthermore, in the step of etching inward from a target area on the substrate surface (the front side of the substrate), the thinning operation is performed from the back side of the chip. This is because substrates with large aspect ratios may have relatively poor morphology quality on the inner wall at the bottom of the via, and thinning can remove this portion of the via.

[0063] The following section provides a more detailed explanation of each step in the hole-forming process.

[0064] The holes can be constructed in different forms in different examples.

[0065] For example, a hole can be a through-hole along the thickness direction of the substrate. Alternatively, the hole can also be a blind hole along the thickness direction of the substrate.

[0066] For through holes, the aspect ratio can be greater than 1; while for blind holes, the aspect ratio is less than 1, and vice versa; and they can be selected as needed without any particular limitation.

[0067] Specifically, the example scheme of this application is applicable to deep silicon etching, for example, the aspect ratio can reach 40:1. To obtain holes with a large aspect ratio, the etching method can be implemented as anisotropic etching; that is, more etching is done in the depth direction and less etching is done in the direction perpendicular to the depth direction (such as the width direction). A large aspect ratio helps to solve the problems of heat dissipation and warpage of the substrate.

[0068] Furthermore, the hole can be a straight hole or a tapered hole. A straight hole is one in which the diameter is the same along the depth of the hole or the thickness of the substrate. A tapered hole, on the other hand, indicates that the diameter of the hole varies along the depth of the hole or the thickness of the substrate, for example, it is gradually tapered.

[0069] The substrate can be made of various suitable materials; for example, in superconducting quantum chips, the substrate can be silicon or sapphire. In other applications, such as semiconductor chips, gallium nitride, silicon carbide, gallium arsenide, etc., can be used. Furthermore, before processing the substrate, it can undergo cleaning, surface polishing, or thinning processes such as planarization.

[0070] To obtain holes of a specified size and shape, photoresist can be spin-coated onto the substrate surface and then patterned to expose the area of ​​the substrate to be etched (i.e., the target area). Therefore, the substrate surface can have a patterned mask. Advantageously, in some other examples, a barrier layer can be formed on the substrate surface, and this barrier layer exposes the target area. That is, a hard mask can be fabricated on the substrate surface. The hard mask can be made of materials such as TiN, SiN, or SiO2.

[0071] The substrate can be made of a completely different material from the barrier layer, meaning they do not contain the same elements. For example, the substrate could be silicon, and the hard mask could be titanium nitride. Alternatively, the substrate could share some of the same elements as the barrier layer. For example, in some specific examples, the barrier layer could be made of silicon dioxide, and the substrate could be made of silicon.

[0072] If the substrate has some of the same elements as the barrier layer, the barrier layer can be formed by reacting the substrate using an appropriate method.

[0073] For example, in the case of oxides where the host element of the barrier layer is the substrate, the barrier layer can be prepared by selectively oxidizing the substrate, with the selected area avoiding the target area. In such examples, the thickness of the substrate may be reduced because the barrier layer is subsequently removed. The manufacturing process may involve oxidizing the substrate surface and then patterning it to form the aforementioned opening.

[0074] In addition to fabricating the barrier layer by oxidizing and patterning the substrate surface, the above-described methods can also be used to directly provide the relevant components of the barrier layer's elemental composition through a reaction. For example, the barrier layer can be prepared by plasma-enhanced chemical vapor deposition and then etched to expose the target area; this can be illustrated in specific optional examples.

[0075] Depending on the implementation in different examples, the mask can have different pattern structures. In some examples, the barrier layer has openings along the thickness direction of the substrate where the projected pattern coincides with the target region, and the barrier layer exposes the target region through these openings.

[0076] For example, if the size of the hole fabricated in the substrate is 1 micrometer, then the opening of the hard mask can also be a 1-micrometer hole with the same cross-sectional shape as that hole. Therefore, it can be understood that the area of ​​the target region exposed by the opening can be equal to the cross-sectional area of ​​the hole fabricated in the substrate.

[0077] Alternatively, in other examples, the opening in the hard mask could be designed to be larger in size (e.g., in diameter) than the hole that is desired to be fabricated in the substrate. Therefore, it can be understood that the area of ​​the target region exposed by the opening can be larger than the cross-sectional area of ​​the hole fabricated in the substrate.

[0078] The above discussion mainly focuses on structure and materials. From a process perspective, the etching process may also require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials chosen, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, and other deposition processes.

[0079] Examples of deposition processes include ion beam assisted deposition (IBAD), vacuum evaporation, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), chemical vapor deposition (CVD), sol-gel deposition, and magnetron sputtering.

[0080] In addition, it may be necessary to remove one or more materials during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or lift-off processes. The materials forming the circuit elements herein can be patterned using known lithographic techniques, such as photolithography or electron beam lithography.

[0081] To avoid going into too much detail, etching in the form of creating holes can be simply expressed as using dry etching methods such as electron beam etching or photolithography, and the relevant information can be obtained from existing processes.

[0082] Specifically, during the etching process, the etching rate (e.g., for ICP etching, the etching rate can be adjusted by controlling equipment parameters such as the power of the etching equipment) during the etching step from the target area on the substrate surface inward can be selected as a preset value, and this preset value depends on the quality of the manufactured via. The applicant unexpectedly discovered that by purposefully selecting the etching rate, the quality of the inner wall of the formed via can be effectively screened. For example, by reducing the etching rate, the smoothness of the via manufactured in the substrate can be increased. This may be related to the fact that a lower etching rate reduces the height of burrs or protrusions on the via wall caused during the etching process.

[0083] In general, the scheme of this disclosure example can be briefly described as follows.

[0084] The specific approach to improving the inner wall morphology of TSVs is as follows: Through-holes are formed by etching silicon with XeF2 gas, and simultaneously oxidized by oxygen plasma. This is followed by BOE cleaning of the through-holes.

[0085] (1) A SiO2 mask was prepared on a Si(111) substrate by plasma-enhanced chemical vapor deposition (PECVD);

[0086] (2) Silicon vias are etched using XeF2 gas in inductively coupled plasma (ICP), while oxygen plasma oxidizes the vias.

[0087] (3) Use acoustic wave-assisted BOE to clean SiO2 in the through hole to reduce irregular surface protrusions such as burrs.

[0088] To make it easier for those skilled in the art to implement the schemes of this application, and more specifically, optional example processes may be disclosed through the following examples.

[0089] 1. Preparation of SiO2 mask layer

[0090] like Figure 1As shown, a SiO2 mask layer is prepared on a Si substrate using PECVD. The specific steps are: cleaning the Si substrate and preparing SiO2 using PECVD.

[0091] (1) Cleaning of Si(111) substrate

[0092] The Si(111) substrate is ultrasonicated with NMP (N-methylpyrrolidone) for 10 min, IPA (isopropanol) for 10 min, and DI (deionized water) for 10 min. Then it is treated with a piranha water bath at 120°C for 10 min. After that, it is ultrasonicated with DI for 15 min, cleaned with BOE (buffered oxidized etchant) for 1 min, and cleaned with DI for 5 min to complete the substrate cleaning.

[0093] (2) Preparation of SiO2 by PECVD

[0094] Temperature 300℃, N2O, N2: 710 sccm, 5% SiH4 / N2: 150 sccm, Forward power: 20 W, Vacuum: 850 mTorr, Thickness 2 μm.

[0095] 2. ICP etching of through-silicon vias

[0096] See Figure 2 The specific steps are: exposing the through-silicon via (TSV), etching SiO2 before ICP etching, and then etching and oxidizing the TSV. It should be noted that... Figure 2 The number and location distribution of vias in the silicon wafer disclosed herein are for illustrative purposes only; in actual implementation, the configuration can be selected and configured as needed without any particular limitation.

[0097] (1) Exposure of through silicon vias

[0098] Photoresist coating: Use double-layer S1813 photoresist, maintain a high speed of 3000 (r / min) and perform a photoresist coating for 40 seconds to ensure that the photoresist is evenly coated on the silicon wafer.

[0099] Pre-baking: Bake on a heating plate at 115°C for 2 minutes;

[0100] Exposure: The location of the through silicon via is exposed using a stepper lithography machine, and the pattern is developed.

[0101] (2) Etching SiO2 before ICP (RIE / Reactive-Ion Etching can also be used for etching)

[0102] Parameters: ICP RF: 200W, CHF3: 25sccm, Ar: 25sccm 140min, Pressure: 30mtorr.

[0103] (3) ICP etching of silicon vias and oxidation

[0104] ICP RF power: 1500W, Pressure: 50mTorr, XeF2: 200sccm, O2: 100sccm, Cycle count: 540.

[0105] 3. BOE cleaning through-hole

[0106] See Figure 3 Megasonic cleaning was performed using BOE solution.

[0107] The etched silicon wafer is placed in a 40% (v / v) BOE solution (an aqueous solution of hydrofluoric acid and deionized water in a 1:10 volume ratio) and cleaned using high-frequency megasonic waves. This method removes the silica within the vias, ensuring complete removal of silica from the bottom of the through-silicon vias.

[0108] The above discussion has clearly described the method of creating a hole in the substrate in this disclosure. In view of the aforementioned three-dimensional packaging of superconducting quantum chips and its higher requirements for TSV process, this method of creating a hole can be applied to the manufacture of superconducting quantum chips to manufacture a flip chip or a three-dimensional packaged chip.

[0109] Furthermore, it is known that this process can be primarily used to optimize the manufacturing process of superconducting quantum chips; see [reference needed]. Figure 5 The optimized process steps mainly involve the TSV manufacturing process in 3D packaged chips.

[0110] For example, a three-dimensionally packaged superconducting quantum chip includes a base chip, an insertion layer chip, and an upper chip.

[0111] The base chip, intercalation layer chip, and upper layer chip are arranged in a layered manner and interconnected by flip-chip bonding to form a flip chip.

[0112] In this superconducting quantum chip, the superconducting qubit structure can be configured into the upper-layer chip. The readout, control circuitry, and other components of the superconducting quantum can be configured into the base layer chip and the insertion layer chip as needed. Specifically, the manufacturing steps of the insertion layer chip include performing a method of creating vias in the substrate to form through-holes and interconnect structures within the vias. Taking an aluminum junction superconducting qubit as an example, the interconnect structure can be indium pillars.

[0113] Next, the flip-chip is tested to evaluate the performance of the interconnect structure. For example, the control effect can be determined by testing cases where control lines are configured to the base chip and the upper chip respectively via indium pillars. Then, based on the evaluation results, the manufacturing steps of the insertion layer chip are optimized to adjust the etching rate from the target area on the substrate surface to the interior during the implementation of the method for creating vias on the substrate.

[0114] In other words, by establishing a correlation between test results (such as control performance) and etching rate through testing, the etching rate can be adjusted according to the quality of the test structure to obtain an ideal etching rate that yields good TSV performance. Subsequently, under the same TSV design (material, structure, etc.), the aforementioned through-hole manufacturing process is selected for hole fabrication, and then the interconnect structure is manufactured by means such as electroplating or filling the holes with metal particles and then melting and solidifying them. Therefore, the TSV structure or interconnect structure in the hole can be a solid columnar structure or a hollow column—such as a thin layer of superconducting materials such as TiN deposited on the inner surface of the through hole using ALD or CVD methods.

[0115] Furthermore, as mentioned above, in the process of creating vias, the substrate can be thinned after mega-sonic cleaning combined with BOE cleaning. Therefore, during the fabrication of the insertion layer chip, the insertion layer chip can be set to have a target thickness, while the substrate used to fabricate the insertion layer chip has an initial thickness, which is greater than the target thickness. Thus, during the via fabrication process, the substrate thickness can be transformed from the initial thickness to the target thickness due to the thinning operation. In other words, the specific selection of the substrate thickness used for via fabrication (such as the aforementioned relative size of the initial and target thicknesses) allows the thinning operation after acoustic cleaning to not only improve the quality of the vias but also ensure that the subsequent chip fabrication meets the preset requirements.

[0116] The embodiments described above with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0117] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments have been described above with reference to the accompanying drawings. Throughout the description, similar reference numerals are used to denote similar components. In the foregoing description, numerous specific details have been set forth for illustrative purposes in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the embodiments may be combined with and referenced to each other without contradiction.

[0118] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0119] The above description of the structure, features and effects of this application is based on the embodiments shown in the drawings. The above are only preferred embodiments of this application. However, this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method of hole making in a substrate, characterized by, The method comprises: etching from a target region on a surface of a substrate to an interior of the substrate under the action of a directional electric field using xenon difluoride and oxygen plasma as working substance to remove part of material of the substrate; and performing acoustic cleaning on the substrate in a cleaning solution.

2. The method of making a hole in a substrate of claim 1 wherein, The hole is a through hole along the thickness direction of the substrate, and the aspect ratio of the through hole is greater than 1; Or, the hole is a blind hole along the thickness direction of the substrate, and the aspect ratio of the blind hole is less than 1.

3. The method of making a hole in a substrate according to claim 1 or 2, wherein, The hole is a straight hole or a tapered hole; And / or, the etching is anisotropic etching; And / or, the acoustic cleaning is megasonic cleaning.

4. The method of forming a hole in a substrate of claim 1 wherein, The surface of the substrate is formed with a barrier layer, and the barrier layer exposes the target region.

5. The method of making an aperture in a substrate of claim 4, wherein, Along the thickness direction of the substrate, the barrier layer has an opening with a projection pattern coinciding with the target region, and the barrier layer exposes the target region through the opening.

6. A method of hole making in a substrate according to claim 4 or 5, characterised in that, The barrier layer is a hard mask layer; Optionally, the barrier layer is silicon dioxide, and the substrate is silicon.

7. The method of making an aperture in a substrate of claim 5, wherein, The barrier layer is prepared by selectively oxidizing the substrate, and the selected region avoids the target region; or the barrier layer is prepared by plasma enhanced chemical vapor deposition, and is etched to expose the target region; Optionally, before the barrier layer is manufactured, the surface of the substrate is subjected to thinning and planarization treatment.

8. The method of making a hole in a substrate of claim 1 wherein, The etching speed during the implementation of the step of etching from the target region on the surface of the substrate to the interior of the substrate is selected as a preset value, and the preset value is determined depending on the quality of the hole to be manufactured.

9. The method of making a hole in a substrate according to claim 1 or 8, wherein, The method of manufacturing a hole in a substrate further comprises a thinning operation performed on the substrate after the acoustic cleaning of the substrate in the cleaning solution; Optionally, in the step of etching from the target region on the surface of the substrate to the interior of the substrate, the surface is the front surface of the substrate, and the thinning operation is performed from the back surface of the chip.

10. The use of the method of manufacturing a hole in a substrate according to any one of claims 1 to 9 in a superconducting quantum chip manufactured by three-dimensional packaging.

11. A method of optimizing a manufacturing process of a superconducting quantum chip, characterized in that, The method comprises: arranging at least a base layer chip, an insertion layer chip and an upper layer chip in a layered manner, and performing interlayer interconnection by flip-chip to form a flip-chip; wherein the manufacturing step of the insertion layer chip comprises implementing the method of manufacturing a hole in a substrate according to any one of claims 1 to 8 to form a through hole in the substrate of the insertion layer chip and form an interconnection structure in the through hole; testing the flip-chip to evaluate the performance of the interconnection structure; and optimizing the manufacturing step of the insertion layer chip according to the evaluation result to adjust the etching speed of the step of etching from a target region on a surface of a substrate to an interior of the substrate during the implementation of the method of manufacturing a hole in a substrate.

12. The method of optimizing a manufacturing process of a superconducting quantum chip of claim 11, wherein, The insertion layer chip has a target thickness, the substrate used to manufacture the insertion layer chip has an initial thickness, the initial thickness is greater than the target thickness, and the thickness of the substrate is changed from the initial thickness to the target thickness through a thinning operation. The method comprises: arranging at least a base layer chip, an insertion layer chip and an upper layer chip in a layered manner, and performing interlayer interconnection by flip-chip to form a flip-chip; wherein the manufacturing step of the insertion layer chip comprises implementing the method of manufacturing a hole in a substrate according to any one of claims 1 to 8 to form a through hole in the substrate of the insertion layer chip and form an interconnection structure in the through hole; testing the flip-chip to evaluate the performance of the interconnection structure; and optimizing the manufacturing step of the insertion layer chip according to the evaluation result to adjust the etching speed of the step of etching from a target region on a surface of a substrate to an interior of the substrate during the implementation of the method of manufacturing a hole in a substrate. The insertion layer chip has a target thickness, the substrate used to manufacture the insertion layer chip has an initial thickness, the initial thickness is greater than the target thickness, and the thickness of the substrate is changed from the initial thickness to the target thickness through a thinning operation.

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