Low-current mismatch charge pump circuit for phase-locked loop

Abstract

The invention discloses a low-current mismatch charge pump circuit for a phase-locked loop, which belongs to the technical field of charge pump phase-locked loops and comprises a PMOS (P-channel Metal Oxide Semiconductor) tube MP1, an NMOS (N-channel Metal Oxide Semiconductor) tube MN1, switches S1-S4, an operational amplifier OP1, a current detection unit and a current-to-voltage conversion and amplification unit. The switches S1 to S4 form a switch matrix, the switch S1 and the switch S2 are located on one side of the switch matrix, the switch S4 and the switch S3 are located on one side of the switch matrix, the switch S2 and the switch S4 are located above, the switch S3 and the switch S1 are located below, a source electrode of the PMOS tube MP1 is connected with a VDD power supply end, a drain electrode of the PMOS tube MP1 is connected with a node Y, and a grid electrode of the PMOS tube MP1 is connected with an output end of the current-to-voltage conversion and amplification unit. The control loop directly controls the current source, errors are prevented from being introduced by using a reference current branch, and current matching is guaranteed; and a NAND gate circuit is added, so that instability of bias voltage of the current source during inherent pulse is avoided.

Description

Technical Field

[0001] This invention relates to the field of charge pump phase-locked loop technology, and more specifically to a low-current mismatch charge pump circuit for a phase-locked loop. Background Technology

[0002] Phase-locked loops (PLLs) are an important module in mixed-signal circuits, offering advantages such as high speed, low power consumption, low jitter, low cost, and ease of integration. Widely used in system clock generation, clock recovery circuits, and wireless communication frequency synthesizers, they have become an indispensable module in integrated circuits.

[0003] A charge pump phase-locked loop (PLL) comprises several main modules, including a phase-frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV). For example... Figure 1 As shown, the comparison result of the frequency and phase detector is a digital signal, including the up signal (charging signal) and the dn signal (discharging signal). These two signals control the charge pump current to charge or discharge the LPF.

[0004] The digital signal output by the phase-frequency detector (PFD) is converted into an analog signal by a charge pump and an LPF. This analog signal controls the frequency change of the voltage-controlled oscillator (VCO). The output of the VCO is divided by a DIV and then fed back to the PFD.

[0005] The addition of a charge pump can provide infinite loop gain and capture range to a phase-locked loop (PLL). In a PLL circuit, the performance of the charge pump directly affects the quality of the VCO output frequency. The selection and application of high-performance charge pump circuits play a crucial role in improving the overall performance of the PLL. However, charge pumps are subject to non-ideal factors such as charge sharing, channel charge injection, clock feedthrough, and current mismatch, which limit the performance of charge pump phase-locked loops (CPPLLs).

[0006] A commonly used charge pump structure is as follows: Figure 2 As shown in the figure, when S1 and S2 are open, S3 and S4 are closed. The operational amplifier (OPAMP) makes the voltage at points X and Y consistent with the voltage at Vc through feedback, thus avoiding the charge sharing effect of the parasitic capacitance at points X and Y on the voltage at Vc when S1 and S2 are closed again. Although this structure improves charge sharing, it cannot avoid the current mismatch between I1 and I2.

[0007] The current mismatch is caused by two main factors. Firstly, there is a mismatch in the manufacturing process, specifically in the current mirror circuits that generate I1 and I2. Secondly, there is the channel length modulation effect, where the magnitudes of I1 and I2 vary with different Vc voltages. When current mismatch occurs, a phase difference is generated between the PLL's reference frequency and feedback frequency. This phase difference increases the reference spurs in the PLL's output spectrum, worsening the output frequency jitter performance.

[0008] like Figure 3 As shown, this structure adds a reference branch to the traditional charge pump structure. Traditional charge pumps avoid charge sharing, while the addition of the reference branch allows for better matching of charging and discharging currents. The branch containing M5 and M6 is the reference branch. Through a negative feedback structure, the voltage at point Y equals the voltage at point Z, and the voltage at point Z equals the voltage at point X, so the voltages at points Y and X are the same. During the inherent pulse, both M1 and M2 are in the conducting state, so the charging and discharging branches containing M1 and M2 operate exactly the same as the reference branch, thus ensuring that the current through M1 and M2 is the same when the inherent pulse arrives, and is equal to the current in M5 and M6. In this structure, OP2, M8, and M10 form a loop. OP2 is the first-stage amplifier, and M8 and M10 form the second-stage amplifier, where M8 acts as the amplifying transistor and M10 acts as the load transistor. Point Y is the location of the secondary pole, determined by the transconductance of M8 and the capacitance at point Y. M8 needs a large size and bias current to push up the secondary pole and ensure loop stability. Therefore, M8 requires a large size and high power consumption. The large size of M8 results in a smaller overdrive voltage, affecting the matching accuracy between M8 and M7. If the charging / discharging branch and the reference branch are not well matched, it will introduce a current mismatch between M1 and M2, i.e., a mismatch in the charging / discharging current. When both M3 and M4 are off, point Z will jump due to the switching, causing a drastic change in the output of OP2, which will affect the current of M7, ultimately leading to a mismatch in the charging / discharging current.

[0009] To avoid introducing errors using a reference current branch and ensure current matching, a low-current mismatch charge pump circuit for a phase-locked loop is proposed. Summary of the Invention

[0010] The technical problem to be solved by this invention is: how to avoid introducing errors by using a reference current branch and ensure current matching, and provides a low current mismatch charge pump circuit for a phase-locked loop.

[0011] This invention solves the aforementioned technical problems through the following technical solution: The invention includes a PMOS transistor MP1, an NMOS transistor MN1, switches S1-S4, an operational amplifier OP1, a current detection unit, and a current-to-voltage conversion and amplification unit; switches S1-S4 form a switch matrix, with switches S1 and S2 located on one side of the switch matrix, and switches S4 and S3 located on the other side, with switches S2 and S4 on top and switches S3 and S1 on the bottom. The source of the PMOS transistor MP1 is connected to the VDD power supply terminal, the drain is connected to node Y, and the gate is connected to the... The output of the current-to-voltage and amplification unit is used to provide a bias voltage Vbp for PMOS transistor MP1. Node Y is located between switch S2 and switch S4. The source of NMOS transistor MN1 is grounded, the drain is connected to node X, and the gate is connected to the bias voltage Vbn. Node X is located between switch S3 and switch S1. The inverting input of operational amplifier OP1 is connected between switch S4 and switch S3, and the non-inverting input is connected between switch S1 and switch S2. The output is connected in sequence to the current detection unit and the current-to-voltage and amplification unit.

[0012] Furthermore, the current detection unit includes a current detection resistor R1, one end of which is connected to the output terminal of the operational amplifier OP1, and the other end is connected to the input terminal of the current-to-voltage and amplification unit.

[0013] Furthermore, the current-to-voltage and amplification unit includes an operational amplifier OP2. The other end of the current sensing resistor R1 is connected to the non-inverting input of the operational amplifier OP2. At the same time, the output of the operational amplifier OP1 is directly connected to the inverting input of the operational amplifier OP2. The output of the operational amplifier OP2 is used to provide a bias voltage Vbp.

[0014] Furthermore, when the voltages of nodes Vc and Vb are kept consistent by the control of operational amplifier OP1, the mismatch current of PMOS transistor MP1 and NMOS transistor MN1 will be provided by operational amplifier OP1. The magnitude of the mismatch current is determined by detecting the voltage difference across the current sensing resistor R1. The voltage across the current sensing resistor R1 is fed into operational amplifier OP2 to adjust the current of PMOS transistor MP1 and NMOS transistor MN1. When the currents of PMOS transistor MP1 and NMOS transistor MN1 are the same, the mismatch current is eliminated. At this time, the current flowing through the current sensing resistor R1 is 0, and the voltages of nodes Va and Vb are equal. Node Vc is located between switch S1 and switch S2, and nodes Vb and Va are located across the current sensing resistor R1, respectively.

[0015] Furthermore, switch S1 is controlled to open and close via digital signal dn, switch S2 via digital signal up, switch S3 via digital signal dnb, and switch S4 via digital signal upb. When up = 1, upb = 0; when dn = 1, dnb = 0. Digital signals up and dn control switches S2 and S1 respectively to realize the charging and discharging of node Vc, and digital signals upb and dnb control switches S4 and S3 respectively to realize the charging and discharging of node Vb.

[0016] Furthermore, the charge pump circuit also includes a NAND gate and a switch S6. The switch S6 is located between the output terminal of the operational amplifier OP2 and the gate of the PMOS transistor MP1. The two ends of the NAND gate are respectively input with digital signals up and dn. When both digital signals up and dn are 1, the switch S6 is turned off.

[0017] Compared with the prior art, the present invention has the following advantages: the low current mismatch charge pump circuit for phase-locked loop directly controls the current source through the control loop, avoiding the introduction of errors by using the reference current branch and ensuring current matching; the addition of NAND gate circuit avoids the instability of the current source bias voltage during inherent pulses. Attached Figure Description

[0018] Figure 1 This is a schematic block diagram of the structure of a charge pump phase-locked loop in the prior art;

[0019] Figure 2 This is a schematic diagram of a traditional charge pump structure in the prior art;

[0020] Figure 3 This is a schematic diagram of a charge pump structure that incorporates a reference branch on top of a traditional charge pump structure.

[0021] Figure 4 This is a schematic diagram of the charge pump circuit in Embodiment 1 of the present invention;

[0022] Figure 5 This is a schematic diagram of the charge pump circuit in Embodiment 2 of the present invention;

[0023] Figure 6 This is a simulation result diagram of the charge pump circuit in Embodiment 2 of the present invention. Detailed Implementation

[0024] The embodiments of the present invention are described in detail below. These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. However, the scope of protection of the present invention is not limited to the following embodiments.

[0025] Example 1

[0026] like Figure 4As shown, this embodiment provides a technical solution: a low-current mismatch charge pump circuit for a phase-locked loop. Based on a traditional charge pump, this invention adds a current detection circuit, a current-to-voltage conversion circuit, and an amplification circuit to control the current source MP1. When OP1 keeps Vb and Vc consistent, the mismatch current between MN1 and MP1 is provided by operational amplifier OP1. The current detection circuit detects the output current of operational amplifier OP1 to determine the magnitude of the mismatch current. The current-to-voltage conversion circuit converts this mismatch current into a voltage value and amplifies it to control the current of current source MP1, reducing the mismatch current until it is undetectable by the current detection circuit.

[0027] Example 2

[0028] This embodiment further illustrates the charge pump circuit in Embodiment 1, such as... Figure 5 As shown, it includes two operational amplifiers OP1 and OP2, six switches S1-S6, and a resistor R1. The switches S1-S4 and operational amplifier OP1 function the same as a traditional charge pump, which is used to keep the voltages of Vc and Vb consistent when S1 and S2 are off and S3 and S4 are on, thereby eliminating the charge sharing effect.

[0029] In this embodiment, the charge pump circuit includes a PMOS transistor MP1, an NMOS transistor MN1, switches S1-S4, operational amplifiers OP1 and OP2, and a resistor R1. Switches S1-S4 form a switch matrix, with switches S1 and S2 on one side of the matrix and switches S4 and S3 on the other side. Switches S2 and S4 are on top, and switches S3 and S1 are on the bottom. The source of PMOS transistor MP1 is connected to the VDD power supply terminal, its drain is connected to node Y, and its gate is connected to the output terminal of operational amplifier OP2. Node Y is located between switches S2 and S4. The source of NMOS transistor MN1 is grounded, the drain is connected to node X, and the gate is connected to the bias voltage Vbn. Node X is located between switches S3 and S1. The inverting input of op-amp OP1 is connected between switches S4 and S3, and the non-inverting input is connected between switches S1 and S2. The output is connected in series with resistor R1 and connected to the non-inverting input of op-amp OP2, and directly connected to the inverting input of op-amp OP2. The output of op-amp OP2 is used to provide the bias voltage Vbp.

[0030] In this embodiment, switch S1 is controlled to be turned on and off by digital signal dn, switch S2 is controlled to be turned on and off by digital signal up, switch S3 is controlled to be turned on and off by digital signal dnb, and switch S4 is controlled to be turned on and off by digital signal upb. When up=1, upb=0, and when dn=1, dnb=0.

[0031] In this embodiment, up / dn directly controls switches S2 / S1 to achieve charging and discharging of the Vc node, and upb / dnb controls switches S4 / S3 to achieve charging and discharging of the Vb node.

[0032] In this embodiment, the function of resistor R1 is current detection. When OP1 keeps voltages Vb and Vc consistent, the mismatch current between MN1 and MP1 is provided by operational amplifier OP1. By detecting the voltage difference across R1, the magnitude of the mismatch current is determined. The voltage across resistor R1 is fed into operational amplifier OP2 to adjust the currents of MP1 and MN1. When the currents of MP1 and MN1 are the same, the current mismatch is eliminated. At this time, the current flowing through resistor R1 is 0, and voltages Va and Vb are equal.

[0033] In this embodiment, the charge pump circuit also includes a NAND gate, which controls the switching off of S6 when both up and dn are 1. That is, during the inherent pulse, both up and dn are 1, at which point S3 and S4 are simultaneously turned off. Vb will jump due to the turn-off of S3 and S4, and OP1 needs a relatively long time to stabilize Vb. When Vb is not stable, the output of op-amp OP2 will change drastically, thus affecting the current of MP1. Therefore, a NAND gate is added... Figure 5 The NAND gate in the code is used to prevent instability of the Vbp voltage.

[0034] like Figure 6 The diagram shows the simulation results of the charge pump circuit. The top curve represents the current mismatch between transistors MN1 and MP1, the middle curve represents the current magnitudes of transistors MN1 and MP1, and the bottom curve represents the output voltage Vout of the charge pump. It can be seen that within the voltage range of Vout from 0.5V to 2.8V, the maximum current mismatch is 7.19nA, accounting for 0.0072% of the total current. In traditional charge pumps, the current mismatch caused by the channel length modulation effect can reach more than 1% of the total current.

[0035] In summary, the low-current mismatch charge pump circuit for phase-locked loops described in the above embodiments directly controls the current source through the control loop, avoiding errors introduced by using a reference current branch and ensuring current matching; and NAND gate circuits are added to avoid instability of the current source bias voltage during inherent pulses.

[0036] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A low-current mismatch charge pump circuit for a phase-locked loop, characterized in that, The system includes a PMOS transistor MP1, an NMOS transistor MN1, switches S1-S4, an operational amplifier OP1, a current detection unit, and a current-to-voltage and amplification unit. Switches S1-S4 form a switch matrix, with switches S1 and S2 on one side of the matrix and switches S4 and S3 on the other side. Switches S2 and S4 are on top, and switches S3 and S1 are on the bottom. The source of PMOS transistor MP1 is connected to the VDD power supply, the drain is connected to node Y, and the gate is connected to the output of the current-to-voltage and amplification unit. The output of the current-to-voltage and amplification unit provides a bias voltage Vbp for PMOS transistor MP1. Node Y is located between switches S2 and S4. The source of NMOS transistor MN1 is grounded, the drain is connected to node X, and the gate is connected to the bias voltage Vbn. Node X is located between switches S3 and S1. The inverting input of operational amplifier OP1 is connected between switches S4 and S3, and the non-inverting input is connected between switches S1 and S2. The output is sequentially connected to the current detection unit and the current-to-voltage and amplification unit.

2. The low-current mismatch charge pump circuit for a phase-locked loop according to claim 1, characterized in that, The current detection unit includes a current detection resistor R1. One end of the current detection resistor R1 is connected to the output terminal of the operational amplifier OP1, and the other end is connected to the input terminal of the current-to-voltage and amplification unit.

3. A low-current mismatch charge pump circuit for a phase-locked loop according to claim 2, characterized in that, The current-to-voltage and amplification unit includes operational amplifier OP2. The other end of the current sensing resistor R1 is connected to the non-inverting input terminal of operational amplifier OP2. At the same time, the output terminal of operational amplifier OP1 is directly connected to the inverting input terminal of operational amplifier OP2. The output terminal of operational amplifier OP2 is used to provide bias voltage Vbp.

4. A low-current mismatch charge pump circuit for a phase-locked loop according to claim 3, characterized in that, When the voltages of nodes Vc and Vb are kept consistent by the control of operational amplifier OP1, the mismatch current of PMOS transistors MP1 and NMOS transistors MN1 will be provided by operational amplifier OP1. The magnitude of the mismatch current is determined by detecting the voltage difference across the current sensing resistor R1. The voltage across the current sensing resistor R1 is fed into operational amplifier OP2 to adjust the current of PMOS transistors MP1 and NMOS transistors MN1. When the currents of PMOS transistors MP1 and NMOS transistors MN1 are the same, the mismatch current is eliminated. At this time, the current flowing through the current sensing resistor R1 is 0, and the voltages of nodes Va and Vb are equal. Node Vc is located between switches S1 and S2, and nodes Vb and Va are located across the current sensing resistor R1.

5. A low-current mismatch charge pump circuit for a phase-locked loop according to claim 4, characterized in that, The switch S1 is controlled to be turned on and off by the digital signal dn, the switch S2 is controlled to be turned on and off by the digital signal up, the switch S3 is controlled to be turned on and off by the digital signal dnb, and the switch S4 is controlled to be turned on and off by the digital signal upb. When up=1, upb=0, and when dn=1, dnb=0. The digital signals up and dn control the switches S2 and S1 respectively to realize the charging and discharging of node Vc, and the digital signals upb and dnb control the switches S4 and S3 respectively to realize the charging and discharging of node Vb.

6. A low-current mismatch charge pump circuit for a phase-locked loop according to claim 5, characterized in that, The charge pump circuit also includes a NAND gate and a switch S6. The switch S6 is located between the output terminal of the operational amplifier OP2 and the gate of the PMOS transistor MP1. The two ends of the NAND gate are respectively input with digital signals up and dn. When both digital signals up and dn are 1, the switch S6 is turned off.

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