Optical proximity effect correction optimization method

Abstract

The invention provides an optical proximity effect correction optimization method comprising the following steps: providing an initial layout, dividing the initial layout into a plurality of small blocks, each small block comprising a main pattern area and an expansion area surrounding the main pattern area, each small cell block is overlapped with the expansion area of the adjacent small cell block; oPC correction and simulation verification are carried out on each small block, and a problem graph and a plurality of suspected weapon graphs appear in an overlapping area between two adjacent small blocks in a simulation verification graph; finding out a target lethal graph causing the problem graph from all the suspected lethal graphs; optimizing the target lethal graphs in all the small blocks to obtain an intermediate layout; and performing OPC correction on the intermediate layout so as to greatly reduce the EPE at the edge of the small area and solve the problem that the verification result of the OPC correction is not convergent.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to an optical proximity correction (OPC) optimization method. BACKGROUND

[0002] Due to the continuous shrinkage of process nodes, optical proximity correction (OPC) is widely used in integrated circuit design. In the process of optical proximity correction, in order to accelerate the efficiency of OPC correction, the design pattern is usually divided into several small blocks (templates) by calculation software, and different small blocks can be calculated simultaneously by software. As shown in Figure 1 Each small block includes a main pattern area and an extension area extending outward from the main area, and the overlapping area between two adjacent small blocks includes the extension area of each other, for example, small block 1 includes main pattern area MA1 and extension area slot1, small block 2 includes main pattern area MA2 and extension area slot2, and extension area slot1 overlaps with main pattern area MA2, and extension area slot2 overlaps with main pattern area MA1. Each small block simultaneously performs OPC correction on the main area of another small block during OPC correction, and due to the different correction parameters of the two small blocks, the sizes of the two small blocks after OPC correction in the overlapping area are inconsistent, resulting in an increase in EPE (Edge Placement Error) at the edge of the small block (i.e. the overlapping area), and the verification result of OPC correction does not converge, which seriously affects the product yield. SUMMARY

[0003] The purpose of the present application is to provide an optical proximity correction optimization method, which can reduce the EPE at the edge of the small area and solve the problem of non-convergence of OPC correction results.

[0004] In order to solve the above technical problems, the present application provides an optical proximity correction optimization method, comprising the following steps:

[0005] An initial layout is provided, the initial layout is divided into several small blocks, the small blocks include a main pattern area and an extension area surrounding the main pattern area, and each small block overlaps with the extension area of the adjacent small block;

[0006] OPC correction and simulation verification are performed on each small block, and problem patterns and several suspected killer patterns appear in the overlapping area between two adjacent small blocks in the simulation verification pattern;

[0007] The target killer pattern causing the problem pattern to appear is found from all the suspected killer patterns;

[0008] The target killer pattern in all the small blocks is optimized to obtain an intermediate layout;

[0009] OPC correcting the intermediate layout.

[0010] Optionally, the main pattern region is in a rectangular shape, and the extension region is in a rectangular ring shape.

[0011] Further, the specific method for dividing the initial layout into small blocks comprises:

[0012] The side length of the main pattern region is fixed, and the outer ring side of the extension region is gradually extended outward by a preset length from the corresponding side of the main pattern region. After each extension, the small blocks are subjected to OPC correction and simulation verification. When the EPE simulation value in the overlap region is greater than the EPE design value, the extension of the outer ring side of the extension region is stopped to obtain the divided small blocks.

[0013] Further, the specific method for dividing the initial layout into small blocks comprises:

[0014] The outer side length of the extension region is fixed, and the side of the main pattern region is gradually shrunk inward by a preset length from the corresponding outer side of the extension region. After each shrinkage, the small blocks are subjected to OPC correction and simulation verification. When the EPE simulation value in the overlap region is greater than the EPE design value, the shrinkage of the main pattern region is stopped to obtain the divided small blocks.

[0015] Optionally, the overlap region comprises a Z-shaped pattern, and the problem pattern is located on the Z-shaped pattern.

[0016] Optionally, the suspected culprit pattern is a step-shaped line.

[0017] Further, the specific method for finding the target culprit pattern comprises:

[0018] Fragmenting the pattern line where the problem pattern is located, and obtaining a plurality of cutting points, the cutting points being small clipping regions arranged at a preset length interval between adjacent cutting points;

[0019] Taking all the cutting points in the problem pattern as the center, projecting the cutting points in the direction of increasing EPE simulation value, and performing parallel search inspection to find the suspected culprit pattern that is aligned with the step edge as the target culprit pattern.

[0020] Further, the small clipping region is in a square shape.

[0021] Further, the specific method for optimizing the target culprit pattern in all the small blocks comprises:

[0022] moving the step edge of the target killer pattern so that the step edge moves towards the direction of the main pattern area adjacent to the main pattern area where the target killer pattern is located.

[0023] Optionally, the specific method for performing OPC correction on the intermediate layout comprises:

[0024] performing OPC correction and simulation verification on the intermediate layout, and when no problem pattern appears in the overlapping area in the verification result, using the layout after OPC correction as the final layout.

[0025] Compared with the prior art, the present application has the following unexpected technical effects:

[0026] The present application provides an optical proximity effect correction optimization method, comprising the following steps: providing an initial layout, dividing the initial layout into a plurality of small blocks, the small blocks comprising a main pattern area and an extension area surrounding the main pattern area, each of the small blocks overlapping with the extension area of the adjacent small block; performing OPC correction and simulation verification on each of the small blocks, and in the simulation verification pattern, problem patterns and a plurality of suspected killer patterns appear in the overlapping area between two adjacent small blocks; finding a target killer pattern causing the problem pattern to appear from all the suspected killer patterns; optimizing the target killer pattern in all the small blocks to obtain an intermediate layout; performing OPC correction on the intermediate layout to greatly reduce the EPE at the edge of the small area, and solving the problem that the verification result of OPC correction does not converge. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a schematic view of the positions of two small blocks.

[0028] Figure 2 is a schematic view of the original layout of two small blocks.

[0029] Figure 3 is an enlarged schematic view of the X block in Figure 2

[0030] Figure 4 is a flowchart of an optical proximity effect correction optimization method provided by an embodiment of the present application.

[0031] Figure 5 is a schematic view of the positions of two adjacent small blocks provided by an embodiment of the present application.

[0032] Figure 6 is a problem pattern and a suspected killer pattern in the overlapping area of two adjacent small blocks provided by an embodiment of the present application.

[0033] Figure 7 ​The modification method of the murderer pattern provided by an embodiment of the present application.

[0034] Reference numerals:

[0035] Figures 1-3 In the figure, 1, 2 - cell blocks;

[0036] Figures 5-7 In the figure, 10, 20 - cell blocks; 11, 21 - main pattern areas; 12, 22 - extension areas; 121, 221 - overlapping areas; 30 - small clip areas; 40 - target murderer pattern. DETAILED DESCRIPTION

[0037] The following will further describe an optical proximity effect correction optimization method of the present application. The present application will be described in more detail below with reference to the accompanying drawings, which show preferred embodiments of the present application. It should be understood that those skilled in the art can modify the present application described herein while still achieving the advantageous effects of the present application. Therefore, the following description should be understood as a broad knowledge for those skilled in the art, and not as a limitation on the present application.

[0038] For clarity, not all features of actual embodiments are described. In the following description, well-known functions or constructions are not described in detail because they can obscure the understanding of the present application due to unnecessary details. It should be understood that in the development of any actual embodiment, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which vary from one implementation to another. Moreover, it should be understood that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0039] To make the purpose and features of the present application more obvious and easy to understand, the specific embodiments of the present application will be further described below with reference to the accompanying drawings. It should be noted that the drawings are very simplified and use non-precise ratios, only to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0040] It should be explained that: in order to clearly show Figure 6 In the figure, Figure 6 In the figure, A1 is the straight line where the edge of the overlapping area of the cell block 20 and the cell block 10 in the main pattern area 11 is located, A2 is the boundary line of the main pattern area 11 and the main pattern area 12, and A3 is the straight line where the edge of the overlapping area of the cell block 20 and the cell block 10 in the main pattern area 21 is located.

[0041] The current method for layout optimization is:

[0042] First, the initial layout is divided into several small blocks; then, each small block is OPC corrected; then, the OPC corrected layout is simulated and verified (OPCV) to obtain a verification result, which includes the EPE (Edge Placement Error) at the edge of the small block (i.e. the overlapping area), wherein when the EPE simulation value is greater than the EPE design value, return to the step of "OPC correction of each small block"; when the EPE simulation value is less than the EPE design value, the OPC layout is the final layout that can form a mask.

[0043] As shown in Figure 2 , in the simulation verification process, a problem pattern X appears in the overlapping area slot1, which appears in the main pattern area MA2, which overlaps the correction of small block 1 and the correction of small block 2. The superposition of the twice corrected patterns appears EPE simulation value greater than EPE design value (as shown in Figure 3 , for example, EPE is 8.5nm, i.e. EPE (for example, 8.5nm) increases at the edge of the small block, and the verification result of the OPC correction appears divergence, which seriously affects the product yield.

[0044] Figure 4 A flowchart of an optical proximity effect correction optimization method provided by the embodiment. As shown in Figure 4 , the embodiment provides an optical proximity effect correction optimization method, which comprises the following steps:

[0045] Step S1: providing an initial layout, dividing the initial layout into several small blocks, the small blocks including a main pattern area and an extension area surrounding the main pattern area, each small block overlapping with the extension area of the adjacent small block;

[0046] Step S2: OPC correction and simulation verification of each small block, and problem patterns and several suspected killer patterns appear in the overlapping area between the adjacent two small blocks in the simulation verification pattern;

[0047] Step S3: finding out the target killer pattern causing the problem pattern from all the suspected killer patterns;

[0048] Step S4: optimizing the target killer pattern in all the small blocks to obtain an intermediate layout;

[0049] Step S5: OPC correction of the intermediate layout.

[0050] The above method can greatly reduce the EPE at the edge of the small area, and solve the problem of divergence of the verification result of the OPC correction.

[0051] The following will be described in combination withFigures 5-7 An optical proximity effect correction optimization method provided by the embodiment is described in detail.

[0052] As shown in Figure 5 , first, step S1 is performed to provide an initial layout, and the initial layout is divided into a plurality of small blocks, the small blocks including a main pattern area and an extension area surrounding the main pattern area, and each of the small blocks overlapping with the extension area of an adjacent small block.

[0053] This step specifically includes:

[0054] First, an initial layout is provided, and the initial layout is divided into a plurality of small blocks by software. Each of the small blocks includes a main pattern area and an extension area surrounding the main pattern area, and each of the overlapping areas includes the total area of the extension area of two adjacent small blocks in the main pattern area of the other. The small blocks and the main pattern area are rectangular, and the extension area is a rectangular ring. See Figure 5 For example, two adjacent small blocks 10 and 20 in a first direction, small block 10 includes a main pattern area 11 and an extension area 12, small block 20 includes a main pattern area 21 and an extension area 22, the extension area 12 of small block 10 has an overlapping area 121 with the main pattern area 21, and the extension area 22 of small block 20 has an overlapping area 221 with the main pattern area 11, so the overlapping area between small block 10 and small block 20 includes overlapping area 121 and overlapping area 221.

[0055] The specific way of dividing the initial layout into a plurality of small blocks is that at least two division methods of the initial layout (i.e., at least including division method one and division method two) are designed in the software. Specifically:

[0056] Division method one: the length of the side of the main pattern area is fixed, and the outer ring side of the extension area is gradually expanded outward from the corresponding side of the main pattern area by a preset length, and needs to be corrected and simulated for OPC at each time of expansion, and in the simulation verification process, when the EPE simulation value in the overlapping area is less than the EPE design value, the outer ring side of the extension area is further expanded; when the EPE simulation value in the overlapping area is greater than the EPE design value, the expansion of the outer ring side of the extension area is stopped, and the divided small blocks are obtained. It should be noted that the preset length of each expansion can be the same or different, which can be adjusted according to actual needs.

[0057] The second division manner is to fix the outer edge length of the extension region, and gradually shrink the edge of the main pattern region inward by a preset length from the corresponding outer edge of the extension region, and each time the edge is shrunk, the small blocks need to be corrected and simulated. In the simulation verification process, when the EPE simulation value of the overlapping region is less than the EPE design value, the edge of the main pattern region is further shrunk; when the EPE simulation value of the overlapping region is greater than the EPE design value, the shrinking of the main pattern region is stopped, and the divided small blocks are obtained. It should be noted that the preset length of each shrinkage can be the same or different, and can be adjusted according to actual needs.

[0058] Then step S2 is performed: correcting and simulating each small block, and in the simulation verification pattern, the problem pattern and a plurality of suspected murderer patterns appear in the overlapping region between the adjacent two small blocks.

[0059] This step specifically includes the following steps:

[0060] First, find the problem pattern and a plurality of suspected murderer patterns in the overlapping region, wherein the suspected murderer patterns are located near the problem pattern and all suspected murderer patterns near the problem pattern in the direction perpendicular to the extension direction of the problem pattern. At this time, the number of suspected murderer patterns is at least one. It is found that the problem pattern usually occurs in the stepped pattern in the overlapping region, such as the Z-shaped pattern.

[0061] As shown in Figures 6-7 , a problem pattern appears in the Z-shaped pattern of the overlapping region, that is, a local line pattern in the Z-shaped pattern whose EPE simulation value is greater than the EPE design value. In Figures 6-7 , the problem pattern extends along the first direction a, and then the suspected murderer patterns of the problem pattern appear in the second direction b near the problem pattern. Among them, the suspected murderer pattern is a straight line in the initial pattern, but it appears as a stepped line in the simulation pattern.

[0062] Then step S3 is performed: finding the target murderer pattern causing the problem pattern from all the suspected murderer patterns. In detail, the pattern line where the problem pattern is located is fragmented, and a plurality of cutting points are obtained, which are small clipping regions arranged at a preset length interval between adjacent cutting points. Then, taking all the cutting points in the problem pattern as the center, project the cutting points in the direction of increasing EPE simulation value, and perform parallel search checking to find the suspected murderer pattern whose stepped edge is aligned with the cutting point as the target murderer pattern. Among them, the small clipping region can be a 10 μm*10 μm square region.

[0063] As shown in Figure 6Taking the example of the Z-shaped pattern in the overlapping area (such as...) as an example, Figure 3 Example of determining whether a suspected culprit graphic is the target culprit graphic: The problematic graphic appears on the line where the simulated EPE value is greater than the designed EPE value, and there is a stepped, suspected culprit graphic below the problematic graphic.

[0064] First, locate the corner points c1 and c2 of the Z-shaped figure; then, find an extension line Y parallel to the second direction extending from the edge of the suspected culprit figure's step. This extension line Y intersects with the line containing the problem figure. Locate this intersection point, such as... Figure 6 The intersection point is point B2.

[0065] Next, along the lines containing the problem image, starting from corner point c1 and moving towards intersection point B2, find the positions where the small clipping area 30 can be placed. Figure 6 First, starting from corner point c1, a small clipping region 30 is placed at the endpoint B1 of a line segment of length C. Then, corner point c2 is projected onto the line containing the problem figure. If the distance between the projections of point B1 and corner point c2 is less than the design value Lmin, no small clipping region 30 is placed at the projection of corner point c2. If the distance between the projections of point B1 and corner point c2 is between the design values ​​Lmin and Lmax, a small clipping region 30 needs to be placed at the projection of corner point c2. Then, starting from point B1, several points with lengths between the design values ​​Lmin and Lmax are found in sequence along the direction from corner point c1 to intersection point B2, and a small clipping region 30 is placed at each of these points. The spacing between point B1 and intersection point B2 is designed to be between Lmin and Lmax. For example, when it is L1, a small clipping region 30 is placed at intersection point B2. When the spacing between point B1 and intersection point B2 is not between Lmin and Lmax, a small clipping region 30 is placed near intersection point B2 at a position that meets the design requirements. Simultaneously, small clipping regions 30 are placed on other lines in the overlapping area, and these positions meet the preset length requirement, i.e., between Lmin and Lmax. Since intersection point B2 and the edge of the step of the suspected murderer graphic are on the same extension line Y, i.e., the edge of the step of the suspected murderer graphic is aligned with the cutting point, the suspected murderer graphic is the target murderer graphic 40. Next, step S4 is executed to optimize the target murderer graphic in all the small blocks to obtain an intermediate layout.

[0066] Specifically, the edge of the step in the target murderer's graphic is moved so that it moves towards the main graphic area adjacent to the main graphic area where the target murderer's graphic is located. For example... Figure 7As shown, when the target killer pattern 40 is located in the main pattern area 12 (i.e. the overlapping area 121), the step edge is moved towards the main pattern area 11 in the first direction a. When the target killer pattern 40 is located in the main pattern area 11 (i.e. the overlapping area 221), the step edge is moved towards the main pattern area 12 in the first direction a to form an intermediate layout, thereby ensuring the profile convergence consistency of the overlapping area between adjacent small blocks in the OPC correction process.

[0067] In the projection of each corner point on the Z-shaped pattern where the problem pattern is located on the target killer pattern 40, when the distance M between the nearest projection to the step edge and the step edge is less than the design value, the step edge is moved to the position of the small clipping area 30 near the projection; when the distance M between the nearest projection to the step edge and the step edge is greater than the design value, the step edge is moved to the projection.

[0068] Then, step S5 is performed to perform OPC correction on the intermediate layout. In detail, the intermediate layout is subjected to OPC correction and simulation verification. When no problem pattern appears in the overlapping area in the verification result, i.e. no problem pattern appears in the verification result, the layout after OPC correction is used as the final layout; when the problem pattern of EPE simulation value greater than EPE design value still appears in the overlapping area in the verification result, the target killer pattern is further optimized in step S3 until no problem pattern appears in this step. It is found that the EPE simulation value at the position where the problem pattern appears is reduced from the existing 8.5 nm to 0.5 nm in simulation simulation when the final layout is obtained by the method of the embodiment, thereby reducing the line width (CD) error by 95%.

[0069] In summary, the present application provides an optical proximity effect correction optimization method, which comprises the following steps: providing an initial layout, dividing the initial layout into a plurality of small blocks, the small blocks comprising a main pattern area and an expansion area surrounding the main pattern area, each small block overlapping with the expansion area of an adjacent small block; performing OPC correction and simulation verification on each small block, and a problem pattern and a plurality of suspected killer patterns appear in the overlapping area between two adjacent small blocks in the simulation verification pattern; finding a target killer pattern causing the problem pattern from all the suspected killer patterns; optimizing the target killer pattern in all the small blocks to obtain an intermediate layout; performing OPC correction on the intermediate layout to greatly reduce the EPE at the edge of the small area, thereby solving the problem of non-convergence of the verification result of OPC correction.

[0070] In addition, it needs to be explained that, unless specifically described or indicated, the terms "first", "second" in the description are only used to distinguish the components, elements, steps, etc. in the description, and are not used to represent the logical relationship or the sequence relationship between the components, elements, steps, etc.

[0071] It can be understood that, although the present application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present application. For any person skilled in the art, many possible changes and modifications, or equivalent embodiments of equivalent changes can be made to the technical solutions of the present application by using the disclosed technical contents without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solutions of the present application, still belongs to the scope of protection of the technical solutions of the present application.

Claims

1. An optical proximity correction optimization method, characterized by, The method comprises the following steps: providing an initial layout, dividing the initial layout into a plurality of small blocks, the small blocks comprising a main pattern area and an extension area surrounding the main pattern area, each of the small blocks overlapping with the extension area of an adjacent small block; OPC correcting and simulation verifying each of the small blocks, and in the simulation verification pattern, a problem pattern and a plurality of suspected culprit patterns appear in the overlapping area between two adjacent small blocks; finding a target culprit pattern causing the problem pattern from all the suspected culprit patterns; optimizing the target culprit pattern in all the small blocks to obtain an intermediate layout; OPC correcting the intermediate layout.

2. The optical proximity correction optimization method of claim 1, wherein, The main pattern area is in the shape of a rectangle, and the extension area is in the shape of a rectangular ring.

3. The optical proximity correction optimization method of claim 2, wherein, The specific method of dividing the initial layout into a plurality of small blocks comprises: fixing the side length size of the main pattern area, and gradually expanding the outer ring side of the extension area outward by a preset length from the corresponding side of the main pattern area, after each expansion, OPC correcting and simulation verifying the small blocks, and when the EPE simulation value in the overlapping area is greater than the EPE design value, stopping the expansion of the outer ring side of the extension area to obtain the divided small blocks.

4. The optical proximity correction optimization method of claim 3, wherein, The specific method of dividing the initial layout into a plurality of small blocks comprises: fixing the outer side length size of the extension area, and gradually shrinking the side of the main pattern area inward by a preset length from the corresponding outer side of the extension area, after each shrinkage, OPC correcting and simulation verifying the small blocks, and when the EPE simulation value in the overlapping area is greater than the EPE design value, stopping the shrinkage of the main pattern area to obtain the divided small blocks.

5. The optical proximity correction optimization method of claim 1, wherein, The overlapping area comprises a Z-shaped pattern, and the problem pattern is located on the Z-shaped pattern.

6. The optical proximity correction optimization method of claim 1, wherein, The suspected culprit pattern is a stepped line.

7. The optical proximity correction optimization method of claim 6, wherein, The specific method of finding the target culprit pattern comprises: fragmenting the pattern line where the problem pattern is located to obtain a plurality of cutting points, the cutting points being small clipping areas arranged at a preset length interval between adjacent cutting points; projecting the cutting points toward the direction of increasing EPE simulation value with all the cutting points in the problem pattern as the center, and performing parallel search checking to find the suspected culprit pattern aligned with the step edge as the target culprit pattern.

8. The optical proximity correction optimization method of claim 7, wherein, The shape of the small clipping area is a square.

9. The optical proximity correction optimization method of claim 6, wherein, The specific method of optimizing the target culprit pattern in all the small blocks comprises: moving the step edge of the target culprit pattern so that the step edge moves toward the direction of the main pattern area adjacent to the main pattern area where the target culprit pattern is located.

10. The optical proximity correction optimization method of claim 1, wherein, The specific method of OPC correcting the intermediate layout comprises: OPC correcting and simulation verifying the intermediate layout, and when no problem pattern appears in the overlapping area in the verification result, the OPC corrected layout is used as the final layout.

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