Demodulation circuit and digital isolator

Abstract

The invention provides a demodulation circuit and a digital isolator. The demodulation circuit comprises a waveform regulator, a first counter, a second counter and an SR latch. The waveform adjuster generates an adjusted modulation signal from a differential isolation modulation signal generated by modulating an input data signal with a carrier clock signal. The first counter counts a period of the adjusted modulation signal to generate a set signal. The second counter counts cycles of a reference clock signal to generate a reset signal. The SR latch comprises: a setting end, which is used for receiving the setting signal; the reset end is used for receiving the reset signal; and the output end is used for outputting the demodulated output signal. And the SR latch is triggered by the setting signal to pull up the demodulated output signal, and is triggered by the reset signal to pull down the demodulated output signal.

Description

TECHNICAL FIELD

[0001] The present invention relates to a demodulation circuit, and more particularly, to a demodulation circuit applied in a digital isolator. BACKGROUND

[0002] A digital isolator is a device that provides electrical isolation between two digital systems while enabling data transfer. Such isolation is critical for safety and noise rejection in many electronic systems, especially in industrial and automotive applications. A digital isolator allows one circuit to transmit digital signals across an isolation barrier to another circuit without physical contact or direct electrical connection. The isolation barrier is typically implemented by capacitive coupling, magnetic coupling, or optical isolation.

[0003] One of the key challenges for a digital isolator is to meet the common mode transient immunity (CMTI) requirement. Common mode transients are sudden voltage spikes or fluctuations between the grounds of the circuits on either side of the isolation barrier. If not properly handled, these transients can cause errors in the digital isolator. SUMMARY

[0004] One aspect of the present invention provides a demodulation circuit. The demodulation circuit includes a waveform conditioner, a first counter, a second counter, and a set-reset (SR) latch. The waveform conditioner is configured to generate a conditioned modulation signal from a pair of differential isolated modulation signals. The differential isolated modulation signals are generated by modulating an input data signal with a carrier clock signal. The first counter includes a clock input receiving the conditioned modulation signal, a reset input, and an output outputting a set signal. The second counter includes a clock input receiving a reference clock signal, a reset input receiving the conditioned modulation signal, and a first output outputting a reset signal. The SR latch includes a set input connected to the output of the first counter, a reset input connected to the output of the second counter, and an output outputting a demodulated output signal. The first counter generates the set signal by counting the number of cycles of the conditioned modulation signal and triggers the SR latch to pull up the demodulated output signal. The second counter generates the reset signal by counting the number of cycles of the reference clock signal and triggers the SR latch to pull down the demodulated output signal.

[0005] Another aspect of the present invention provides a digital isolator. The digital isolator includes the aforementioned demodulation circuit and an isolation circuit. The isolation circuit receives a pair of differential modulation input signals generated by modulating an input data signal with a carrier clock signal and outputs the pair of differential isolated modulation signals.

[0006] The present invention aims to provide a demodulation circuit and a digital isolator to meet the common mode transient immunity (CMTI) requirement.

[0007] To achieve the above object, the present application provides a demodulation circuit, comprising: a waveform adjuster configured to generate an adjusted modulation signal according to a pair of differential isolated modulation signals, wherein the differential isolated modulation signals are generated by modulating an input data signal with a carrier clock signal; a first counter comprising: a clock input configured to receive the adjusted modulation signal; a reset input; and an output configured to output a set signal; a second counter comprising: a clock input configured to receive a reference clock signal; a reset input configured to receive the adjusted modulation signal; and a first output configured to output a reset signal; and a first set-reset (SR) latch comprising: a set input coupled to the output of the first counter; a reset input coupled to the first output of the second counter; and an output configured to output a demodulated output signal; wherein the first counter is configured to count periods of the adjusted modulation signal to generate the set signal and trigger the first SR latch to pull up the demodulated output signal, and the second counter is configured to count periods of the reference clock signal to generate the reset signal and trigger the first SR latch to pull down the demodulated output signal.

[0008] In an example, the second counter further comprises a second output coupled to the reset input of the first counter, and the second counter is further configured to output an enable reset signal through the second output when a duration that the adjusted modulation signal remains at a logical low level exceeds a duration that a first predetermined number of periods of the reference clock signal.

[0009] In an example, the first counter is configured to generate the set signal when a second predetermined number of periods of the adjusted modulation signal are counted and the enable reset signal is not received.

[0010] In an example, the second counter is configured to generate the reset signal when the adjusted modulation signal remains at the logical low level and a third predetermined number of periods of the reference clock signal are counted.

[0011] In an example, the first, second, and third predetermined numbers of periods are programmable.

[0012] In an example, the first counter further comprises a counter register, and the output of the first counter is coupled to a most significant bit of the counter register to output the set signal.

[0013] In an example, the second counter further comprises a counter register, and the first output of the second counter is coupled to a most significant bit of the counter register to output the reset signal.

[0014] In an example, the demodulation circuit further includes an OR gate including a plurality of input terminals coupled to a plurality of most significant bits of the counter register, and an output terminal coupled to a reset terminal of the first counter and configured to output an on-pulse reset signal.

[0015] In an example, the reference clock signal has a frequency equal to a frequency of the carrier clock signal.

[0016] In an example, the waveform regulator adjusts a duty cycle of the adjusted modulation signal to be substantially equal to 50% when the differential isolated modulation signal periodically toggles.

[0017] In an example, the waveform regulator includes a hysteretic comparator including a non-inverting input terminal configured to receive a first isolated modulation signal of the differential isolated modulation signal, an inverting input terminal configured to receive a second isolated modulation signal of the differential isolated modulation signal, and an output terminal, a D flip-flop including a data terminal configured to receive a supply voltage, a clock terminal coupled to the output terminal of the hysteretic comparator, a reset terminal, and an output terminal configured to output the adjusted modulation signal, and a delay circuit including an input terminal coupled to the output terminal of the D flip-flop, and an output terminal coupled to the reset terminal of the D flip-flop.

[0018] In an example, the delay circuit includes a plurality of cascaded inverters.

[0019] In an example, the delay circuit includes a resistor including a first terminal coupled to the input terminal of the delay circuit, a second terminal coupled to the output terminal of the delay circuit, and a capacitor including a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to a ground node.

[0020] In an example, the waveform regulator includes a first hysteretic comparator including a non-inverting input terminal configured to receive a first isolated modulation signal of the differential isolated modulation signal, an inverting input terminal configured to receive a second isolated modulation signal of the differential isolated modulation signal, and an output terminal, a second hysteretic comparator including a non-inverting input terminal configured to receive the second isolated modulation signal, an inverting input terminal configured to receive the first isolated modulation signal, and an output terminal, and a second SR latch including a set terminal coupled to the output terminal of the second hysteretic comparator, a reset terminal coupled to the output terminal of the first hysteretic comparator, and an output terminal configured to output the adjusted modulation signal.

[0021] The application also provides a digital isolator, comprising: the demodulation circuit as described above; and an isolation circuit configured to receive a pair of differential modulated input signals generated by modulating an input data signal with a carrier clock signal, and output the pair of differential isolated modulated signals.

[0022] In an example, the second counter further comprises a second output coupled to a reset terminal of the first counter, and the second counter is further configured to output a turn-on reset signal through the second output when a duration that the adjusted modulated signal remains at a logic low exceeds a duration of a first predetermined number of cycles of the reference clock signal.

[0023] In an example, the isolation circuit comprises: a first capacitor comprising a first terminal configured to receive a first modulated input signal of the pair of differential modulated input signals, a second terminal; a second capacitor comprising a first terminal configured to receive a second modulated input signal of the pair of differential modulated input signals, a second terminal; a third capacitor comprising a first terminal coupled to the second terminal of the first capacitor, a second terminal configured to output a first isolated modulated signal of the pair of differential isolated modulated signals; a fourth capacitor comprising a first terminal coupled to the second terminal of the second capacitor, a second terminal configured to output a second isolated modulated signal of the pair of differential isolated modulated signals; a first resistor comprising a first terminal coupled to the second terminal of the third capacitor, a second terminal; and a second resistor comprising a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the first resistor.

[0024] In an example, the isolation circuit further comprises: a third resistor comprising a first terminal configured to receive the first modulated input signal, a second terminal coupled to the first terminal of the first capacitor; and a fourth resistor comprising a first terminal configured to receive the second modulated input signal, a second terminal coupled to the first terminal of the second capacitor.

[0025] In an example, the digital isolator further comprises a modulation circuit configured to generate the pair of differential modulated input signals by modulating the input data signal with the carrier clock signal.

[0026] In one example, the modulation circuit includes an AND gate including a first input configured to receive the carrier clock signal, a second input configured to receive the input data signal, and an output configured to output a first modulation input signal of the differential modulation input signals, and an inverter including an input coupled to the output of the AND gate and an output configured to output a second modulation input signal of the differential modulation input signals.

[0027] In summary, compared with the prior art, the digital isolator and demodulation circuit provided by the present application adopts two counters to control the on and off time of the demodulation output signal. By utilizing the time measurement capability of the counters, the demodulation circuit can ignore the noise caused by different types of common mode transients, thereby reducing the glitches in the demodulation output signal, so that the digital isolator achieves high CMTI. In addition, since the on glitch removal threshold number, the off glitch removal threshold number and the maximum allowed off time can be programmed by the counters, this also provides great flexibility for circuit design. BRIEF DESCRIPTION OF DRAWINGS

[0028] The present application can be more completely understood in consideration of the following detailed description and claims, with reference to the accompanying drawings, in which like reference numerals denote like elements throughout.

[0029] Figure 1 A digital isolator is shown as a first embodiment of the present application.

[0030] Figure 2 A digital isolator is shown as a first embodiment of the present application. Figure 1 A signal timing diagram of the digital isolator is shown.

[0031] Figure 3 A signal timing diagram of the digital isolator is shown. Figure 1 A glitch removal capability timing diagram of the digital isolator in one example case is shown.

[0032] Figure 4 A glitch removal capability timing diagram of the digital isolator in another example case is shown. Figure 1 A glitch removal capability timing diagram of the digital isolator in another example case is shown.

[0033] Figure 5 A digital isolator is shown as a second embodiment of the present application.

[0034] Figure 6 A digital isolator is shown as a third embodiment of the present application.

[0035] Figure 7 A digital isolator is shown as a fourth embodiment of the present application.

[0036] Figure 8 A digital isolator is shown as a fifth embodiment of the present application. DETAILED DESCRIPTION

[0037] The following description is taken in conjunction with the accompanying drawings, which form part of this specification and illustrate embodiments of the invention, but the invention is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to form other embodiments.

[0038] The terms "one embodiment," "embodiment," "exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments must include that particular feature, structure, or characteristic. Furthermore, repeated use of the phrase "in this embodiment" does not necessarily refer to the same embodiment.

[0039] To make the invention fully clear, the following description will provide detailed steps and structures. Obviously, the implementation of the invention is not limited to the specific details known to those skilled in the art. Furthermore, to avoid unnecessarily limiting the invention, known structures and steps will not be repeated. Preferred embodiments of the invention will be described in detail below, but in addition to the detailed description, the invention can also be widely implemented in other embodiments. The scope of the invention is not limited by the detailed description, but is defined by the claims.

[0040] Figure 1 A digital isolator 100 according to a first embodiment of the present invention is shown. The digital isolator 100 includes a modulation circuit 110, an isolation circuit 120, and a demodulation circuit 130. The digital isolator 100 provides isolation between the input side (e.g., the side where the modulation circuit 110 is located) and the output side (e.g., the side where the demodulation circuit 130 is located) through a capacitive isolation barrier in the isolation circuit 120. In some embodiments, the capacitor-based isolation circuit 120 can be considered as a high-pass filter or a band-pass filter capable of blocking low-frequency noise. In this case, to enable data transmission across the capacitive isolation barrier, the modulation circuit 110 uses a carrier clock signal SIG with a carrier frequency. CRCK Modulated input data signal SIG DIN , will low-frequency SIG DIN Converted to modulated input signal SIG MA1 and its complementary signal SIG MA2 Due to SIG MA1 and SIG MA2 All of them are high-frequency signals, so they can pass through the filter of isolation circuit 120.

[0041] Figure 2 Show the signal timing diagram of digital isolator 100. For example... Figure 2 As shown, during period P1, the input data signal SIG DIN When the logic level is high, the modulation circuit 110 will input the data signal SIG. DIN Modulated with carrier clock signal SIG CRCK High-frequency modulated input signal SIG of the same frequency MA1 and SIGMA2 Furthermore, during period P2, the input data signal SIG DIN When the logic level is low, the modulation circuit 110 modulates the input signal SIG. MA1 Keep it at logic low and modulate the input signal SIG. MA2 Maintain a logic high level.

[0042] Isolation circuit 120 receives modulated input signal SIG MA1 and SIG MA2 And outputs an isolated modulation signal SIG after filtering. MB1 and SIG MB2 Subsequently, demodulation circuit 130 isolates the modulated signal SIG. MB1 and SIG MB2 Demodulation is performed to obtain, as follows Figure 2 The input data signal SIG is shown. DIN Similar demodulated output signal SIG DOUT This enables data transmission across the isolation barrier. In this embodiment, the demodulation circuit 130 uses two counters (first counter 134 and second counter 136) to control the setting and resetting of the SR latch 138, thereby generating the demodulated output signal SIG. DOUT By utilizing the timing measurement capabilities of the first counter 134 and the second counter 136, the demodulation circuit 130 can ignore noise caused by common-mode transients, thereby reducing the demodulated output signal SIG. DOUT The glitch in the digital isolator 100 enables high CMTI.

[0043] The following section will provide more details and structure of the modulation circuit 110, isolation circuit 120, and demodulation circuit 130.

[0044] like Figure 1 As shown, the modulation circuit 110 includes an AND gate 112 and an inverter 114. The AND gate 112 includes a function for receiving the carrier clock signal SIG. CRCK The first input terminal is used to receive the input data signal SIG. DIN The second input terminal, and a SIG for outputting the modulation input signal. MA1 The inverter 114 includes: an input coupled to the output of the AND gate 112, and an output for outputting the modulated input signal SIG. MA2 The output terminal of the inverter 114. In this case, the modulated input signal SIG output by the inverter 114. MA2 The modulated input signal SIG output from AND gate 112 MA1 Complementary, modulated input signal SIG MA1 and SIG MA2The modulated input signal pair can be considered as a differential modulated input signal pair.

[0045] In the present embodiment, the modulation is implemented by an AND gate 112. However, in other embodiments, the modulation can also be implemented by other logic gates other than the AND gate 112. For example, a NAND gate can be employed instead of the AND gate 112 for data modulation. In addition, in some embodiments, in order to compensate for the delay introduced by the inverter 114, the modulated input signal SIG MA1 and the modulated input signal SIG MA2 may be synchronized, more inverters and / or non-inverting transmission gates can be added on the input path and the output path of the modulation circuit 110.

[0046] The isolation circuit 120 receives the differential modulated input signal pair SIG MA1 and SIG MA2 and outputs a differential isolated modulated signal pair SIG MB1 and SIG MB2 . As shown in FIG. 1, the isolation circuit 120 includes resistors R1 and R2, and capacitors C1, C2, C3 and C4. Figure 1

[0047] The capacitor C1 includes a first end for receiving the modulated input signal SIG MA1 and a second end. The capacitor C2 includes a first end for receiving the modulated input signal SIG MA2 and a second end. The capacitor C3 includes a first end coupled to the second end of the capacitor C1 and a second end for outputting the isolated modulated signal SIG MB1 . The capacitor C4 includes a first end coupled to the second end of the capacitor C2 and a second end for outputting the isolated modulated signal SIG MB2 . The resistor R1 includes a first end coupled to the second end of the capacitor C3 and a second end. The resistor R2 includes a first end coupled to the second end of the capacitor C4 and a second end coupled to the second end of the resistor R1.

[0048] In the isolation circuit 120, the capacitor-resistor network formed by the capacitors C1, C3, C2, C4 and the resistors R1, R2 is able to block low frequency noise and distinguish the modulated input signal pair SIG MA1 and SIG MA2 as signal transients (i.e. the isolated modulated signal pair SIG MB1 and SIG MB2 ). In some embodiments, the capacitance of the capacitors C1, C2, C3 and C4 can be the same, for example but not limited to about 70 fF, and the resistance of the resistors R1 and R2 can be the same, for example but not limited to less than or equal to 150 ohms (Ω).

[0049] ​Furthermore, in some embodiments, the modulation circuit 110 and capacitors C1 and C2 are arranged in one chip, while the demodulation circuit 130 and capacitors C3 and C4 are arranged in another chip, thereby ensuring isolation between the input and output stages of the digital isolator 100. In this case, the second ends of capacitors C1 and C2 are coupled to the first ends of capacitors C3 and C4, respectively, via bonding wires.

[0050] like Figure 1 As shown, the isolation circuit 120 also includes resistors R3 and R4. Resistor R3 is coupled between capacitor C1 and modulation circuit 110, and resistor R4 is coupled between capacitor C2 and modulation circuit 110. Resistor R3 includes: a pin coupled to the output of AND gate 112 to receive the modulated input signal SIG. MA1 The first terminal of the capacitor C1 and a second terminal coupled to the first terminal of the capacitor C1. Resistor R4 includes: a terminal coupled to the output of inverter 114 to receive the modulated input signal SIG. MA2 The first end and a second end coupled to the first end of capacitor C2.

[0051] Resistors R3 and R4 are used to increase the time constant of the isolation circuit 120, thereby slowing down the glitches at the input of the hysteresis comparator 1321 in the demodulation circuit 130, and enabling the hysteresis comparator 1321 to respond promptly. In some embodiments, the resistance values ​​of resistors R3 and R4 can be the same, for example, but not limited to, 500 ohms (Ω).

[0052] In addition, such as Figure 1 As shown, the isolation circuit 120 also includes capacitors C5 and C6. Capacitor C5 is the input capacitor of the hysteresis comparator 1321, and capacitor C6 is used to hold and indicate the differential isolation modulation signal SIG. MB1 and SIG MB2 The common-mode voltage. In some embodiments, capacitor C5 is crucial for the hysteresis comparator 1321 to receive input signals within the amplitude range. In some embodiments, the capacitance of capacitor C5 should be less than the capacitance of capacitors C1, C2, C3, or C4.

[0053] The demodulation circuit 130 includes a waveform conditioner 132, a first counter 134, a second counter 136, and a set / reset (SR) latch 138. The waveform conditioner 132 operates based on the differential isolation modulation signal SIG. MB1 and SIG MB2 Generate the regulated modulation signal SIG RM The first counter 134 is activated by the input data signal SIG. DIN It is a logic high level and is controlled by the carrier clock signal SIG. CRCK During modulation, a set signal SIG is generated. SETand triggers the SR latch 138 to pull up the demodulation output signal SIG DOUT . The second counter 136 generates a reset signal SIG DIN when the input data signal SIG RST is at a logic low level, and triggers the SR latch 138 to pull down the demodulation output signal SIG DOUT .

[0054] The waveform regulator 132 includes a hysteresis comparator 1321, a D flip-flop 1322, and a delay circuit 1323. The hysteresis comparator 1321 includes a non-inverting input terminal for receiving the isolated modulation signal SIG MB1 , an inverting input terminal for receiving the isolated modulation signal SIG MB2 , and an output terminal. The D flip-flop 1322 includes a data terminal for receiving a power supply voltage VCC, a clock terminal coupled to the output terminal of the hysteresis comparator 1321, a reset terminal, and an output terminal for outputting the regulated modulation signal SIG RM . The delay circuit 1323 includes an input terminal coupled to the output terminal of the D flip-flop 1322, and an output terminal coupled to the reset terminal of the D flip-flop 1322.

[0055] When the voltage at the non-inverting input terminal of the hysteresis comparator 1321 is higher than the voltage at the inverting input terminal by a threshold value, the output terminal of the hysteresis comparator 1321 assumes a high level. When the voltage at the inverting input terminal is higher than the voltage at the non-inverting input terminal by the threshold value, the output terminal of the hysteresis comparator 1321 assumes a low level. Thus, the hysteresis comparator 1321 converts signal transients (i.e., the isolated modulation signals SIG MB1 and SIG MB2 ) into pulses to trigger the D flip-flop 1322.

[0056] Each time the D flip-flop 1322 is triggered to output a logic high level, the delay circuit 1323 resets the D flip-flop 1322 after a fixed delay time. Since the isolated modulation signals SIG MB1 and SIG MB2 periodically jump during signal modulation, the fixed delay provided by the delay circuit 1323 allows the waveform regulator 132 to generate the regulated modulation signal SIG RM with a uniform duty cycle. In some embodiments, the waveform regulator 132 can regulate the duty cycle of the regulated modulation signal SIG RM to be about 50%, but the present application is not limited thereto.

[0057] The regulated modulation signal SIG RMThe signal is then received as a clock signal by the first counter 134 and as a reset signal by the second counter 136. Specifically, the first counter 134 includes: a clock input terminal for receiving the regulated modulation signal SIG. RM A reset terminal; and an output terminal for outputting the set signal SIG. SET The second counter 136 includes: a clock input for receiving a reference clock signal SIG. RFCK A reset pin is used to receive the regulated modulation signal SIG. RM A first output terminal is used to output the reset signal SIG. RST ; and a second output terminal, coupled to the reset terminal of the first counter 134, for outputting a turn-on reset signal SIG. ONRST The SR latch 138 includes: a set terminal coupled to the output of the first counter 134; a reset terminal coupled to the output of the second counter 136; and an output terminal for outputting the demodulated output signal SIG. DOUT .

[0058] When the adjusted modulation signal SIG RM A continuous jump may indicate that the input data signal SIG is being used. DIN It is a logic high level and is controlled by the carrier clock signal SIG. CRCK Modulation. At this time, the first counter 134 continuously modulates the adjusted modulation signal SIG. RM The counter counts periodically to determine whether the voltage jump is caused by signal modulation or transient noise. The first counter 134 generates a set signal SIG based on the counting result. SET And when the count reaches the predetermined number of cycles, the SR latch 138 is triggered to pull up the demodulated output signal SIG. DOUT .

[0059] For example, in Figure 2 During period P1, due to the input data signal SIG DIN Carrier clock signal SIG CRCK Modulation, the modulated signal SIG after adjustment RM The signal continues to change. At this point, the first counter 134 counts up to the adjusted modulation signal SIG. RM A logic high-level set signal SIG is generated after 8 cycles. SET SR latch 138 will demodulate the output signal SIG at time T1. DOUT Pulled high to logic high. In other words, the modulated signal SIG after counting adjustment. RM The first counter 134 can wait for a period of time after detecting its transition before sending the set signal SIG. SET, so as to ensure that the voltage jump is caused by stable data modulation and reduce glitches caused by unstable transients. Therefore, in the present application, the first counter 134 generates a set signal SIG SET , and the second counter 136 generates a reset signal SIG RM . The number of periods of the adjusted modulation signal SIG CRCK may also be referred to as the turn-on glitch threshold number.

[0060] In some embodiments, the frequency of the carrier clock signal SIG RM is 500MHz, for example, and by counting 8 periods of the adjusted modulation signal SIG RM , the first counter 134 will cause an input-output delay of 16ns, which is very short and acceptable for most cases. However, in some embodiments, the turn-on glitch threshold number can be programmed for the first counter 134 and adjusted as needed.

[0061] In addition, when the adjusted modulation signal SIG DIN remains at a logic low level (for example Figure 2 , the period P2), it can mean that the input data signal SIG RFCK is also at a logic low level. At this time, the second counter 136 counts the periods of the reference clock signal SIG RM to measure the duration of the adjusted modulation signal SIG DIN remaining at a logic low level, so as to determine whether its low level state is caused by the input data signal SIG RST or transient noise. Therefore, the second counter 136 generates a reset signal SIG DOUT according to the counting result, and triggers the SR latch 138 to pull down the demodulation output signal SIG RM when the count reaches a predetermined number of periods.

[0062] For example, in the period P2 Figure 2 , the adjusted modulation signal SIG RFCK remains at a logic low level, and the second counter 136 generates a reset signal SIG RST at a logic high level after counting 8 periods of the reference clock signal SIG RST . Therefore, the SR latch 138 will be reset by the reset signal SIG DOU , and the demodulation output signal SIG DOUT will be pulled low at time T2. In this way, the demodulation output signal SIG DIN can reproduce the waveform of the input data signal SIG RSTthe reference clock signal SIG RFCK whose period is counted

[0063] In some embodiments, the frequency of the reference clock signal SIG RFCK may be the same as the frequency of the carrier clock signal SIG CRCK , and the reference clock signal SIG RFCK may be generated by an oscillator different from the oscillator that generates the carrier clock signal SIG CRCK , because the modulation circuit 110 and the demodulation circuit 130 are arranged in different chips. In some embodiments, the reference clock signal SIG RFCK may be generated by an external oscillator, but the present application is not limited thereto. Furthermore, in Figure 2 (and subsequent Figure 3 and Figure 4 ), the reference clock signal SIG RFCK may be in phase with the carrier clock signal SIG CRCK , but the present application is not limited thereto. In some embodiments, the reference clock signal SIG RFCK and the carrier clock signal SIG CRCK may have a phase difference, resulting in slight edge transition inaccuracy, but this does not affect the debouncing function and the demodulation function of the demodulation circuit 130.

[0064] In the present embodiment, the first counter 134 can include a 4-bit counter register for recording the current count value. In this case, as the first counter 134 continues to count the period of the adjusted modulation signal SIG RM , the counter register can overflow, and the count value can be reset to zero. When the count value is reset to zero, the first counter 134 will stop outputting the set signal SIG SET at a logic high level, as shown in Figure 2 . Since the SR latch 138 can be implemented by an NOR gate, as long as the reset signal SIG RST is not received, the demodulation output signal SIG DOUT output therefrom will remain at a logic high level. Similarly, the second counter 136 can also include a 4-bit counter register for recording the current count value, and the count value can be reset to zero when the counter register overflows. Therefore, the second counter 136 will not continuously output the reset signal SIG RST at a logic high level as in the period P2 of Figure 2 . However, as mentioned previously, the SR latch 138 will remain at a logic low level until the next set signal SIG SET is received.

[0065] Since the first counter 134 can count the period of the adjusted modulation signal SIGRM After a predetermined number of cycles, a set signal SIG is generated. SET The SR latch 138 is triggered to pull up the demodulation output signal SIG. DOUT The second counter 136 can count the reference clock signal SIG. RFCK After a predetermined number of cycles, a reset signal SIG is generated. RST The SR latch 138 is triggered to pull the demodulation output signal SIG low. DOUT Therefore, it can reduce the demodulated output signal SIG caused by common-mode transients. DOUT Burrs.

[0066] Figure 3 The signal timing diagram of digital isolator 100 is shown, illustrating its glitching capability in an example scenario. For example... Figure 3 As shown, in the initial period P1, the input data signal SIG DIN The modulation signal SIG is at a logic high level. RM The signal continues to jump. Then, it counts up to the adjusted modulation signal SIG. RM After 8 cycles, the first counter 134 generates a logic high-level set signal SIG. SET And at time T1, the SR latch 138 is triggered to pull up the demodulated output signal SIG. DOUT .

[0067] exist Figure 3 At time T2, a common-mode transient occurs, causing the regulated modulation signal SIG to... RM Five pulses are lost. In this case, when the adjusted modulation signal SIG... RM When the logic level changes to low, the second counter 136 will start counting the reference clock signal SIG. RFCK The cycle. However, the second counter 136 counts to the reference clock signal SIG. RFCK During the 5th cycle, due to the adjusted modulation signal SIG RM When the second counter 136 returns to logic high at time T3, it will be reset. Since the second counter 136 has not reached the deglitch count (e.g., 8), a logic high reset signal SIG will not be generated. RST Demodulated output signal SIG DOUT In Figure 3 The logic remains high throughout the entire time period, unaffected by common-mode transients. In other words, the counting scheme of the second counter 136 avoids glitches caused by common-mode transients, thereby improving the CMTI of the digital isolator 100. The counting scheme of the first counter 134 can also achieve glitch removal capability.

[0068] Furthermore, common-mode transients can not only cause pulse loss but also trigger unexpected pulses. Therefore, the second counter 136 can also generate a turn-on reset signal SIG when an unexpected pulse is generated by a common-mode transient. ONRST This resets the first counter 134. Specifically, because the frequency of the accidental pulse may be low and the logic low level duration is long, the second counter 136 can measure the regulated modulation signal SIG. RM The shutdown time (i.e., the time it holds a logic low level), and if the shutdown time exceeds the maximum allowed shutdown time (e.g., the reference clock signal SIG), RFCK When the predetermined number of cycles corresponds to the duration, a turn-on reset signal SIG is output through the second output terminal. ONRST .

[0069] Figure 4 The signal timing diagram of digital isolator 100 is shown, demonstrating glitching capability in another example scenario. For example... Figure 4 As shown, due to the input data signal SIG DIN Keep the logic low and modulate the input signal SIG. MA1 Keep the logic low and modulate the input signal SIG. MA2 The logic level remains high. However, a common-mode transient occurs at time T1, causing the regulated modulation signal SIG to... RM Ten unexpected pulses occurred. At this point, the number of unexpected pulses exceeded the predetermined de-glitch threshold number of the first counter 134 (e.g., the adjusted modulation signal SIG). RM (8 cycles). However, because the turn-off time of each of these 10 pulses exceeds the maximum allowable turn-off time predetermined by the second counter 136 (e.g., the reference clock signal SIG), RFCK (2 cycles), the second counter 136 will reset the first counter 134 during each pulse.

[0070] Therefore, the count value of the first counter 134 will remain at 1 during these 10 pulses and will not reach the conduction de-glitch threshold (e.g., 8). Therefore, the first counter 134... Figure 4 No set signal SIG will be generated during the entire time period shown. SET At this point, even if a common-mode transient occurs, the demodulated output signal SIG will remain unchanged. DOUT It will still be related to the input data signal SIG DIN To maintain consistency, keep the logic low level. In some embodiments, the second counter 136 is used to determine the reference clock signal SIG for the maximum allowable shutdown time. RFCK The number of cycles is programmable and can be adjusted as needed.

[0071] In other words, the first counter 134 needs to generate a set signal SIG.SET And triggers SR latch 138 to pull up the demodulated output signal SIG. DOUT The modulated signal SIG after adjustment must be counted at least. RM The 8 cycles, and the off time in each cycle must not exceed the reference clock signal SIG. RFCK Two cycles. For example, although Figure 2 and Figure 3 The on / off reset signal SIG is not displayed. ONRS T, but Figure 2 and Figure 3 During period P1, due to the adjusted modulation signal SIG RM The off time for each cycle is approximately 1 ns (shorter than the reference clock signal SIG). RFCK During the two cycles, the second counter 136 will not generate a SIG signal. ONRST To reset the first counter 134. Therefore, the first counter 134 will start from the regulated modulation signal SIG. R The count proceeds from the first cycle of M to the eighth cycle, then a set signal SIG is generated. SET The SR latch 138 is triggered to pull up the demodulation output signal SIG. DOUT .

[0072] In some embodiments, the set signal SIG generated by the first counter 134 SET It can be controlled by referring to the most significant bit of its counter register. Similarly, the reset signal SIG generated by the second counter 136... RST and the on reset signal SIG ONRST It can also be controlled by referring to certain bits of its counter register.

[0073] Figure 5 The digital isolator 200 according to a second embodiment of the present invention is shown. The difference between digital isolator 200 and digital isolator 100 is that the output terminals of the first counter 234 and the second counter 236 in the demodulation circuit 230 can be coupled to the selected position in its counter register.

[0074] like Figure 5 As shown, the first counter 234 includes a 4-bit counter register 2342 for recording the current count value. The current count value can be represented by bits A[3] to A[0], and the output of the first counter 234 is coupled to the most significant bit A[3] of the counter register 2342, which is used to output a set signal SIG when the count value reaches 8. SET However, the invention is not limited thereto. In other embodiments, the size of the counter register 2342 can be determined based on the conduction de-glitch threshold number used by the first counter 234.

[0075] In addition, such as Figure 5 As shown, the second counter 236 includes a 4-bit counter register 2362 for recording the current count value. The current count value can be represented by bits B[3] to B[0], and the first output of the second counter 236 is coupled to the most significant bit B[3] of the counter register 2362, which is used to output a reset signal SIG when the count value reaches 8. RST .

[0076] Furthermore, in the second embodiment, the demodulation circuit 230 includes an OR gate 239. The OR gate 239, combined with the second counter 236, can generate a turn-on reset signal SIG for resetting the first counter 234. ONRST OR gate 239 has multiple inputs (e.g., 3 inputs) coupled to multiple most significant bits (e.g., bit B[3] to bit B[1]) of counter register 2362. In this case, as long as the modulated signal SIG is regulated... RM The logic level is held low for longer than the reference clock signal SIG. RFCK After two cycles, the OR gate 239 will output a logic high-level on / off reset signal SIG. ONRST The first counter 234 is reset. However, the invention is not limited thereto. In other embodiments, the size of the counter register 2362 can be adjusted according to the number of turn-off de-glitch thresholds used by the second counter 236, and the bits coupled to the OR gate 239 can be selected according to the maximum allowable turn-off time measured by the second counter 236.

[0077] Figure 6 This illustrates a digital isolator 300 according to a third embodiment of the present invention. The difference between digital isolator 300 and digital isolator 100 is that the delay circuit 3323 of the waveform conditioner 332 in the demodulation circuit 330 uses a resistor R332 and a capacitor C332 instead of the inverter INV in the delay circuit 1323. For example... Figure 6 As shown, resistor R332 includes a first terminal coupled to the input of delay circuit 3323 and a second terminal coupled to the output of delay circuit 3323. Capacitor C332 includes a first terminal coupled to the second terminal of resistor R332 and a second terminal coupled to ground node GND.

[0078] In this embodiment, the delay time provided by the delay circuit 3323 can be set by adjusting the resistance value of resistor R332 and / or the capacitance value of capacitor C332.

[0079] Figure 7The digital isolator 400 according to a fourth embodiment of the present invention is shown. In the fourth embodiment, the digital isolator 400 replaces the waveform conditioner 132 in the digital isolator 100 with a waveform conditioner 432, which includes two hysteresis comparators 4321 and 4322 and an SR latch 4323.

[0080] like Figure 7 As shown, the hysteresis comparator 4321 includes: a non-inverting input for receiving the isolation modulation signal SIG. MB1 One inverting input is used to receive the isolated modulation signal SIG. MB2 The hysteresis comparator 4322 includes: a non-inverting input for receiving the isolation modulation signal SIG. MB2 One inverting input is used to receive the isolated modulation signal SIG. MB1 The SR latch 4323 includes: a set terminal coupled to the output of the hysteresis comparator 4322; a reset terminal coupled to the output of the hysteresis comparator 4321; and an output terminal for outputting the regulated modulation signal SIG. RM .

[0081] Figure 8 The digital isolator 500 according to the fifth embodiment of the present invention is shown. The difference between digital isolator 500 and digital isolator 200 lies in the demodulation circuit 530. In the demodulation circuit 530, the first counter 534 includes an N-bit counter register 5342 for recording the current count value, and the demodulation circuit 530 also includes a logic circuit 539A coupled to bits A[N] and A[0] of the counter register 5342 and the set terminal of the SR latch 138, for outputting a set signal SIG according to the current count value of the counter register 5342 and the conduction de-glitch threshold number. SET Where N is a positive integer. In some embodiments, logic circuit 539A allows the user to set the conduction de-glitch threshold number (i.e., the first counter 534 generates a set signal SIG). SET The modulated signal SIG that needs to be counted before adjustment RM The counter register 5342 can be configured to output a set signal SIG when the current count value reaches a predetermined de-glitch threshold number. SET In other words, the conduction de-glitch threshold number is programmable. For example, if the user sets the conduction de-glitch threshold number to 8, the logic circuit 539A will generate a logic high set signal SIG when bit A[3] becomes logic high (i.e., the value becomes "1"). SET .

[0082] Similarly, the second counter 536 may include an M-bit counter register 5362 for recording the current count value, and the demodulation circuit 530 may also include a logic circuit 539B, coupled to bits B[M] and B[0] of the counter register 5362 and the reset terminal of the SR latch 138, for outputting a reset signal SIG based on the current count value of the counter register 5362 and the de-glitch threshold number. RST Where M is a positive integer. In some embodiments, logic circuit 539B allows the user to set the de-glitch threshold number (i.e., the second counter 536 generates a reset signal SIG). RST The reference clock signal SIG that needs to be counted beforehand RFCK The counter register 5362 can be configured to output a reset signal SIG when the current count value reaches a predetermined shutdown de-glitch threshold number (the number of cycles). RST In other words, the descrambling threshold number can be programmed.

[0083] In addition, the demodulation circuit 530 may also include a logic circuit 539C, coupled to bit B[M] and bit B[0] of the counter register 5362 and the reset terminal of the first counter 534, for outputting a turn-on reset signal SIG based on the current count value of the counter register 5362 and the maximum allowable off time. ONRST In some embodiments, logic circuit 539C allows the user to set the maximum allowable shutdown time. For example, logic circuit 539C may allow the user to set a second counter 536 to generate a turn-on reset signal SIG. ONRST The reference clock signal SIG that needs to be counted beforehand RFCK The number of cycles can be configured to output a turn-on reset signal SIG when the current count value of the counter register 5362 reaches a user-defined predetermined value. ONRST In other words, the maximum allowable shutdown time is programmable. Furthermore, the demodulation circuit 530 employs an RC-based delay circuit 3323, including a resistor R332 and a capacitor C332. However, the invention is not limited to this. In other embodiments, other types of delay circuits may be used. For example, in some embodiments, a delay line-based delay circuit (e.g.) may be used. Figure 1 and Figure 5 The delay circuit 1323 replaces the delay circuit 3323.

[0084] In summary, the digital isolator and demodulation circuit provided by the embodiments of the present application adopt two counters to control the on and off time of the demodulation output signal. By using the time measurement capability of the counters, the demodulation circuit can ignore the noise caused by different types of common mode transients, thereby reducing the glitches in the demodulation output signal, and enabling the digital isolator to achieve high CMTI. In addition, since the on glitch threshold number, the off glitch threshold number and the maximum allowed off time can be programmed by the counters, this also provides great flexibility for circuit design.

[0085] While the application and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application as defined by the appended claims. For example, many of the steps recited herein can be carried out in a different order or omitted or supplemented with other steps or combinations thereof.

[0086] Furthermore, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized according to the present application. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A demodulation circuit, characterized by comprising: The demodulation circuit comprises: a waveform regulator configured to generate a regulated modulation signal according to a pair of differential isolated modulation signals, wherein the differential isolated modulation signals are generated by modulating an input data signal with a carrier clock signal; a first counter comprising: a clock input configured to receive the regulated modulation signal; a reset input; and an output configured to output a set signal; a second counter comprising: a clock input configured to receive a reference clock signal; a reset input configured to receive the regulated modulation signal; and a first output configured to output a reset signal; and a first set-reset (SR) latch comprising: a set input coupled to the output of the first counter; a reset input coupled to the first output of the second counter; and an output configured to output a demodulated output signal; wherein the first counter is configured to count periods of the regulated modulation signal to generate the set signal and trigger the first SR latch to pull up the demodulated output signal, and the second counter is configured to count periods of the reference clock signal to generate the reset signal and trigger the first SR latch to pull down the demodulated output signal.

2. The demodulation circuit of claim 1, wherein, The second counter further comprises a second output coupled to the reset input of the first counter, and the second counter is further configured to output an enable reset signal through the second output when the regulated modulation signal remains at a logical low level for a duration that exceeds a first predetermined number of periods of the reference clock signal.

3. The demodulation circuit of claim 2, wherein, The first counter is configured to generate the set signal when a second predetermined number of periods of the regulated modulation signal are counted and the enable reset signal is not received.

4. The demodulation circuit of claim 3, wherein, The second counter is configured to generate the reset signal when the regulated modulation signal remains at a logical low level and a third predetermined number of periods of the reference clock signal are counted.

5. The demodulation circuit of claim 4, wherein, The first, second, and third predetermined numbers of periods are programmable.

6. The demodulation circuit of claim 1, wherein, The first counter further comprises a counter register, and the output of the first counter is coupled to a most significant bit of the counter register to output the set signal.

7. The demodulation circuit of claim 1, wherein, The second counter further comprises a counter register, and the first output of the second counter is coupled to a most significant bit of the counter register to output the reset signal.

8. The demodulation circuit of claim 7, wherein, The demodulation circuit further comprises an OR gate comprising: a plurality of inputs coupled to a plurality of most significant bits of the counter register; and an output coupled to the reset input of the first counter and configured to output the enable reset signal.

9. The demodulation circuit of claim 1, wherein, The frequency of the reference clock signal is equal to the frequency of the carrier clock signal.

10. The demodulation circuit of claim 1, wherein, The waveform regulator is configured to regulate a duty cycle of the regulated modulation signal to be substantially equal to 50% when the differential isolated modulation signals periodically jump.

11. The demodulation circuit of claim 1, wherein, The waveform regulator comprises: a hysteresis comparator comprising a non-inverting input configured to receive a first isolated modulated signal of the pair of differential isolated modulated signals, an inverting input configured to receive a second isolated modulated signal of the pair of differential isolated modulated signals, and an output; a D flip-flop comprising a data terminal configured to receive a supply voltage, a clock terminal coupled to the output of the hysteresis comparator, a reset terminal, and an output terminal configured to output the adjusted modulated signal; and a delay circuit comprising an input terminal coupled to the output terminal of the D flip-flop, and an output terminal coupled to the reset terminal of the D flip-flop.

12. The demodulation circuit of claim 11, wherein, The delay circuit comprises a plurality of cascaded inverters.

13. The demodulation circuit of claim 11, wherein, The delay circuit comprises: a resistor comprising a first terminal coupled to the input terminal of the delay circuit, a second terminal coupled to the output terminal of the delay circuit, and a capacitor comprising a first terminal coupled to the second terminal of the resistor, and a second terminal coupled to a ground node.

14. The demodulation circuit of claim 1, wherein, The waveform adjuster comprises: a first hysteresis comparator comprising a non-inverting input configured to receive a first isolated modulated signal of the pair of differential isolated modulated signals, an inverting input configured to receive a second isolated modulated signal of the pair of differential isolated modulated signals, and an output; a second hysteresis comparator comprising a non-inverting input configured to receive the second isolated modulated signal, an inverting input configured to receive the first isolated modulated signal, and an output; and a second SR latch comprising a set terminal coupled to the output terminal of the second hysteresis comparator, a reset terminal coupled to the output terminal of the first hysteresis comparator, and an output terminal configured to output the adjusted modulated signal.

15. A digital isolator comprising: comprises: the demodulation circuit of claim 1; and an isolation circuit configured to receive a pair of differential modulated input signals generated by modulating an input data signal with a carrier clock signal, and output the pair of differential isolated modulated signals.

16. The digital isolator of claim 15, wherein, The second counter further comprises a second output terminal coupled to the reset terminal of the first counter, and the second counter is further configured to output, through the second output terminal, an enable reset signal when a duration for which the adjusted modulated signal remains at a logical low level exceeds a duration of a first predetermined number of cycles of a reference clock signal.

17. The digital isolator of claim 15, wherein, The isolation circuit comprises: a first capacitor comprising a first terminal configured to receive a first modulated input signal of the pair of differential modulated input signals, and a second terminal; a second capacitor comprising a first terminal configured to receive a second modulated input signal of the pair of differential modulated input signals, and a second terminal; a third capacitor comprising a first terminal coupled to the second terminal of the first capacitor, and a second terminal configured to output a first isolated modulated signal of the pair of differential isolated modulated signals; and a fourth capacitor comprising a first terminal coupled to the second terminal of the second capacitor, and a second terminal configured to output a second isolated modulated signal of the pair of differential isolated modulated signals. a fourth capacitor comprising: a first end coupled to a second end of the second capacitor; a second end configured to output a second isolated modulated signal of the differential isolated modulated signals; a first resistor comprising: a first end coupled to a second end of the third capacitor; a second end; and a second resistor comprising: a first end coupled to a second end of the fourth capacitor; a second end coupled to the second end of the first resistor.

18. The digital isolator of claim 17, wherein, the isolation circuit further comprises: a third resistor comprising: a first end configured to receive the first modulated input signal; a second end coupled to the first end of the first capacitor; and a fourth resistor comprising: a first end configured to receive the second modulated input signal; a second end coupled to the first end of the second capacitor.

19. The digital isolator of claim 15, wherein, further comprising a modulation circuit configured to generate the differential modulated input signals by modulating the input data signal with the carrier clock signal.

20. The digital isolator of claim 19, wherein, the modulation circuit comprises: a NAND gate comprising: a first input configured to receive the carrier clock signal; a second input configured to receive the input data signal; and an output configured to output a first modulated input signal of the differential modulated input signals; and an inverter comprising: an input coupled to the output of the NAND gate; and an output configured to output a second modulated input signal of the differential modulated input signals.

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