Electroencephalogram acquisition system

Abstract

The invention provides an electroencephalogram collecting system which comprises a plurality of electroencephalogram electrodes connected to the brain of a living body to detect electroencephalogram signals. The acquisition module is correspondingly connected with the electroencephalogram electrodes so as to acquire electroencephalogram signals and preprocess the electroencephalogram signals; the acquisition module comprises at least one electroencephalogram acquisition sub-module, and the electroencephalogram acquisition sub-module is integrated with an amplifier, a multiplexer and an analog-to-digital converter; the main control module is used for carrying out secondary processing on the electroencephalogram signals and comprises a logic control unit and a processing unit; the logic control unit is connected with the acquisition module; and the processing unit is connected with a management terminal so as to configure parameters of the logic control unit and send the electroencephalogram signals subjected to secondary processing to the management terminal. According to the electroencephalogram acquisition system, the acquisition module and the main control module are integrated, so that electroencephalogram acquisition can be realized without a sickbed, and the portability and the flexibility of the electroencephalogram acquisition system are improved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of electroencephalogram acquisition, and in particular to an electroencephalogram acquisition system. BACKGROUND

[0002] Electroencephalogram is a method of recording brain activity by using electrophysiological indicators. When the brain is active, a large number of neuron synaptic potentials occur synchronously and form after summation. It records the change of the electric wave when the brain is active, and is the overall reflection of the electrophysiological activity of brain nerve cells on the cerebral cortex or scalp surface. In-depth study of the characteristics of electroencephalogram will promote the exploration and research process of human brain and enhance the diagnosis ability of diseases.

[0003] The implementation modes of brain-computer interface include non-invasive and invasive modes. The non-invasive technology is a technology for capturing brain signals without surgery, and some wearable miniaturized devices exist in the related art. However, the signal strength obtained by the non-invasive technology is weak, and the signal-to-noise ratio is low, which greatly limits its performance in high-precision tasks. Compared with the non-invasive technology, the invasive technology has higher spatial resolution and greater bandwidth, and can more accurately observe the excitation of single neurons and the encoding mode of neuron clusters. However, the implementation of the invasive technology in the related art often depends on large equipment, which cannot be moved once connected, and has poor flexibility. SUMMARY

[0004] The application provides an electroencephalogram acquisition system to solve the problem of poor flexibility caused by the large size of the electroencephalogram device in the related art.

[0005] To solve the above problems, the technical scheme provided by the application is as follows:

[0006] The application provides an electroencephalogram acquisition system, which comprises: a plurality of electroencephalogram electrodes connected to the brain to detect electroencephalogram signals; an acquisition module connected to the electroencephalogram electrodes to acquire and preprocess the electroencephalogram signals, the acquisition module comprising at least one electroencephalogram acquisition sub-module, the electroencephalogram acquisition sub-module integrating an amplifier, a multiplexer and an analog-to-digital converter; and a master control module for secondary processing of the electroencephalogram signals, the master control module comprising a logic control unit and a processing unit, the logic control unit being connected to the acquisition module, and the processing unit being connected to a management terminal to configure parameters of the logic control unit and send the secondary-processed electroencephalogram signals to the management terminal.

[0007] Optionally, the acquisition module and the master module are connected through a plurality of differential signal pairs, the differential signal pairs include a control signal differential pair and a data interaction differential pair; two signal lines of each differential signal pair are connected through a matching resistor, the matching resistor and the plurality of differential signal pairs form an impedance matching network; wherein the master module is provided with 1 to 8 differential signal input interfaces.

[0008] Optionally, the acquisition module includes at least two EEG acquisition sub-modules connected in parallel through a connection chip, and each EEG acquisition sub-module is integrated in a single packaging structure.

[0009] Optionally, the connection chip includes: two rows of symmetrically distributed pin arrays, the number of pins in the pin array on one side of the connection chip is consistent with the number of channels of a single EEG acquisition sub-module.

[0010] Optionally, each EEG acquisition sub-module includes: a 64-channel EEG signal input end, the EEG signal input end of each channel is independently connected to an electrode contact on the EEG electrode; and a differential signal output end, each differential signal output end is connected to an independent differential signal input interface of the master module.

[0011] Optionally, the acquisition module further includes a power supply module, the power supply module includes: a rectifier chip including a rectifier input end, a rectifier ground end, a rectifier enable end and a rectifier output end, the rectifier output end is configured to output a direct current voltage; a first inductor, one end of the first inductor is connected to the rectifier voltage, the other end is connected to the rectifier input end; a second inductor, one end of the second inductor is connected to a digital circuit ground, the other end is connected to an analog circuit ground and the rectifier ground end; a first capacitor, a first plate of the first capacitor is connected to the rectifier input end, a second plate of the first capacitor is connected to the analog circuit ground; a first resistor, one end of the first resistor is connected to the first plate of the first capacitor, the other end is connected to the rectifier enable end; a second capacitor, a first plate of the second capacitor is connected to the rectifier output end, a second plate of the second capacitor is connected to the analog circuit ground.

[0012] Optionally, the logic control unit includes a programmable gate array chip, the processing unit includes an ARM processor, the logic control unit and the processing unit are connected through an extensible interface bus, and the processing unit is in communication connection with the management terminal through a wireless communication chip.

[0013] Optionally, the electroencephalogram acquisition system further comprises a power management module connected to the power module, the power management module comprising: a voltage regulating circuit, an input of the voltage regulating circuit being connected to the DC power supply, an output of the voltage regulating circuit generating a plurality of voltage levels and being connected to the main control module and the acquisition module; and a protection circuit connected in series between the power module and the voltage regulating circuit to suppress abnormal current surges.

[0014] Optionally, the voltage regulating circuit comprises: a voltage boosting unit connected to the power module to boost the voltage output by the power module; and a DC conversion unit connected to the voltage boosting unit to convert the boosted voltage into a plurality of stepped voltage levels.

[0015] Optionally, the protection circuit comprises: a current sampling unit connected to the power module to monitor the output current of the power module; and an overcurrent protection unit connected to the current sampling unit to cut off the enable signal of the voltage regulating circuit when the current sampling unit detects an overcurrent.

[0016] Optionally, the power management module further comprises: a switch circuit provided in the series circuit between the protection circuit and the voltage regulating circuit, the switch circuit being further connected to the processing unit to be controlled to cut off or conduct the power supply path of the power module and the voltage regulating circuit.

[0017] Optionally, the power module comprises a DC power supply connected to an external power supply through a charging interface; the power management module further comprises a charging management circuit provided in the series circuit between the charging interface and the protection circuit.

[0018] Optionally, the power module further comprises a power over Ethernet circuit connected to an Ethernet cable; the power over Ethernet circuit comprising: an Ethernet isolation transformer, an input of the Ethernet isolation transformer being connected to the Ethernet cable; a power over Ethernet controller, an input of the power over Ethernet controller being connected to an output of the Ethernet isolation transformer, an output of the power over Ethernet controller being connected to the protection circuit; and an Ethernet data transmitter connected between the Ethernet isolation transformer and the main control module.

[0019] Optionally, the electroencephalogram acquisition system further comprises a storage module, the storage module comprising: a storage medium configured to store data of the electroencephalogram signals; and a level conversion circuit connected between the storage medium and the processing unit.

[0020] Optionally, the EEG acquisition system further includes an isolation and protection module, which includes: a power isolation circuit, a series line between the acquisition module and the voltage regulation circuit; a communication isolation circuit, a series line between the acquisition module and the logic control unit; and an electrostatic protection circuit, a series line between the EEG electrodes and the EEG acquisition submodule, a series line between the charging interface and the charging management circuit, a series line between the Ethernet data transmitter and the Ethernet isolation transformer, and a series line between the storage medium and the level conversion circuit.

[0021] Optionally, the electrostatic discharge protection circuit includes: a plurality of electrostatic discharge diodes, each diode corresponding to a signal input terminal; a common ground terminal, the cathodes of all diodes being connected to the common ground terminal to discharge electrostatic charge; and a signal input terminal connected to the signal amplification unit.

[0022] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0023] This application provides an electroencephalogram (EEG) acquisition system, comprising several EEG electrodes connected to the brain of an organism to detect EEG signals; an acquisition module connected corresponding to the EEG electrodes to acquire and preprocess the EEG signals; the acquisition module includes at least one EEG acquisition submodule, which integrates an amplifier, a multiplexer, and an analog-to-digital converter; and a main control module for secondary processing of the EEG signals, comprising a logic control unit and a processing unit, wherein the logic control unit is connected to the acquisition module, and the processing unit is connected to a management terminal to configure the parameters of the logic control unit and send the secondary-processed EEG signals to the management terminal. This EEG acquisition system, by implementing an integrated acquisition module and main control module, enables EEG acquisition to be performed bedside, thereby improving the portability and flexibility of the EEG acquisition system. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Appendix Figure 1 This is a schematic diagram of the overall modular structure of the EEG acquisition system in some embodiments of this application;

[0026] Appendix Figure 2 This is a schematic diagram of the specific module structure of the EEG acquisition system in some embodiments of this application;

[0027] Appendix Figure 3 This is a schematic diagram of the connection between the acquisition module and the main control module in some embodiments of this application;

[0028] Appendix Figure 4 This is a schematic diagram of the connection chip of the acquisition module in some embodiments of this application;

[0029] Appendix Figure 5 This is a schematic diagram of the circuit principle of the EEG acquisition submodule in some embodiments of this application;

[0030] Appendix Figure 6 This is a schematic diagram of the circuit principle of the channel selection unit of the EEG acquisition submodule in some embodiments of this application;

[0031] Appendix Figure 7 This is a timing diagram of the double data rate synchronous dynamic random access memory in some embodiments of this application;

[0032] Appendix Figure 8 This is a schematic diagram of the circuit principle of the power supply module of the acquisition module in some embodiments of this application;

[0033] Appendix Figure 9 This is a schematic diagram of the specific control flow of the main control module in some embodiments of this application;

[0034] Appendix Figure 10 This is a schematic diagram of the circuit structure of the power management module in some embodiments of this application;

[0035] Appendix Figure 11 This is a schematic diagram of the charging management circuit in some embodiments of this application;

[0036] Appendix Figure 12 This is a schematic diagram of the circuit structure of the storage module in some embodiments of this application;

[0037] Appendix Figure 13 This is a schematic diagram of the electrostatic discharge protection circuit in some embodiments of this application.

[0038] Explanation of the reference numerals in the figure:

[0039] 1. Electroencephalogram (EEG) acquisition system;

[0040] 100. Electroencephalogram (EEG) electrodes;

[0041] 200. Acquisition module; 210. EEG acquisition submodule; 211. Signal amplification unit; 211a. First gain amplification unit; 211b. Second gain amplification unit; 211c. Amplifier bandwidth selector; 212. Channel selection unit; 213. Analog-to-digital conversion unit;

[0042] 300. Main control module; 310. Logic control unit; 320. Processing unit;

[0043] 400. Power management module; 410. Voltage regulation circuit; 420. Protection circuit; 430. Switching circuit; 440. Charging management circuit;

[0044] 500. Power supply module; 510. DC power supply; 520. Ethernet power supply circuit; 521. Ethernet isolation transformer; 522. Ethernet power supply controller; 523. Ethernet data transmitter;

[0045] 600. Storage module; 610. Storage medium; 620. Level conversion circuit;

[0046] 700. Isolation and protection module; 710. Power isolation circuit; 720. Communication isolation circuit; 730. Electrostatic discharge protection circuit. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] As used in this article, the singular forms “a,” “one,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0049] It will also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the said feature or component, but do not exclude the presence or addition of one or more other features or components.

[0050] In invasive EEG acquisition systems, deep electrodes are typically stereotactically implanted into deep brain structures, such as the hippocampus and amygdala. They are then connected to a digital EEG head unit via lead wires to amplify and digitize the weak bioelectrical signals from the human brain, record the electrical activity in these areas, and then store and analyze the data.

[0051] In related technologies, digital electroencephalogram (EEG) machines are typically designed as desktop or trolley-type devices, which leads to several major drawbacks or problems. First, due to their large size, these devices are not easily portable, especially when EEG testing needs to be performed in multiple locations. For example, this design is particularly cumbersome and impractical for situations requiring relocation between different wards or even different medical facilities. Second, once the electrodes are connected via leads, the device is essentially fixed to the bedside and cannot be moved. This limits the flexibility of device use and can cause unnecessary inconvenience or decreased comfort for patients requiring long-term monitoring. Furthermore, this fixed nature may hinder the rapid response of medical personnel to patients in emergency situations.

[0052] Reference Figure 1 and Figure 2 As shown, this application provides an EEG acquisition system 1, including: a plurality of EEG electrodes 100, an acquisition module 200 and a main control module 300.

[0053] Among them, several EEG electrodes 100 are connected to the brain of the organism to detect EEG signals.

[0054] Optionally, in some embodiments of this application, the EEG electrode 100 may be a scalp electrode, an electrocorticography (ECoG) electrode, and / or a stereoelectroencephalography (SEEG) electrode, wherein the scalp electrode performs non-invasive recording of brain electrical activity; the ECoG electrode is placed on the surface of the cerebral cortex to record cortical electrical activity; and the SEEG electrode is inserted into a specific brain region to capture electrical activity of deep structures.

[0055] The acquisition module 200 is connected to the EEG electrode 100.

[0056] Optionally, the acquisition module 200 and the EEG electrodes 100 are connected via lead wires to ensure that EEG signals can be transmitted from the electrodes to the acquisition module 200. It should be noted that the acquisition module 200 is also provided with a compatible interface for the EEG electrodes 100 to enable the connection of different types of EEG electrodes 100 in the aforementioned embodiments.

[0057] The acquisition module 200 acquires EEG signals and preprocesses them. Optionally, this preprocessing includes digital processing such as amplification, filtering, and analog-to-digital conversion of weak EEG signals.

[0058] The acquisition module 200 includes at least one EEG acquisition submodule 210, which integrates an amplifier, a multiplexer, and an analog-to-digital converter.

[0059] It should be noted that EEG signals are very weak. Therefore, by setting an amplifier, the μV-level EEG signal can be amplified to the range that the analog-to-digital converter (ADC) can quantize. Then, the amplified analog signal is converted into a digital signal with a certain precision by the ADC. In this process, the influence of high-frequency noise on sampling can also be eliminated by using a low-pass filter. In addition, multiplexers can be used to achieve multi-channel synchronous acquisition while ensuring the time consistency of EEG signals from multiple points.

[0060] Optionally, in some more specific examples, the acquisition module 200 may also include a communication module to transmit digitized EEG signals to the main control module 300.

[0061] The main control module 300 performs secondary processing on the EEG signal. The main control module 300 includes a logic control unit 310 and a processing unit 320. The logic control unit 310 is connected to the acquisition module 200, and the processing unit 320 is connected to the management terminal to configure the parameters of the logic control unit 310 and send the secondary processed EEG signal to the management terminal.

[0062] Optionally, secondary processing includes serial-to-parallel conversion of data, preliminary data filtering, construction of data frames, data caching, and data transmission conversion.

[0063] It should be noted that the management terminal can send corresponding operation commands to the main control module 300 to control the main control module 300 to collect EEG signals. After the management terminal receives the EEG signal data after secondary processing, it will calculate the waveform data based on the original channel data and lead configuration. The waveform data will be filtered by a filter and then subjected to wavelet transform and Fourier transform to remove noise. The final data will be drawn in the form of spectrum and heat map for visualization.

[0064] Optionally, combined Figure 3As shown, in some embodiments of this application, the acquisition module 200 and the main control module 300 are connected via multiple differential signal pairs, including control signal differential pairs and data interaction differential pairs. Specifically, the control signal differential pairs include chip select signal differential pairs (CS+ / CS-) and clock signal differential pairs (SCLK+ / SCLK-). The chip select signal selects the acquisition module 200 currently communicating, enabling channel expansion and time-division multiplexing. Simultaneously, the use of differential transmission reduces signal latency. The data interaction differential pairs include master-output-slave-in signal differential pairs (MOSI+ / MOSI-) and master-input-slave-output signal differential pairs (MISO+ / MISO-). Independent signal lines are used for command issuance (MOSI) and data return (MISO), avoiding bus conflicts and ensuring real-time data transmission. Furthermore, using differential signal pairs for data transmission helps to offset common-mode interference introduced by long cables, thereby improving the signal-to-noise ratio. Differential signal transmission can be achieved using twisted-pair cables, which can effectively reduce signal interference and noise, thereby ensuring reliable data transmission.

[0065] Optionally, in some embodiments, the two signal lines of each differential signal pair are connected by a matching resistor, which forms an impedance matching network with the multiple differential signal pairs. In some specific examples, the resistance of the matching resistor can be 100Ω, which effectively reduces signal reflection.

[0066] Optionally, combine again Figure 3 As shown, in some embodiments of this application, the acquisition module 200 includes at least two parallel EEG acquisition sub-modules 210, each EEG acquisition sub-module 210 being integrated into a single package structure.

[0067] Optionally, combined Figure 4 As shown, in some embodiments of this application, the acquisition module 200 further includes a connection chip configured to connect the EEG acquisition submodules 210 in parallel. The connection chip includes two symmetrically distributed pin arrays, and the number of pins in the pin array on one side of the connection chip is consistent with the number of channels of a single EEG acquisition submodule 210.

[0068] Optionally, combined Figure 2 and Figure 5 As shown, each EEG acquisition submodule 210 includes 64 channels of EEG signal input terminals and differential signal output terminals. The EEG signal input terminal of each channel is independently connected to an electrode contact on the EEG electrode 100, and each differential signal output terminal is correspondingly connected to the independent differential signal input interface of the main control module 300.

[0069] It should be noted that in related technologies, some sampling chips have a small number of channels. To increase the number of acquisition channels, multiple sampling chips are often used to form a daisy-chain topology. Although this expands the number of channels, the sampling rate of a single channel is reduced because all channels share the bandwidth of the same data transmission path. This may affect the ability of the acquisition module 200 to capture rapid changes in electrical activity. In addition, the complex circuit design of the daisy-chain topology also increases the design and manufacturing difficulty. In some embodiments of this application, by using two 64-channel EEG acquisition submodules 210 connected in parallel, the functions of a 128-channel high-sampling, high-fidelity, and high-precision signal amplification circuit, a high-speed, low-noise, and low-power analog-to-digital conversion circuit, and a data communication circuit are realized. While ensuring the sampling rate, the size of the acquisition module 200 is effectively reduced.

[0070] Optionally, in some embodiments of this application, the main control module 300 is provided with multiple differential signal input interfaces, each of which is connected to a differential signal output terminal of the acquisition module. In some specific examples, the main control module 300 may have 1-8 connection ports for connecting to the acquisition module 200, thereby enabling up to 1024 acquisition channels to operate in parallel in real time.

[0071] Optionally, combined Figure 5 As shown, in some embodiments of this application, the EEG acquisition submodule 210 includes a signal amplification unit 211, a channel selection unit 212, and an analog-to-digital conversion unit 213.

[0072] Specifically, the signal amplification unit 211 is an array of 64 amplifiers with unipolar inputs (0, 1, ...) and a common shared reference line (ref_elec). Within this array of 64 amplifiers, the signal amplification unit 211 is divided into two categories, each connected to a different channel selection unit 212: a first gain amplification unit and a second gain amplification unit. Both the first and second gain amplification units contain a two-stage gain architecture; the first-stage gain is fixed at 96x, and the second-stage gain is configured to be 2x or 1x. Furthermore, the signal amplification unit 211 also includes an amplifier bandwidth selector 211c for dynamically adjusting the amplifier's frequency response range. By configuring register parameters, the high-pass / low-pass cutoff frequencies of the amplifier can be selected to adapt to different bioelectrical signal requirements.

[0073] Optionally, combined Figure 6As shown, in some embodiments of this application, the channel selection unit 212 may employ a dual data rate (DDR) multiplexer. This multiplexer includes two D flip-flops, two NOT gates, an AND gate, and a selector. This multiplexer can combine two serial data signals (MISO A and MISO B) into a single dual data rate (DDR) MISO signal. Specifically, the AND gate generates the multiplexer's gating control signal based on the clock (SCLK) and chip select (CS) signals, while the NOT gate inverts the output signal of one of the D flip-flops, thereby generating complementary control logic. This allows the data to be synchronized with the rising or falling edge of SCLK, enabling the selector to alternately select data from MISO A and MISO B to combine the two serial data streams.

[0074] Optionally, in some embodiments of this application, the analog-to-digital conversion unit 213 may be a 16-bit analog-to-digital conversion chip (ADC).

[0075] Optionally, combined Figure 6 As shown, both EEG acquisition submodules 210 include module A and module B. Module A consists of amplifier channels 0-31, and module B consists of amplifier channels 32-63. Modules A and B receive the same commands from the MOSI rows. If a command is sent to switch amplifier channel X, module A switches amplifier channel X, and module B simultaneously switches amplifier channel X+32. The 16-bit results from the two ADCs (transmitted consecutively on MISO A and MISO B rows) are combined into a single MISO signal via a dual data rate (DDR) multiplexer.

[0076] It should be noted that in the two EEG acquisition sub-modules 210, the basic structure of the two EEG acquisition sub-modules 210 is the same. When one EEG acquisition sub-module 210 is used as the core of functional expansion, the other EEG acquisition sub-module 210 is only used for the expansion of the signal amplification unit.

[0077] Optionally, the acquisition module 200 also includes an auxiliary signal input port, a temperature sensing circuit, and a power monitoring circuit. The auxiliary signal input port, temperature sensing circuit, and power monitoring circuit are only connected to the EEG acquisition submodule 210, which serves as the core of functional expansion. When using auxiliary input or sensors, the other EEG acquisition submodule 210 generates invalid data due to the lack of actual signal input, and the system needs to actively discard it to avoid erroneous processing.

[0078] Specifically, the auxiliary signal input port includes three independent input ports auxin1 to auxin3. A temperature sensor circuit monitors the chip's temperature, and a power monitoring circuit monitors the VDD voltage. The auxiliary signal input port, temperature sensor circuit, and power monitoring circuit are all directly connected to the multiplexer of the EEG acquisition submodule 210, which serves as the core of the functional expansion. The temperature sensor circuit monitors the chip's temperature. While the three independent input ports auxin1 to auxin3 do not pass through an amplifier array, their bandwidth still needs to be limited to avoid high-frequency noise interfering with the ADC conversion. Therefore, the three independent input ports auxin1 to auxin3 can also be switched to connect to an amplifier bandwidth selector via a switch.

[0079] Based on this, the input terminal of the channel selection unit 212 is connected to the second gain amplification unit, and the reference voltage input terminal of the channel selection unit 212 is connected to the half-voltage divider point of the supply voltage. Since bioelectrical signals typically exist in differential form, but a fixed common-mode reference level is required in unipolar input mode, connecting the multiplexer to 1 / 2VDD provides a unified common-mode reference for all input channels (such as in0-in31, auxin1-3), ensuring that the signal remains within the linear range during amplification, gating, and ADC conversion, thus avoiding saturation distortion.

[0080] The power supply voltage is derived from the reference voltage pin of the acquisition module 200. The reference voltage pin is connected to the power supply voltage and is also grounded through a 100nF filter capacitor. By setting this capacitor, it forms a low-pass filter with the reference voltage node, which can filter out voltage fluctuations (such as power supply transients and load changes) and maintain the DC accuracy of the reference voltage.

[0081] Optionally, in some embodiments of this application, the acquisition module 200 further includes a communication control module, which includes a protocol parsing unit, a data merging unit, and a timing synchronization unit.

[0082] Specifically, the protocol parsing unit is configured to control the on-chip registers to enable or disable a specified channel, set filter parameters, or start electrode impedance detection according to external control instructions (SPI); the data merging unit is configured to merge the odd and even channel data streams output by the analog-to-digital conversion unit into a single data stream through the channel selection unit and transmit it through the low-voltage differential signal interface; the timing synchronization unit is configured to trigger the synchronous sampling of all signal acquisition modules according to the falling edge of the chip select signal.

[0083] Optionally, combined Figure 7 The diagram shown is a timing control diagram of external control instructions (SPI). It should be noted that this DDR technology is a non-standard SPI communication mode, which requires a programmable logic controller to assist in its implementation.

[0084] The communication control module has four SPI interfaces, including: active-low chip select (CS), serial data clock with base value zero (SCLK), master output / slave input data line (MOSI), and master input / slave output data line (MISO).

[0085] During the idle waiting phase, the chip select signal CS remains high to disable communication, SCLK remains low, MOSI is at any level, and MISO is in a high impedance state (HiZ), thereby ensuring that the signal acquisition module is inactive and avoiding erroneous operation.

[0086] When the CS signal is at its falling edge, the communication cycle begins. The communication control module receives the SLCK signal, and the MOSI data is updated on the falling edge of the SLCK signal. 16-bit command words are sent sequentially in high-order priority. The signal acquisition module samples the MOSI data on the rising edge of the SLCK signal, completing command reception. Simultaneously, the ADC triggers analog signal sampling on the selected channel on the falling edge of the CS signal. It is important to note that after each 16-bit command transmission, the CS signal must be pulled high to reset for the next transmission.

[0087] Optionally, in some embodiments of this application, the acquisition module 200 may further include an electronic supply module, combined with... Figure 8 As shown, the power supply module includes: rectifier chip U6, first inductor L5, second inductor L6, first capacitor C18, first resistor R6, and second capacitor C22.

[0088] Specifically, the rectifier chip U6 includes a rectifier input terminal IN, a rectifier ground terminal GND, a rectifier enable terminal EN, and a rectifier output terminal OUT. The rectifier output terminal OUT is configured to output a DC voltage. One end of the first inductor L5 is connected to the rectified voltage, and the other end is connected to the rectifier input terminal IN, thereby suppressing input voltage noise. One end of the second inductor L6 is connected to the digital circuit ground, and the other end is connected to the analog circuit ground and the rectifier ground terminal GND, thereby isolating common-mode interference between the digital ground and the analog ground. The first plate of the first capacitor C18 is connected to the rectifier input terminal IN, and the second plate of the first capacitor C18 is connected to the analog circuit ground, filtering out high-frequency ripple at the input terminal and absorbing voltage spikes. One end of the first resistor R6 is connected to the first plate of the first capacitor C18, and the other end is connected to the rectifier enable terminal EN, thereby limiting the current in the enable signal path and providing level matching. The first plate of the second capacitor C22 is connected to the rectifier output terminal OUT, and the second plate of the second capacitor C22 is connected to the analog circuit ground, thereby stabilizing the output voltage VCCA and suppressing output ripple.

[0089] Optionally, in some embodiments of this application, combined with Figure 2As shown, the main control module 300 executes corresponding actions based on instructions sent from the management terminal, and then sends the collected data results to the management terminal. Optionally, the main control module 300 can be a System on Chip (SoC), the logic control unit 310 includes a Field-Programmable Gate Array (FPGA) chip, and the processing unit 320 includes an ARM processor. The logic control unit 310 and the processing unit 320 are connected and interact via an Advanced eXtensible Interface (AXI) bus, and the processing unit 320 communicates with the management terminal via a wireless communication chip, which can be a Wi-Fi module.

[0090] The ARM processor includes an embedded subsystem that acts as a connector within the overall EEG acquisition system 1. This subsystem helps the management terminal (such as a client on a PC) control and manage the FPGA chip. It also handles some functions that do not require continuous data transmission. For example, when the main control module 300 is temporarily disconnected from the management terminal, the ARM processor can act as a temporary control core for the entire EEG acquisition system 1, maintaining the normal operation of the EEG electrodes 100, acquisition module 200, and main control module 300. This ensures a more rational and efficient overall functional deployment of the EEG acquisition system 1, better supports its flexible use outside the bed, and greatly enhances the freedom of use of the entire EEG acquisition system 1.

[0091] Optionally, such as Figure 9 As shown, in some embodiments of this application, the embedded subsystem is configured with virtual units corresponding to system control functions, data control functions, and FPGA control functions, which are respectively system control unit, FPGA control unit, and data control unit.

[0092] The system control unit is responsible for controlling the overall operation of the ARM processor and FPGA, and can also control the status of the FPGA control unit and the data control unit.

[0093] The FPGA control unit is used to shield the system control unit from the configuration details of the FPGA and provide an abstract control interface.

[0094] The data control unit is used to shield the system control unit from the details of data transmission and provide an abstract data reading interface.

[0095] Optionally, the ARM processor also includes a wireless communication chip. The wireless communication chip shields the system control unit from network connections and TCP protocol details, providing an abstract communication interface to enable communication and interaction between the processing unit 320 and the management terminal.

[0096] Optionally, the FPGA can control multiple acquisition modules 200 in parallel to achieve high sampling rate high-passband signal acquisition. Specifically, the FPGA connects to the acquisition module 200 via a bidirectional SPI interface, enabling it to send acquisition commands to the acquisition module 200 while simultaneously receiving pre-processed acquisition result data.

[0097] Optionally, in some embodiments, combined with Figure 9 As shown, in order to implement the functions required by the FPGA, a running control state machine, an instruction sending state machine, and a data reading state machine are set up in the FPGA.

[0098] Among them, the operation control state machine is configured as the main state machine of the entire FPGA. The operation control state machine is connected and interacts with the FPGA control unit in the embedded subsystem of the ARM processor through the AXI bus. It not only controls the instruction sending state machine and the data reading state machine, but also is responsible for the overall configuration of the FPGA and manages the overall operation status and performance of the FPGA.

[0099] The instruction sending state machine sends instructions to the acquisition module 200 according to the different task configurations of the running control state machine, such as chip calibration, chip signal verification, impedance testing, and data acquisition. Different tasks will be configured with different instruction sequences.

[0100] The data reading state machine receives the command execution results transmitted back from the acquisition module 200, and simultaneously completes the serial-to-parallel conversion and preliminary data screening of the data.

[0101] Specifically, the FPGA control module communicates with the operation control state machine and the instruction sending state machine via the AXI bus to realize the control flow thread between the processing unit 320 and the logic control unit 310. Furthermore, this is achieved by directly reading and writing registers on the FPGA, allowing the instruction sending state machine to perform corresponding register configurations. The data reading state machine communicates with the data control unit via Direct Memory Access (DMA) data transfer to realize the data flow thread between the logic control unit 310 and the processing unit 320.

[0102] It should be noted that high-frequency, multi-channel continuous sampling will generate a large amount of data. Since the embedded subsystem is a non-real-time system, data buffering is necessary to ensure smooth and stable data transmission and prevent data loss due to insufficient time to reach the ARM or management terminal. The FPGA is responsible for acquiring full-band EEG signals, constructing data frames, and buffering data. Leveraging the FPGA's programmability and efficient parallel processing capabilities, combined with the aforementioned acquisition module 200, the frequency band for EEG signal acquisition can be flexibly selected.

[0103] It is understandable that the technical solution of this application, by implementing the functions of each part of the main control module 300 through integrated chips, greatly improves the portability of the EEG acquisition system 1. At the same time, based on data transmission through a wireless communication chip, the EEG acquisition system 1 of this application can be freed from wired signal transmission methods, and thus, in conjunction with the power supply module 500, can better realize the use of the EEG acquisition system 1 without the hospital bed.

[0104] Optionally, combined Figure 1 and Figure 2 As shown, in some embodiments of this application, the EEG acquisition system 1 further includes a power management module 400 connected to the power module 500. Specifically, in conjunction with Figure 2 As shown, the power management module 400 includes a voltage regulation circuit 410 and a protection circuit 420. The input terminal of the voltage regulation circuit 410 is connected to the power module 500, and the output terminal of the voltage regulation circuit 410 generates multi-level voltages and is connected to the main control module 300 and the acquisition module 200. The protection circuit 420 is connected in series between the power module 500 and the voltage regulation circuit 410 to suppress abnormal current surges.

[0105] Optionally, in some embodiments of this application, combined with Figure 2 As shown, the voltage regulation circuit 410 may include a boost unit and a DC-DC converter. The boost unit is connected to the power module 500 to boost the voltage output by the power module 500, and the DC-DC converter is connected to the boost unit to convert the boosted voltage into a multi-stage voltage.

[0106] Specifically, in combination Figure 10As shown, the voltage regulation circuit 410 can convert the battery voltage into a stable low-voltage output and integrates safety functions such as on / off control and overcurrent protection. Specifically, it eliminates low-frequency ripple and high-frequency interference at the battery input through related circuits, providing a clean power supply for subsequent DC-DC conversion. Simultaneously, it monitors the battery voltage status through voltage divider resistors. Furthermore, this circuit converts the battery voltage to 1.2V, 1.8V, 3.3V, and 5V through high-efficiency DC-DC voltage conversion and multi-stage filtering, supplying power to modules such as FPGAs, ARM processors, and gigabit network cards required for network connectivity. This achieves stable voltage conversion, and by setting up simulated ground isolation, it achieves low ripple, improving circuit reliability.

[0107] Optionally, in some embodiments of this application, the protection circuit 420 includes a current sampling unit and an overcurrent protection unit, wherein the current sampling unit is connected to the power module 500 to monitor the output current of the power module 500, and the overcurrent protection unit is connected to the current sampling unit to cut off the enable signal of the voltage regulation circuit 410 when the current sampling unit detects an overcurrent.

[0108] Optionally, combined Figure 2 As shown in some embodiments of this application, the power management module 400 further includes a switching circuit 430, which is located in series between the protection circuit 420 and the voltage regulation circuit 410. The switching circuit 430 is also connected to the ARM processor to be controlled to cut off or connect the power supply path between the power module 500 and the voltage regulation circuit 410. The switching circuit 430, as the physical switching node between the power module 500 and the voltage regulation circuit 410, can control the flow of battery energy through MOSFETs or relays, thereby achieving seamless switching between charging and discharging states. It can also act as a buffer before the voltage regulation circuit 410, working with the protection circuit 420 to achieve surge protection, cutting off the power path when some modules experience sudden overload.

[0109] Optionally, combined Figure 2 As shown, in some embodiments of this application, the power module 500 includes a DC power supply 510, which can be connected to an external power source through a charging interface to achieve the charging function. The DC power supply 510 can be a lithium battery module, etc. The corresponding power management module 400 also includes a charging management circuit 440, which is a series line between the charging interface and the protection circuit 420.

[0110] Optionally, in some embodiments of this application, combined with Figure 11As shown, the charging management circuit 440 uses the IP5356 protocol power management chip as its core, integrating functions such as input filtering, charging control, status indication, button interaction, and output management. Furthermore, the IP5356 chip also incorporates chip temperature, battery temperature, input voltage control loops, current sampling circuits, and compensation circuits, thereby achieving accurate measurement of battery voltage and current, as well as overcurrent protection and temperature compensation. This chip is well-suited for the charging and discharging management of mobile devices, allowing the EEG acquisition system 1 to have a more compact circuit layout, improving its size and flexibility. In this embodiment, by setting the power supply of the main control module to a DC power supply, the entire device can be powered by a lithium battery module, further facilitating portability.

[0111] Optionally, combined Figure 1 and Figure 2 As shown, in some embodiments of this application, the power module 500 further includes an Ethernet power supply circuit 520, which is connected to an Ethernet cable to transmit power via the network cable. Specifically, the Ethernet power supply circuit 520 includes an Ethernet isolation transformer 521, an Ethernet power supply controller 522, and an Ethernet data transmitter 523. The input terminal of the Ethernet isolation transformer 521 is connected to the Ethernet cable, the input terminal of the Ethernet power supply controller 522 is connected to the output terminal of the Ethernet isolation transformer 521, the output terminal of the Ethernet power supply controller 522 is connected to the protection circuit 420, and the Ethernet data transmitter 523 connects the Ethernet isolation transformer 521 and the main control module 300. The Ethernet power supply controller 522 can be a PoE (Power over Ethernet) chip, and the Ethernet data transmitter 523 can be an Ethernet physical layer chip (PHY).

[0112] It should be noted that the Ethernet PHY chip is an integrated circuit specifically designed for handling physical layer data transmission. It converts digital signals into analog signals and enables high-speed data transmission between devices. Its main functions also include clock extraction, differential signal transmission, auto-negotiation, fault diagnosis, and energy-saving control. The clock extraction function extracts the clock signal from the received data to synchronize data transmission and reception. Differential signal transmission reduces interference and transmission error rate, improving data transmission reliability. The auto-negotiation function allows the PHY chip to automatically adjust the transmission rate and operating module according to the peer device. The fault diagnosis function helps users quickly locate and resolve network problems. The energy-saving control function reduces power consumption and saves energy when network traffic is low. The combination of the PoE chip and the PHY chip effectively improves the integration of the EEG acquisition system 1, thereby enhancing its portability and flexibility, while still achieving all the functions of EEG acquisition.

[0113] Optionally, combined Figure 1 and Figure 2 As shown, in some embodiments of this application, the EEG acquisition system 1 further includes a storage module 600, which includes a storage medium 610 and a level conversion circuit 620. The storage medium 610 is configured to store EEG signal data, and the level conversion circuit 620 connects the storage medium 610 and the processing unit 320.

[0114] Optionally, in some specific examples, the storage medium 610 can be a TF card (Micro SD Card), which is more conducive to the overall miniaturization of the device and has lower power consumption. The level conversion circuit 620 can be implemented by an SDIO (Secure Digital Input and Output) conversion chip. The SDIO level conversion chip is mainly used to convert signals between different voltage levels to ensure compatibility and communication between different devices or modules.

[0115] It should be noted that the SDIO level conversion chip is mainly used for level conversion of devices such as SD cards and SDIO cards. In some embodiments, the SDIO level conversion chip can also be used to connect SSDs, especially when the SSD needs to communicate through the SDIO interface.

[0116] Optionally, in some embodiments, a chip can be used to construct a hardware buffer, such as a DDR4 chip, to ensure that there is sufficient buffer space in the FPGA to temporarily store data during high-speed real-time signal acquisition, which can effectively alleviate the pressure on the management terminal caused by the time difference between data processing and transmission.

[0117] Furthermore, the large amount of data generated during real-time acquisition of high-throughput EEG signals poses a significant challenge to the real-time data throughput and processing capabilities of the EEG acquisition system 1. To ensure smooth and stable data transmission, the main control module 300 can be configured with an external chip cache as the main data cache area, and in conjunction with the on-chip cache resources of the FPGA, two micro-cache areas can be set up to regulate the data flow, forming a three-level cache structure. Data is stored in the three-level cache structure to assist in achieving data buffering and data decoupling functions.

[0118] Optionally, combined Figure 12The diagram shows a specific circuit structure of an optional storage module 600 according to this application. By matching different chips or circuits with multiple voltage power supplies, power consumption can be effectively reduced. Furthermore, by setting up dual data buses such as DAT0B1 / DAT1B1 / DAT2A / DAT3A, high-speed parallel transmission is achieved through time-division multiplexing. Overall, this circuit, through multi-voltage coordination and a dual-bus architecture, achieves highly reliable storage in a compact layout, which is beneficial for improving the integration and flexibility of the EEG acquisition system 1.

[0119] Optionally, combined Figure 2 As shown, in some embodiments of this application, the EEG acquisition system 1 further includes an isolation and protection module 700, which includes a power isolation circuit 710, a communication isolation circuit 720, and an electrostatic discharge protection circuit 730. Specifically, the power isolation circuit 710 is disposed on the series line between the acquisition module 200 and the voltage regulation module, the communication isolation circuit 720 is disposed on the series line between the acquisition module 200 and the logic control unit 310, and the electrostatic discharge protection circuit 730 is disposed on the series line between multiple modules.

[0120] More specifically, the electrostatic discharge (ESD) protection circuit 730 is installed in the series connection between the EEG electrode 100 and the EEG acquisition submodule 210. Since the EEG electrode 100 is in direct contact with the human body, it is prone to static electricity. The ESD protection circuit 730 protects the sensitive amplifier of the acquisition module 200 from ESD damage and ensures that signal quality is not interfered with. Furthermore, medical equipment must meet safety standards to prevent leakage current from harming the patient.

[0121] Optionally, the electrostatic discharge protection circuit 730 is also provided on the series line between the charging interface and the charging management circuit 440. Since the charging interface is exposed, static electricity may be generated when plugging and unplugging. The electrostatic discharge protection circuit 730 is provided here to prevent surges or static electricity from damaging the power management chip and battery module through the charging line, ensuring the safety of the charging process and avoiding overvoltage or overcurrent from affecting the system stability.

[0122] Optionally, the electrostatic discharge protection circuit 730 is also installed on the series line between the Ethernet data transmitter 523 and the Ethernet isolation transformer 521. Since the Ethernet interface is often connected to external devices, it is susceptible to lightning strikes or static electricity. The electrostatic discharge protection circuit 730 is installed here to suppress transient voltages and protect the PHY chip. At the same time, it works with the isolation transformer to block common-mode interference and ensure the stability and reliability of data communication.

[0123] Optionally, the electrostatic discharge protection circuit 730 is also provided on the series line between the storage medium 610 and the level conversion circuit 620. Since storage devices such as SD cards or SSDs are frequently inserted and removed, static electricity is easily generated. The electrostatic discharge protection circuit 730 is provided here to prevent static electricity from damaging the storage controller and conversion chip, maintain data integrity, and avoid logical errors or data loss.

[0124] Optionally, in some embodiments of this application, in conjunction with Figure 13 As shown, the electrostatic discharge protection circuit 730 has 64 input channels, each equipped with two diodes. The anodes of the diodes are connected to the input ports respectively, and the cathodes of all diodes are connected to the common ground terminal GND, forming a star grounding network, which can ensure the rapid discharge of electrostatic energy.

[0125] It is important to understand that the EEG acquisition system 1 of this application, with its high degree of integration and functional completeness, can not only be deployed at the bedside, transmitting data and power via network cable and management terminal host communication, to collect EEG data long-term, but also perform offline acquisition, powered by a battery, storing the acquired data in the local storage module 600, thus removing it from the bedside environment and allowing the patient to be in a comfortable environment where they can move freely. Furthermore, the relevant data can also be decoded in real time and transmitted to the management terminal via a wireless communication chip.

[0126] It is worth noting that when the power module 500 uses a DC power supply, the EEG acquisition system 1 can be used completely detached from the hospital bed, greatly improving its portability and flexibility. Specifically, the main control module 300 manages the normal operation of the acquisition module 200 and the EEG electrodes 100; the storage module 600 stores the acquired data using a three-level cache structure, ensuring that the data is not lost. Simultaneously, the acquisition module 200 and the main control module 300 can also be integrated into different micro-devices. Using a backpack or mobile cart, the EEG acquisition system 1 can move with the user. The data stored in the three-level cache structure of the storage module 600 can also be further transmitted, under the control of the main control module 300, to a fixed management terminal or a mobile management terminal via a wireless communication chip as needed. The acquired EEG data can then be viewed in real time via software on the management terminal.

[0127] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. An electroencephalogram (EEG) acquisition system, characterized in that, include: Several EEG electrodes are connected to the brain of an organism to detect brain electrical signals; The acquisition module is connected to the EEG electrodes to acquire EEG signals and preprocess the EEG signals. The acquisition module includes at least one EEG acquisition sub-module, which integrates an amplifier, a multiplexer and an analog-to-digital converter. as well as The main control module performs secondary processing on the EEG signal. The main control module includes a logic control unit and a processing unit. The logic control unit is connected to the acquisition module, and the processing unit is connected to the management terminal to configure the parameters of the logic control unit and send the secondary processed EEG signal to the management terminal.

2. The EEG acquisition system according to claim 1, characterized in that, The acquisition module and the main control module are connected through multiple differential signal pairs, including control signal differential pairs and data interaction differential pairs. The two signal lines of each differential signal pair are connected by a matching resistor, and the matching resistor and the plurality of differential signal pairs form an impedance matching network; The main control module has 1 to 8 differential signal input interfaces.

3. The EEG acquisition system according to claim 1 or 2, characterized in that, The acquisition module includes at least two EEG acquisition sub-modules connected in parallel via a connecting chip, each of which is integrated within a single package structure. The connection chip includes: Two symmetrically distributed pin arrays, wherein the number of pins in the pin array on one side of the connecting chip is consistent with the number of channels in a single EEG acquisition submodule; Each of the aforementioned EEG acquisition submodules includes: A 64-channel EEG signal input terminal, wherein each channel's EEG signal input terminal is independently connected to an electrode contact on the EEG electrodes; and Differential signal output terminals, each of which is connected to an independent differential signal input interface of the main control module.

4. The EEG acquisition system according to claim 1, characterized in that, The acquisition module further includes an electron supply module, which includes: A rectifier chip includes a rectifier input terminal, a rectifier ground terminal, a rectifier enable terminal, and a rectifier output terminal, wherein the rectifier output terminal is configured to output a DC voltage; A first inductor, one end of which is connected to the rectified voltage, and the other end of which is connected to the rectified input terminal; The second inductor has one end connected to the digital circuit ground and the other end connected to the analog circuit ground and the rectifier ground terminal. A first capacitor, the first plate of the first capacitor is connected to the rectifier input terminal, and the second plate of the first capacitor is connected to the analog circuit ground; A first resistor, one end of which is connected to the first plate of the first capacitor, and the other end of which is connected to the rectifier enable terminal; The second capacitor has its first plate connected to the rectifier output terminal and its second plate connected to the analog circuit ground.

5. The EEG acquisition system according to claim 1, characterized in that, The logic control unit includes a programmable gate array chip, the processing unit includes an ARM processor, the logic control unit and the processing unit are connected via an expandable interface bus, and the processing unit is connected to the management terminal via a wireless communication chip.

6. The EEG acquisition system according to claim 1, characterized in that, The EEG acquisition system further includes a power management module connected to the power module, the power management module comprising: A voltage regulating circuit, the input of which is connected to the power supply module, and the output of which generates multi-stage voltages and is connected to the main control module and the acquisition module; and A protection circuit is connected in series between the power supply module and the voltage regulation circuit to suppress abnormal current surges; wherein, the voltage regulation circuit includes: A boost unit, connected to the power module, to boost the voltage output by the power module; and A DC-DC converter unit is connected to the boost unit to convert the boosted voltage into a multi-stage voltage. The protection circuit includes: A current sampling unit, connected to the power module, is used to monitor the output current of the power module; and... An overcurrent protection unit, connected to the current sampling unit, cuts off the enable signal of the voltage regulation circuit when the current sampling unit detects an overcurrent.

7. The EEG acquisition system according to claim 6, characterized in that, The power management module also includes: A switching circuit is provided in series between the protection circuit and the voltage regulating circuit. The switching circuit is also connected to the processing unit so as to be controlled to cut off or connect the power supply path between the power module and the voltage regulating circuit.

8. The EEG acquisition system according to claim 6 or 7, characterized in that, The power module includes a DC power supply, which is connected to an external power source via a charging interface. The power management module also includes a charging management circuit, which is a series line between the charging interface and the protection circuit. And / or the power module further includes an Ethernet power supply circuit, which is connected to an Ethernet cable; The Power over Ethernet (PoE) circuit includes: An Ethernet isolation transformer, the input of which is connected to the Ethernet cable; An Ethernet power supply controller, wherein the input terminal of the Ethernet power supply controller is connected to the output terminal of the Ethernet isolation transformer, and the output terminal of the Ethernet power supply controller is connected to the protection circuit; and An Ethernet data transmitter connects the Ethernet isolation transformer to the main control module.

9. The EEG acquisition system according to claim 8, characterized in that, The EEG acquisition system further includes a storage module, which comprises: Storage medium, configured to store data of the electroencephalogram (EEG) signals; and A level conversion circuit connects the storage medium to the processing unit.

10. The EEG acquisition system according to claim 9, characterized in that, The EEG acquisition system also includes an isolation and protection module, which comprises: A power isolation circuit is provided in a series line between the acquisition module and the voltage regulation circuit; A communication isolation circuit is provided in the series line between the acquisition module and the logic control unit; and The electrostatic discharge protection circuit includes a series line between the EEG electrodes and the EEG acquisition submodule, a series line between the charging interface and the charging management circuit, a series line between the Ethernet data transmitter and the Ethernet isolation transformer, and a series line between the storage medium and the level conversion circuit.

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