RGMII delay automatic compensation system and method
By integrating Ethernet MAC, sampling, and delay compensation circuitry, the system automatically detects and dynamically adjusts the RGMII interface signal delay, resolving the signal delay inconsistency caused by PCB trace length differences and improving communication reliability and adaptability.
Patent Information
- Application Number
- CN202511616867.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-06
- Publication Date
- 2025-12-12
AI Technical Summary
In existing technologies, the RGMII interface suffers from sampling errors and communication interruptions due to signal line delay deviations in PCB layout. It lacks accurate delay compensation capabilities, and cannot guarantee reliable signal sampling, especially when there are large differences in wiring length.
The Ethernet MAC circuit, sampling circuit, and delay compensation circuit are integrated into a single programmable logic device. A high-frequency signal is generated by frequency multiplication through a phase-locked loop for sampling. The signal line delay is automatically detected and the relative delay time is calculated. The signal transmission and reception timing is dynamically adjusted to achieve accurate compensation.
It improves signal integrity and stability of the RGMII interface in different hardware designs, enhances the system's adaptability to cabling scenarios, and reduces communication failures and redesign costs.
Smart Images
Figure CN121125028A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of electronic communication, in particular to a RGMII delay automatic compensation system and method. BACKGROUND
[0002] In the field of Ethernet communication, RGMII (Reduced Gigabit Media Independent Interface) interface is widely used due to its high efficiency. However, RGMII interface has very strict timing requirements, requiring signals within a group to maintain strict equal-length wiring to ensure signal synchronization. In actual PCB layout, due to physical limitations such as component position, wiring space, etc., it is extremely difficult to achieve absolute equal-length of signal lines, resulting in delay deviation between signal lines in each group. When the delay deviation exceeds a certain range, sampling errors will occur at the receiving end, causing signal integrity problems such as data packet loss and communication interruption.
[0003] In the prior art, a method of configuring a fixed delay at the Ethernet PHY end is usually used to increase the sampling margin. However, this method is only applicable to cases where the wiring length difference is small. When the actual delay difference between signal lines exceeds the fixed delay amount, this method fails to ensure reliable sampling. In addition, this scheme lacks the ability to measure and adapt to actual wiring delays, and cannot accurately compensate for different PCB layouts. Therefore, there is an urgent need for a solution that can automatically detect signal delays and achieve precise dynamic compensation to fundamentally improve the robustness and reliability of RGMII interface in different hardware designs. SUMMARY
[0004] In view of the above-mentioned defects or shortcomings in the prior art, it is desirable to provide a RGMII delay automatic compensation system and method to solve the above-mentioned problems.
[0005] The first aspect of the present application provides a RGMII delay automatic compensation system, comprising: an Ethernet MAC circuit, configured to transmit and receive data through a RGMII interface; a sampling circuit, connected with the RGMII interface, configured to sample multiple signal lines of the RGMII to obtain phase information between signals; a delay compensation circuit, connected with the high-precision sampling circuit and the Ethernet MAC circuit respectively, configured to calculate delay time of each signal line according to the phase information, and control the Ethernet MAC circuit to perform delay compensation.
[0006] According to the technical scheme provided in the embodiment of the present application, the Ethernet MAC circuit, the sampling circuit and the delay compensation circuit are integrated in a single programmable logic device.
[0007] According to the technical scheme provided in the embodiment of the present application, the sampling circuit always samples the RGMII signal using high frequency generated by a phase-locked loop frequency multiplication.
[0008] According to the technical scheme provided in the embodiment of the present application, the delay compensation circuit is configured to determine a reference channel from the multiple signal lines based on the phase information, and calculate the delay time of the remaining signal lines relative to the reference channel; the reference channel is the channel corresponding to the signal line with the shortest delay time.
[0009] According to the technical scheme provided in the embodiment of the present application, the delay compensation circuit is further configured to send the identification information of the reference channel and the relative delay time of the remaining signal lines relative to the reference channel to the Ethernet MAC circuit.
[0010] The second aspect of the present application provides an RGMII delay automatic compensation method, applied to the RGMII delay automatic compensation system as described above, and the method comprises: receiving phase information between signals, the phase information being obtained by sampling multiple signal lines of an RGMII interface by a sampling circuit; calculating the delay time of each signal line according to the phase information; adjusting the signal transmission and reception timing of the RGMII interface according to the calculated delay time, so as to realize delay automatic compensation.
[0011] According to the technical scheme provided in the embodiment of the present application, the calculation of the delay time of each signal line comprises: determining a reference channel from the multiple signal lines based on the phase information; calculating the delay time of the remaining signal lines relative to the reference channel; wherein the reference channel is the channel corresponding to the signal line with the shortest delay time.
[0012] According to the technical scheme provided in the embodiment of the present application, the phase information is represented by one or more pulse signals, each pulse signal corresponding to a predetermined type of level jump occurring on a signal line; the determination of the reference channel and the calculation of the delay time comprise: starting timing when the first pulse signal arrives based on the received pulse signal; recording the arrival time of the subsequent pulse signal; Calculate the relative delay time between each signal line based on the arrival time of the first pulse signal and the arrival time of the subsequent pulse signal.
[0013] According to the technical scheme provided by the embodiment of the application, the phase information is acquired in response to a set test signal sequence passing through the RGMII interface; the set test signal sequence includes: first signals passing through the RGMII interface, making all data lines become low, and second signals passing through the RGMII interface, making all data lines become high.
[0014] According to the technical scheme provided by the embodiment of the application, after the delay time is calculated, the method further includes: Outputting the identification information of the reference channel and the relative delay time of the remaining signal lines relative to the reference channel; The adjustment of the signal transceiving timing includes: Based on the output identification information and the relative delay time, a delay is applied to the corresponding data channel, so that all signal lines can be synchronously transmitted and received.
[0015] Compared with the prior art, the application has the beneficial effects that: by adopting the system architecture composed of an Ethernet MAC circuit, a sampling circuit and a delay compensation circuit, the phase information between the multiple signal lines of the RGMII can be automatically and accurately acquired, and the specific delay time of each signal line can be calculated accordingly, and finally the automatic compensation of the RGMII interface signal transceiving timing is realized; the problem of inconsistent signal delay caused by the length difference of PCB wiring is solved, the signal integrity and system stability of the RGMII interface communication are effectively improved, the limitation of relying on fixed delay configuration is avoided, the adaptability of the system to different wiring scenarios is enhanced, the communication failure and system redesign caused by timing problems are reduced, the reliability of the product is improved, and the development and production cost is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0016] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments made with reference to the accompanying drawings: Figure 1 The structural schematic diagram of the RGMII delay automatic compensation system provided for the embodiment 1 is shown in the figure; Figure 2 The step flowchart of the RGMII delay automatic compensation method provided for the embodiment 2 is shown in the figure.
[0017] Reference numerals: DETAILED DESCRIPTION The application will be described in further detail below with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the application. In addition, it should be noted that only parts related to the application are shown in the drawings for ease of description.
[0018] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and embodiments.
[0019] Embodiment 1 Please refer to Figure 1 The present application provides an RGMII delay automatic compensation system, comprising: an Ethernet MAC circuit 10, which is used for receiving and transmitting data through an RGMII interface; a sampling circuit 20, which is connected with the RGMII interface and is used for sampling multiple signal lines of the RGMII to obtain phase information between signals; a delay compensation circuit 30, which is connected with the high-precision sampling circuit 20 and the Ethernet MAC circuit 10 respectively, and is used for calculating delay time of each signal line according to the phase information and controlling the Ethernet MAC circuit 10 to perform delay compensation.
[0020] Specifically, the Ethernet MAC circuit 10 serves as a core control unit of the system and is responsible for data receiving and transmitting communication with an external PHY chip through the RGMII interface. The Ethernet MAC circuit 10 has a data delay adjustment function and can independently adjust the transmission and reception time sequence of each data channel according to received delay control information. The sampling circuit 20 is directly connected with all data lines of the RGMII interface and is responsible for real-time monitoring of level state changes of each signal line. The sampling circuit 20 obtains phase information reflecting the time sequence relationship between signals by continuously sampling these signal lines. In this embodiment, the RGMII interface includes 8 data lines D0-D7. The delay compensation circuit 30 serves as a processing core of the system and is connected with the sampling circuit 20 and the Ethernet MAC circuit 10 respectively. The delay compensation circuit 30 receives phase information from the sampling circuit 20, accurately calculates the relative delay time between each signal line of the RGMII through a specific algorithm, generates corresponding compensation control instructions based on the calculation results, and sends the compensation control instructions to the Ethernet MAC circuit 10 to control the time sequence adjustment of each data channel, so as to finally realize delay automatic compensation.
[0021] The three circuits cooperate with each other to form a complete closed-loop control system: the sampling circuit 20 is responsible for signal monitoring, the delay compensation circuit 30 is responsible for information processing and decision-making, and the Ethernet MAC circuit 10 is responsible for compensation execution, thereby solving the problem of inconsistent signal delays caused by differences in PCB wiring lengths.
[0022] Further, the Ethernet MAC circuit 10, the sampling circuit 20, and the delay compensation circuit 30 are integrated in a single programmable logic device.
[0023] Specifically, considering system integration and signal processing efficiency, the Ethernet MAC circuit 10, the sampling circuit 20, and the delay compensation circuit 30 can be integrated in a single programmable logic device. This integrated design not only reduces the additional delay introduced by external wiring, but also improves the reliability and reconfigurability of the system. In this embodiment, the programmable logic device is an FPGA.
[0024] Further, the sampling circuit 20 samples the RGMII signal using a high-frequency signal generated by a phase-locked loop frequency multiplier.
[0025] Specifically, to ensure sampling accuracy, the sampling circuit 20 uses a high-precision clock for signal sampling. This high-frequency sampling clock is generated by frequency multiplication of a reference clock through a phase-locked loop (PLL), so that the sampling circuit 20 can sample each data line at a speed much higher than the RGMII signal rate, thereby accurately capturing the subtle timing differences of signal transition edges.
[0026] Further, the delay compensation circuit 30 is configured to determine a reference channel from the plurality of signal lines based on the phase information, and calculate the delay time of the remaining signal lines relative to the reference channel; the reference channel is the channel corresponding to the signal line with the shortest delay time.
[0027] Specifically, the delay compensation circuit 30 is configured to perform an automated delay measurement process. Specifically, based on the phase information provided by the sampling circuit 20, the following operations are performed: First, determine the reference channel. The delay compensation circuit 30 identifies the fastest path of signal transmission among all signal lines by analyzing the phase information of the signal lines. In a specific implementation, this is achieved by detecting the transition order of each signal line from low to high: the channel corresponding to the signal line with the shortest delay time will have its level transition detected first, and this channel is determined as the reference channel. For example, if the rising edge of data line D0 arrives first, then D0 is determined as the reference channel.
[0028] Secondly, the relative delay time of the rest of the signal lines is calculated. After the reference channel is determined, the delay compensation circuit 30 takes the signal transition time of the reference channel as the starting point of timing (T0), and accurately measures the arrival time (T1, T2,..., T7) of the same type of transition signal of each of the rest of the signal lines. Then, by calculating T1-T0, T2-T0,..., T7-T0, the specific delay time of each of the rest of the signal lines relative to the reference channel is obtained. This series of calculations obtains the accurate delay amount of all signal lines in the RGMII bus group relative to the shortest path.
[0029] The delay compensation circuit 30 does not use a fixed external clock as an absolute reference, but uses the fastest signal in the group as a dynamic reference to automatically adapt to the specific wiring of different PCB boards, thereby realizing high-precision relative delay measurement.
[0030] After the delay compensation circuit 30 completes the determination of the reference channel and the calculation of the relative delay time of each signal line, it enters the compensation execution phase. Specifically, the delay compensation circuit 30 is configured to perform the following operations: The identification information of the reference channel and the relative delay time of the rest of the signal lines relative to the reference channel are sent to the Ethernet MAC circuit 10.
[0031] In a specific implementation scenario, the process is as follows: assuming that through the foregoing measurement process, it is determined that the data line D0 is the reference channel (i.e., the shortest delay path), and the delay times of the data lines D1 to D7 relative to D0 are calculated as T1, T2,..., T7, respectively. Then, the delay compensation circuit 30 generates a control instruction containing the target channel and the compensation amount, for example, {reference channel: D0, compensation parameter: [D1: T1, D2: T2,..., D7: T7]}, and sends the instruction to the Ethernet MAC circuit 10.
[0032] After receiving the instruction, the Ethernet MAC circuit 10 configures the internal data sending and receiving logic according to the identification information and the relative delay time in the instruction. Specifically, the Ethernet MAC circuit 10 takes the timing of the reference channel D0 as a reference, and applies a compensation delay corresponding to the measured delay time (T1 to T7) in the opposite direction to the timing of the rest of the data channels (D1 to D7), respectively. For example, a compensation delay of T1 is applied to the D1 line with a delay of T1, a compensation delay of T2 is applied to the D2 line with a delay of T2, and so on.
[0033] Embodiment 2 Please refer to Figure 2On the basis of the above embodiment 1, the present embodiment provides an RGMII delay automatic compensation method, applied to the RGMII delay automatic compensation system as described in embodiment 1, the method comprising: S100: receiving phase information between signals, the phase information being obtained by sampling circuit 20 sampling multiple signal lines of the RGMII interface.
[0034] Step S100 is the data input stage of the method. Specifically, the system receives the phase information between signals obtained by sampling circuit 20 sampling multiple data lines (D0-D7) of the RGMII interface. This phase information represents the relative relationship of each signal line in time sequence, which is the basis for subsequent delay calculation.
[0035] S200: calculating the delay time of each signal line according to the phase information.
[0036] Step S200 is the processing and calculation core of the method. Based on the phase information received in step S601, the system performs specific calculation logic to quantify the timing difference between each signal line, thereby obtaining the specific delay time of each signal line.
[0037] S300: adjusting the signal transmission timing of the RGMII interface according to the calculated delay time to realize automatic delay compensation.
[0038] Step S300 is the final execution and output stage of the method. The system uses the accurate delay time data calculated in step S602 to generate corresponding control instructions to dynamically adjust the data transmission timing of the RGMII interface. This adjustment acts on the Ethernet MAC circuit 10, aiming to offset the inherent delay difference introduced by PCB wiring, thereby ensuring that all data signals can be synchronized, and finally realizing automatic compensation of delay.
[0039] Further, the calculation of the delay time of each signal line in step S200 comprises: S201: determining a reference channel from the multiple signal lines based on the phase information; S202: calculating the delay time of the remaining signal lines relative to the reference channel; Wherein, the reference channel is the channel corresponding to the signal line with the shortest delay time.
[0040] Specifically, in step S201, the system identifies and determines the channel corresponding to the signal line with the shortest delay time as the reference channel by analyzing the received phase information. For example, in an eight-bit data bus (D0-D7), the system compares the signal transition timing of all data lines and finds that the signal transition of data line D3 arrives first, and then determines D3 as the reference channel of the group of signal lines. This step ensures that the subsequent delay calculation is referenced to the fastest signal path in the group, thereby truly reflecting the relative delay of other signal lines.
[0041] In step S202, the system takes the key timing point of the reference channel (such as D3 in the previous example) as the timing reference T0, and then accurately measures the arrival time T1, T2,..., T7 of the corresponding timing points of the remaining each signal line (D0-D2, D4-D7). Subsequently, by calculating the time difference ΔT, the specific delay time of each non-reference signal line relative to the reference channel is obtained.
[0042] Further, the phase information is characterized by one or more pulse signals, each pulse signal corresponding to a predetermined type of level transition occurring on a signal line; The determination of the reference channel and the calculation of the delay time include: Based on the received pulse signals, starting timing when the first pulse signal arrives; Recording the arrival time of the subsequent pulse signals; Based on the arrival time of the first pulse signal and the arrival time of the subsequent pulse signals, calculating the relative delay time between the signal lines.
[0043] Specifically, in the present embodiment, the phase information is not directly processed with the original sampling data, but is efficiently characterized by one or more pulse signals. Specifically, the sampling circuit 20, when running, each pulse signal corresponds to a predetermined type of level transition occurring on a signal line. In a preferred embodiment, the "predetermined type of level transition" specifically refers to the transition from low to high (i.e. rising edge). The sampling circuit 20 will monitor each data line (D0-D7) in real time, and whenever it detects such a transition on a certain data line, it will immediately send a narrow pulse to the delay compensation circuit 30. In this way, the eight data lines will theoretically generate eight time-displaced pulse signals in the process of changing from all low to all high, and the distribution of these pulses on the time axis directly reflects the delay difference of each signal line.
[0044] Based on the above pulse signals to determine the reference channel and calculate the delay time, specifically including the steps of: Firstly, the delay compensation circuit 30 continuously monitors the pulse signals from the sampling circuit 20. When the first valid rising edge pulse is detected (e.g. corresponding to data line D0), the circuit immediately clears its internal high-precision timer and starts it. The channel corresponding to this first pulse signal, i.e. the channel with the shortest delay, is by default the reference channel. Its arrival time is defined as the timing origin To.
[0045] Secondly, after starting the timer, the delay compensation circuit 30 continues to receive and record the exact arrival times of the remaining pulse signals, denoted as Ti, T2,..., T7 respectively. These time data are temporarily stored in registers or buffers.
[0046] Thirdly, after all expected pulses are received, the delay compensation circuit 30 performs calculations. It obtains the delay times of the remaining seven signal lines relative to the reference channel by simple subtraction operations. For example, Ti - To is the delay amount of the second pulse corresponding channel relative to the reference channel.
[0047] Further, the phase information is acquired in response to a set test signal sequence passing through the RGMII interface; the set test signal sequence includes: first, a first signal passing through the RGMII interface, so that all data lines become low, and then, a second signal passing through the RGMII interface, so that all data lines become high.
[0048] Specifically, the phase information is acquired in response to a set test signal sequence passing through the RGMII interface, rather than in random communication data. The test sequence is actively triggered by the system at a specific time (e.g. in the system power-on initialization stage or periodic calibration period), or is sent out in cooperation with an external device.
[0049] The set test signal sequence specifically includes two ordered stages: First, a signal is sent through the RGMII interface to make all data lines (D0-D7) simultaneously low. In a typical embodiment, this signal is data byte 0x00. This step aims to reset all signal lines to a unified and determined initial state (all low), to prepare for subsequent observation of the jump.
[0050] Then, after the first signal, a signal is sent through the RGMII interface to make all data lines (D0-D7) simultaneously high. In a typical embodiment, this signal is data byte 0xFF.
[0051] The sampling circuit 20 generates pulse signals for characterizing the delay of each signal line by capturing this deterministic jump edge from all low to all high.
[0052] Further, after the delay time is calculated, the method further comprises: outputting the identification information of the reference channel and the relative delay time of the remaining signal lines with respect to the reference channel; the adjustment of the signal transceiving timing comprises: based on the outputted identification information and relative delay time, applying delay to the corresponding data channel, so that all signal lines can be synchronously transmitted and received.
[0053] Specifically, after the accurate delay time of each signal line with respect to the reference channel is calculated through the foregoing steps, the method further comprises the following operations: The system outputs the calculated key compensation parameters, which include the identification information of the reference channel and the delay time of the remaining signal lines with respect to the reference channel; the identification information of the reference channel explicitly indicates which signal line is the reference channel with the shortest delay, and the delay time of the remaining signal lines with respect to the reference channel is a data set containing the specific delay amount of each signal line. This output action marks the end of the measurement phase and the beginning of the compensation execution phase. These information is sent to the execution unit responsible for signal transceiving, i.e. the Ethernet MAC circuit 10.
[0054] After receiving the above-mentioned identification information and relative delay time, the Ethernet MAC circuit performs specific timing adjustment operations. For example, when transmitting data: the Ethernet MAC circuit 10 takes the timing of the reference channel as the absolute reference, and for each of the remaining signal lines Dn (n = 1 to 7), the Ethernet MAC circuit 10 inserts a digital delay unit with a size of Tn on its data path. After this adjustment, the D0 signal that originally arrives in advance on the physical line will "wait" for the Dn signal that has been delayed for Tn time, and finally all signals (D0 to D7) are synchronously transmitted on the physical layer of the RGMII interface.
[0055] The above description is only the preferred embodiment of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above-mentioned features can be replaced with the technical features disclosed in the present application (but not limited to) with similar functions to form technical solutions.
Claims
1. An RGMII delay automatic compensation system, characterized in that, include: Ethernet MAC circuit (10), the Ethernet MAC circuit (10) is used to send and receive data through the RGMII interface; The sampling circuit (20) is connected to the RGMII interface and is used to sample multiple signal lines of the RGMII to obtain phase information between signals; The delay compensation circuit (30) is connected to the high-precision sampling circuit (20) and the Ethernet MAC circuit (10) respectively. It is used to calculate the delay time of each signal line according to the phase information and control the Ethernet MAC circuit (10) to perform delay compensation.
2. The RGMII deskew auto-compensation system of claim 1, wherein, The Ethernet MAC circuit (10), sampling circuit (20) and delay compensation circuit (30) are integrated into a single programmable logic device.
3. The RGMII deskew auto-compensation system of claim 2, wherein, The sampling circuit (20) uses a high frequency generated by the phase-locked loop frequency multiplication to continuously sample the RGMII signal.
4. The RGMII delay auto-compensation system of claim 3, wherein, The delay compensation circuit (30) is configured to: determine a reference channel from the plurality of signal lines based on the phase information, and calculate the delay time of the remaining signal lines relative to the reference channel; The reference channel is the channel corresponding to the signal line with the shortest delay time.
5. The RGMII deskew auto-compensation system of claim 4, wherein, The delay compensation circuit (30) is further configured to send the identification information of the reference channel and the relative delay time of the remaining signal lines relative to the reference channel to the Ethernet MAC circuit (10).
6. An automatic RGMII delay compensation method, characterized in that, Applied to the RGMII automatic delay compensation system as described in any one of claims 1-5, the method comprises: Phase information between received signals is obtained by sampling circuit (20) sampling multiple signal lines of RGMII interface; Calculate the delay time of each signal line based on the phase information; Based on the calculated delay time, the signal transmission and reception timing of the RGMII interface is adjusted to achieve automatic delay compensation.
7. The RGMII delay automatic compensation method according to claim 6, characterized in that, The calculation of the delay time of each signal line includes: Based on the phase information, a reference channel is determined from the multiple signal lines; Calculate the delay time of the remaining signal lines relative to the reference channel; The reference channel is the channel corresponding to the signal line with the shortest delay time.
8. The RGMII delay automatic compensation method according to claim 7, characterized in that, The phase information is characterized by one or more pulse signals, each pulse signal corresponding to a predetermined type of level transition occurring on a signal line; The process of determining the reference channel and calculating the delay time includes: Based on the received pulse signal, timing is started when the first pulse signal arrives; Record the arrival time of subsequent pulse signals; Based on the arrival time of the first pulse signal and the arrival time of subsequent pulse signals, the relative delay time between each signal line is calculated.
9. The RGMII delay automatic compensation method according to claim 8, characterized in that, The acquisition of the phase information is in response to a set test signal sequence being passed through the RGMII interface; The set test signal sequence includes: first, using the first signal of the RGMII interface to make all data lines go low, and then using the second signal of the RGMII interface to make all data lines go high.
10. The RGMII delay automatic compensation method according to claim 9, characterized in that, After calculating the delay time, the method further includes: Output the identification information of the reference channel and the relative delay time of the remaining signal lines relative to the reference channel; The adjusted signal transmission and reception timing includes: Based on the output identification information and relative delay time, a delay is applied to the corresponding data channel so that all signal lines can transmit and receive synchronously.