Design method, device and equipment of input / output circuit and storage medium

Abstract

The present disclosure provides a design method, device and equipment of an input-output circuit and a storage medium. The design method of the input-output circuit comprises: constructing a parameterized circuit unit corresponding to the input-output circuit; obtaining a circuit configuration parameter; and forming an input-output circuit of a memory according to the parameterized circuit unit and the circuit configuration parameter; wherein the input-output circuit is used to write data into the memory after delaying the data when the memory receives a data write operation instruction, and read data from the memory when the memory receives a data read operation instruction. In the present disclosure, the input-output circuit delays the written data, so that the time of data arrival matches the write clock inside the memory, and the problem of incorrect data writing is solved under the condition of reducing the power consumption of the memory. The input-output circuit keeps the time of data reading unchanged, avoiding the problem of incorrect data reading, thereby improving the reliability of the memory operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a design method, device and equipment of an input-output circuit and a storage medium. BACKGROUND

[0002] At present, with the development of artificial intelligence technology, the processing amount of data is rapidly increasing, and the requirements for the read-write speed and bandwidth of a dynamic random access memory (DRAM) are gradually increasing. However, with the increase of the read-write speed and bandwidth of the dynamic random access memory, the power consumption of the dynamic random access memory gradually increases. In the case of reducing the power consumption of the dynamic random access memory, when a data write operation instruction is received, the dynamic random access memory may have a problem that data cannot be correctly written. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the protection scope of the claims.

[0004] The present disclosure provides a design method, device and equipment of an input-output circuit and a storage medium.

[0005] According to a first aspect of some embodiments of the present disclosure, a design method of an input-output circuit is provided, and the design method of the input-output circuit comprises:

[0006] constructing a parameterized circuit unit corresponding to the input-output circuit;

[0007] obtaining a circuit configuration parameter;

[0008] forming an input-output circuit of a memory according to the parameterized circuit unit and the circuit configuration parameter;

[0009] The input-output circuit is configured to write data into the memory after delaying the data when the memory receives a data write operation instruction, and read data from the memory when the memory receives a data read operation instruction.

[0010] According to some embodiments of the present disclosure, the parameterized circuit unit comprises:

[0011] a delay circuit unit, the delay circuit unit comprising a first switch and a delay unit arranged in series;

[0012] a non-delay circuit unit, the non-delay unit comprising a second switch;

[0013] The delay circuit unit and the non-delay circuit unit are coupled in parallel.

[0014] According to some embodiments of the present disclosure, the parameterized circuit unit further comprises:

[0015] a first RC unit comprising a first resistor and a first capacitor coupled in series between a first power supply and a second power supply, the first RC unit being disposed in the delay circuit unit, a first end of the parameterized circuit unit being coupled between the first resistor and the first capacitor;

[0016] a second RC unit comprising a second resistor and a second capacitor coupled in series between a third power supply and a fourth power supply, the second RC unit being coupled to both the delay circuit unit and the non-delay circuit unit, a second end of the parameterized circuit unit being coupled between the second resistor and the second capacitor.

[0017] According to some embodiments of the present disclosure, the parameterized circuit unit further comprises a first parameter configuration unit for defining control signal parameters for controlling the turn-on and turn-off of the delay circuit unit and the non-delay circuit unit.

[0018] According to some embodiments of the present disclosure, the control signal parameters comprise first control signal parameters of the first switch and second control signal parameters of the second switch, the first control signal parameters comprising first switch identification parameters for turning on and turning off the first switch and delay time parameters of the first switch identification parameters, and the second control signal parameters comprising second switch identification parameters for turning on and turning off the second switch and delay time parameters of the second switch identification parameters.

[0019] According to some embodiments of the present disclosure, when the first switch is multiple, the first control signal parameters further comprise execution order parameters of each of the first switch identification parameters; and when the second switch is multiple, the second control signal parameters further comprise execution order parameters of each of the second switch identification parameters.

[0020] According to some embodiments of the present disclosure, the parameterized circuit unit further comprises a second parameter configuration unit for defining first characteristic parameters for characterizing the characteristics of units and lines.

[0021] According to some embodiments of the present disclosure, the first characteristic parameters comprise delay time parameters of the delay unit, line impedance parameters when the delay circuit unit is turned on and turned off, and line impedance parameters when the non-delay circuit unit is turned on and turned off.

[0022] According to some embodiments of the present disclosure, the parameterized circuit unit further comprises a third parameter configuration unit configured to define a second characteristic parameter used to characterize a characteristic of the device.

[0023] According to some embodiments of the present disclosure, the second characteristic parameter comprises a resistance parameter of the first resistance, a capacitance parameter of the first capacitance, a resistance parameter of the second resistance, a capacitance parameter of the second capacitance, a power supply parameter of the first power supply, a power supply parameter of the second power supply, a power supply parameter of the third power supply, and a power supply parameter of the fourth power supply.

[0024] According to some embodiments of the present disclosure, forming an input / output circuit of a memory according to the parameterized circuit unit and the circuit configuration parameter comprises:

[0025] creating a circuit matrix according to the parameterized circuit unit and the circuit configuration parameter;

[0026] invoking a circuit element according to the circuit matrix to form the input / output circuit.

[0027] According to some embodiments of the present disclosure, after forming an input / output circuit according to the parameterized circuit unit and the circuit configuration parameter, the design method of the input / output circuit further comprises:

[0028] establishing a circuit netlist file according to the input / output circuit.

[0029] A second aspect of the present disclosure provides a design device of an input / output circuit, the design device of the input / output circuit comprising:

[0030] a construction module configured to construct a parameterized circuit unit corresponding to the input / output circuit;

[0031] an acquisition module configured to acquire a circuit configuration parameter;

[0032] a formation module configured to form an input / output circuit according to the parameterized circuit unit and the circuit configuration parameter;

[0033] wherein the input / output circuit is configured to write data into the memory after delaying the data when the memory receives a data write operation instruction, and read data out of the memory when the memory receives a data read operation instruction.

[0034] A third aspect of the present disclosure provides a design device of an input / output circuit, the design device of the input / output circuit comprising:

[0035] a processor;

[0036] a memory for storing processor-executable instructions;

[0037] wherein the processor is configured to perform:

[0038] constructing a parameterized circuit unit corresponding to the input / output circuit;

[0039] obtaining circuit configuration parameters;

[0040] forming an input / output circuit of a memory according to the parameterized circuit unit and the circuit configuration parameters;

[0041] the input / output circuit is configured to write data into the memory after delaying the data when the memory receives a data write operation instruction, and read data out of the memory when the memory receives a data read operation instruction.

[0042] According to a fourth aspect of embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, when instructions in the storage medium are executed by a processor of a design device of an input / output circuit, the design device of the input / output circuit is enabled to perform:

[0043] constructing a parameterized circuit unit corresponding to the input / output circuit;

[0044] obtaining circuit configuration parameters;

[0045] forming an input / output circuit of a memory according to the parameterized circuit unit and the circuit configuration parameters;

[0046] the input / output circuit is configured to write data into the memory after delaying the data when the memory receives a data write operation instruction, and read data out of the memory when the memory receives a data read operation instruction.

[0047] In the design method, apparatus, device and storage medium of the input / output circuit provided by the embodiments of the present disclosure, a parameterized circuit unit corresponding to the input / output circuit is constructed as a template for forming the input / output circuit, thereby reducing the complexity of the design of the input / output circuit. Circuit configuration parameters are obtained, and a configuration mode of the parameterized circuit unit is determined to form an expected input / output circuit. According to the parameterized circuit unit and the circuit configuration parameters, the input / output circuit of the memory is formed to adjust the time of writing data into the memory. When the memory receives a data write operation instruction, the input / output circuit can write the data into the memory after delaying the data. When the memory receives a data read operation instruction, the input / output circuit can directly read the data from the memory. By delaying the written data through the input / output circuit, the time of the data arrival is matched with the write clock inside the memory, and the problem of incorrect data writing can be solved under the condition of reducing the power consumption of the memory. By keeping the time of data reading unchanged through the input / output circuit, the problem of incorrect data reading is avoided, thereby improving the reliability of the memory operation. Meanwhile, since the input / output circuit is formed according to the parameterized circuit unit and the circuit configuration parameters, different input / output circuits can be formed by using different circuit configuration parameters by the user, thereby improving the design efficiency of the input / output circuit.

[0048] Other aspects can become apparent from the following detailed description, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure. In the drawings, like reference numerals are used to represent like elements throughout. The accompanying drawings are of some, but not necessarily all, embodiments of the present disclosure. These drawings should not be considered limiting in scope, because the application can be embodied in many different forms.

[0050] Figure 1 is a flowchart of a design method of an input / output circuit according to an example embodiment;

[0051] Figure 2 is a structural schematic diagram of a parameterized circuit unit according to an example embodiment;

[0052] Figure 3 is a structural schematic diagram of a parameterized circuit unit according to an example embodiment;

[0053] Figure 4 is a flowchart of a design method of an input / output circuit according to an example embodiment;

[0054] Figure 5is a flow chart of a design method of an input / output circuit according to an exemplary embodiment;

[0055] Figure 6 is a flow chart of a design method of an input / output circuit according to an exemplary embodiment;

[0056] Figure 7 is a flow chart of a design method of an input / output circuit according to an exemplary embodiment;

[0057] Figure 8 is a block diagram of a design device of an input / output circuit according to an exemplary embodiment;

[0058] Figure 9 is a block diagram of a design device of an input / output circuit according to an exemplary embodiment.

[0059] In the figure: 10, delay circuit unit; 20, non-delay circuit unit; 30, first resistance-capacitance unit; 40, second resistance-capacitance unit; 100, construction module; 200, acquisition module; 300, formation module; 400, design device of input / output circuit; 401, processor; 402, memory; S1, first switch; S2, second switch; DT, delay unit; R1, first resistance; R2, second resistance; C1, first capacitance; C2, second capacitance; N1, first node; N2, second node; Vdd1, first power supply; Vss1, second power supply; Vdd2, third power supply; Vss2, fourth power supply. DETAILED DESCRIPTION

[0060] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, any other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other at will.

[0061] At present, with the development of artificial intelligence technology, the processing amount of data increases rapidly, and the requirements for the read / write speed and bandwidth of dynamic random access memory are gradually increased. With the improvement of the read / write speed and bandwidth of dynamic random access memory, the power consumption of dynamic random access memory gradually increases, which leads to the decline of the stability of dynamic random access memory.

[0062] In order to reduce the power consumption of the dynamic random memory, a frequency reduction circuit is introduced inside the dynamic random memory to reduce the power supply requirement. When the frequency reduction circuit converts the external clock signal into the write clock signal, the frequency reduction circuit needs a certain time to convert the external clock signal, resulting in a certain delay of the write clock signal. Since the input and output circuit samples the data when the write clock signal rises and falls, when the write clock signal has a delay, the time of data sampling deviates from the time of data arrival, resulting in the problem that the data cannot be correctly written.

[0063] Based on this, the present disclosure provides a design method of an input and output circuit, which is designed to eliminate the deviation of the time of data sampling from the time of data arrival. By using parameterized circuit units and circuit configuration parameters, an input and output circuit capable of delaying the written data is formed, so that the time of data sampling matches the time of data arrival to solve the problem that the data cannot be correctly written.

[0064] In an exemplary embodiment of the present disclosure, a design method of an input and output circuit is provided, which can be applied to a design device of an input and output circuit (also referred to as a design platform of an input and output circuit). As shown in Figure 1 Figure 1 A flowchart of the design method of the input and output circuit according to an exemplary embodiment of the present disclosure is shown, which includes:

[0065] S100, constructing a parameterized circuit unit corresponding to the input and output circuit.

[0066] S200, obtaining circuit configuration parameters.

[0067] S300, forming an input and output circuit of the memory according to the parameterized circuit unit and the circuit configuration parameters.

[0068] The input and output circuit is used to delay the data and write the data into the memory when the memory receives a data write operation instruction, and read the data from the memory when the memory receives a data read operation instruction.

[0069] ​In the embodiment, the parameterized circuit unit corresponding to the input and output circuit is constructed as a template of forming the input and output circuit, and the complexity of the input and output circuit design is reduced. The circuit configuration parameters are obtained, the configuration mode of the parameterized circuit unit is determined, and the expected input and output circuit is formed. According to the parameterized circuit unit and the circuit configuration parameters, the input and output circuit of the memory is formed to adjust the time of writing data into the memory. When the memory receives a data write operation instruction, the input and output circuit can write the data into the memory after delaying the data. When the memory receives a data read operation instruction, the input and output circuit can directly read the data from the memory. By delaying the written data through the input and output circuit, the time of the data arrival is matched with the write clock inside the memory, and the problem of incorrect data writing is solved under the condition of reducing the power consumption of the memory. By keeping the data read time unchanged through the input and output circuit, the problem of incorrect data reading is avoided, thereby improving the reliability of the memory operation. At the same time, since the input and output circuit is formed according to the parameterized circuit unit and the circuit configuration parameters, different circuit configuration parameters are used by the user to form different input and output circuits, thereby improving the efficiency of the input and output circuit design.

[0070] In some example embodiments provided in the present disclosure, as shown in Figure 2 The parameterized circuit unit includes a delay circuit unit 10 and a non-delay circuit unit 20. The delay circuit unit 10 includes a first switch S1 and a delay unit DT arranged in series. The non-delay unit 20 includes a second switch S2. The delay circuit unit 10 and the non-delay circuit unit 20 are coupled in parallel. The number of the first switch S1 and the second switch S2 can be one or more.

[0071] In the embodiment, the parameterized circuit unit is composed of the delay circuit unit and the non-delay circuit unit coupled in parallel, the delay circuit unit is used to write the external data after delaying, and the non-delay circuit unit is used to directly read the internal data. The conduction and disconnection of the delay circuit unit are controlled through the first switch, the conduction and disconnection of the non-delay circuit unit are controlled through the second switch, and the external data is delayed through the delay unit. Since the delay circuit unit can delay the written data, the time of the data arrival is matched with the write clock inside the memory, and the problem of incorrect data writing is solved under the condition of reducing the power consumption of the memory. Since the non-delay circuit unit can keep the data read time unchanged, the problem of incorrect data reading is avoided, thereby improving the reliability of the memory operation.

[0072] In some example embodiments provided in the present disclosure, as shown in Figure 3As shown, the parameterization circuit unit further comprises a first RC unit 30 and a second RC unit 40. The first RC unit 30 comprises a first resistor R1 and a first capacitor C1 connected in series between a first power supply Vdd1 and a second power supply Vss1. A first end of the first resistor R1 is coupled to the first power supply Vdd1, and a second end is coupled to a first end of the first capacitor C1 to form a first node N1. A second end of the first capacitor C1 is coupled to the second power supply Vss1. The first RC unit 30 is disposed in the delay circuit unit 10, and can be coupled to the first node N1 through the first switch S1 or the delay unit DT. A first end of the parameterization circuit unit can be coupled between the first resistor R1 and the first capacitor C1 (i.e., the first node N1), or can be coupled to the first node N1 through the first switch S1. The second RC unit 40 comprises a second resistor R2 and a second capacitor C2 connected in series between a third power supply Vdd2 and a fourth power supply Vss2. A first end of the second resistor R2 is coupled to the third power supply Vdd2, and a second end is coupled to a first end of the second capacitor C2 to form a second node N2. A second end of the second capacitor C2 is coupled to the fourth power supply Vss2. The second RC unit 40 is coupled to the delay circuit unit 10 and the non-delay circuit unit 20, and can be coupled to the first switch S1 or the delay unit DT of the delay circuit unit 10 through the second node N2, and can be coupled to the second switch S2 of the non-delay circuit unit 20 through the second node N2. A second end of the parameterization circuit unit is coupled between the second resistor R2 and the second capacitor C2 (i.e., the second node N2). Herein, the first end of the parameterization circuit unit refers to an end of the parameterization unit for coupling to an external device, such as a controller. The second end of the parameterization circuit unit refers to an end of the parameterization unit for coupling to an internal device, such as a read / write amplifier in the memory. When the memory receives a data write operation instruction, the data is transmitted to the delay circuit unit 10 through the first end of the parameterization circuit unit, and then transmitted to the second end of the parameterization circuit unit through the delay circuit unit 10 to write the data into the memory. When the memory receives a data read operation instruction, the data is transmitted to the non-delay circuit unit 20 through the second end of the parameterization circuit unit, and then transmitted to the first end of the parameterization circuit unit through the non-delay circuit unit 20 to read the data from the memory.

[0073] In the embodiment, the first resistor and the second resistor can pull up the data written and read, clamp uncertain data, avoid misjudgment of the data, and improve the reliability of the input and output circuit in transmitting data. The first capacitor and the second capacitor can filter and reduce noise of the data written and read, eliminate interference in the data, and improve the reliability of the input and output circuit in transmitting data. The first resistor-capacitor unit is arranged in the delay circuit unit, the data written can be directly transmitted in the delay circuit unit after processing, and the interference of the line to the data is reduced. The second resistor-capacitor unit can process the data output by the delay circuit unit again, reduce the interference of the delay circuit unit to the data, and improve the reliability of the memory in writing data. At the same time, the second resistor-capacitor unit can process the data read and transmit the data to the outside of the memory through the non-delay circuit unit, and improve the reliability of the memory in reading data.

[0074] In some example embodiments provided in the present disclosure, the parameterized circuit unit further includes a first parameter configuration unit. The first parameter configuration unit is configured to define a control signal parameter, and the control signal parameter is configured to control the turn-on and turn-off of the delay circuit unit 10 and the non-delay circuit unit 20. The control signal parameter includes a control signal name, a control signal value, and a control signal description.

[0075] In the embodiment, the first parameter configuration unit defines the control signal parameter, and the turn-on and turn-off of the delay circuit unit and the non-delay circuit unit can be controlled according to the control signal parameter. Different unit paths can be selected under different requirements. According to the control signal name and the control signal description, the corresponding relationship of the control signal can be determined to select the required control signal. According to the control signal value, the selected control signal can be configured to control the delay circuit unit and the non-delay circuit unit in an expected manner. Since the first parameter configuration unit can select different unit paths in the form of the control signal parameter, the complexity of the control signal can be reduced in the process of designing the input and output circuit, and the efficiency of the input and output circuit design is improved.

[0076] In some example embodiments provided in the present disclosure, the first control signal parameter includes a first control signal parameter of the first switch S1 and a second control signal parameter of the second switch S2. The first control signal parameter includes a first switch identifier parameter for turning on and turning off the first switch S1 and a delay time parameter of the first switch identifier parameter. The second control signal parameter includes a second switch identifier parameter for turning on and turning off the second switch S2 and a delay time parameter of the second switch identifier parameter.

[0077] In the embodiment, the first control signal parameter can be used to control the on and off of the first switch, thereby controlling the on and off of the delay circuit unit. In the first control signal parameter, the first switch identification parameter can directly make the first switch on or off, and the delay time parameter of the first switch identification parameter can make the first switch delay on or off. The second control signal parameter can be used to control the on and off of the second switch, thereby controlling the on and off of the non-delay circuit unit. In the second control signal parameter, the second switch identification parameter can directly make the second switch on or off, and the delay time parameter of the second switch identification parameter can make the second switch delay on or off. Since the first control signal parameter and the second control signal parameter can select different unit paths and their delay times in the form of parameters, the first switch and the second switch can be controlled by inputting corresponding parameters in the process of designing the input and output circuit, thereby improving the efficiency of the input and output circuit design.

[0078] For example, the name of the first switch identification parameter can be D_ctrl_name, the value of which is ctrl, and the description of which is the control signal of the delay path generated by the instruction. When the value of ctrl is 1, the first switch S1 is off. When the value of ctrl is 0, the first switch S1 is on. Alternatively, the name of the first switch identification parameter can also be D_ctrl_short and / or D_ctrl_open, the value of which is 0 and 1, and the description of which is the control signal of the delay path. When the value of D_ctrl_short is 1 and / or the value of D_ctrl_open is 0, the first switch S1 is on. When the value of D_ctrl_short is 0 and / or the value of D_ctrl_open is 1, the first switch S1 is off. The name of the second switch identification parameter can be noD_ctrl_name, the value of which is ctrl, and the description of which is the control signal of the non-delay path generated by the instruction. When the value of ctrl is 1, the second switch S2 is on. When the value of ctrl is 0, the second switch S2 is off. The name of the second switch identification parameter can also be noD_ctrl_short and / or noD_ctrl_open, the value of which is 0 and 1, and the description of which is the control signal of the non-delay path. When the value of noD_ctrl_short is 1 and / or the value of noD_ctrl_open is 0, the second switch S2 is on. When the value of noD_ctrl_short is 0 and / or the value of noD_ctrl_open is 1, the second switch S2 is off. The name of the delay time parameter of the first switch identification parameter and the delay time parameter of the second switch identification parameter can be delay, which is located after D_ctrl_name and noD_ctrl_name, the value of which is a non-negative number (usually in picoseconds), and the description of which is the delay time of the control signal. For example, the name of the first switch identification parameter and the delay time parameter of the first switch identification parameter is D_ctrl_name-delay, the value of which is ctrl-time, and the description of which is the control signal of the delay path generated by the instruction and the delay time of the control signal. The name of the second switch identification parameter and the delay time parameter of the second switch identification parameter is noD_ctrl_name-delay, the value of which is ctrl-time, and the description of which is the control signal of the non-delay path generated by the instruction and the delay time of the control signal.

[0079] In some exemplary embodiments provided in the present disclosure, when the first switch S1 is multiple, the first control signal parameter further comprises an execution order parameter of each first switch identification parameter. When the second switch S2 is multiple, the second control signal parameter further comprises an execution order parameter of each second switch identification parameter.

[0080] In the embodiment, when the number of the first switches and / or the second switches is multiple, the on and off of the multiple switches can have a certain order, which is determined by the execution order parameter of the first switch identification parameter and the second switch identification parameter. By determining the execution order of the multiple first switches and the second switches, the function realized by the input and output circuit can be increased and the efficiency of the input and output circuit design can be improved in the process of designing the input and output circuit.

[0081] For example, the name of the execution order parameter of the first switch identification parameter can be D_ctrl_order, the value of which is ctrl or ctrl1-ctrl2-…-ctrln (the maximum value of n is the number of the first switches S1), and the description is the control signal order of the delay path. When the value of the first switch identification parameter of each first switch S1 is the same, the value of D_ctrl_order is ctrl, and the execution order is the same. When the value of the first switch identification parameter of at least one first switch S1 is different from the value of the first switch identification parameter of other first switches S1, the value of D_ctrl_order can be ctrl1-ctrl2-…-ctrln. Ctrl1-ctrl2-…-ctrln indicates that ctrl1 is executed first, then ctrl2, and finally ctrln. The name of the execution order parameter of the second switch identification parameter can be noD_ctrl_order, the value of which is ctrl or ctrl1-ctrl2-…-ctrlm (the maximum value of m is the number of the second switches S2), and the description is the control signal order of the non-delay path. When the value of the second switch identification parameter of each second switch S2 is the same, the value of noD_ctrl_order is ctrl, and the execution order is the same. When the value of the second switch identification parameter of at least one second switch S2 is different from the value of the second switch identification parameter of other second switches S2, the value of noD_ctrl_order can be ctrl1-ctrl2-…-ctrlm. Ctrl1-ctrl2-…-ctrlm indicates that ctrl1 is executed first, then ctrl2, and finally ctrlm.

[0082] In some exemplary embodiments provided in the present disclosure, the parameterized circuit unit further comprises a second parameter configuration unit. The second parameter configuration unit is configured to define a first characteristic parameter, and the first characteristic parameter is configured to represent the characteristics of the unit and the line. The first characteristic parameter comprises a first parameter name, a first parameter value, and a first parameter description.

[0083] In the embodiment, the first characteristic parameter is defined by the second parameter configuration unit, the characteristics of the unit and the line can be determined according to the first characteristic parameter determination unit, and the unit and the line are designed under the expected characteristics. According to the first parameter name and the first parameter description, the corresponding relationship between the unit and the line can be determined to select the unit and the line. According to the first parameter value, the selected unit and the line can be configured to achieve the expected characteristics. Since the second parameter configuration unit can determine the characteristics of the unit and the line in the form of the first characteristic parameter, the input and output circuit can achieve the expected effect, thereby improving the efficiency of the input and output circuit design.

[0084] In some example embodiments provided in the disclosure, the first characteristic parameter includes a delay time parameter of a delay unit DT, a line impedance parameter when the delay circuit unit 10 is turned on and turned off, and a line impedance parameter when the non-delay circuit unit 20 is turned on and turned off.

[0085] In the embodiment, the delay time parameter of the delay unit can achieve a certain time delay, thereby delaying the written data. The line impedance parameters of the delay circuit unit and the non-delay circuit unit when turned on and turned off can make the line impedance of the designed input and output circuit reach the expectation, thereby improving the efficiency of the input and output circuit design.

[0086] For example, the name of the delay time parameter of the delay unit DT can be delay_time, the value is a non-negative number (the unit is generally picosecond), and the description is to define the delay time. The name of the line impedance parameter when the delay circuit unit 10 is turned on can be D_short_r, the value is a non-negative number (the unit is generally ohm), and the description is the line impedance when the delay circuit unit is turned on. The name of the line impedance parameter when the delay circuit unit 10 is turned off can be D_open_r, the value is a non-negative number (the unit is generally megaohm), and the description is the line impedance when the delay circuit unit is turned off. The name of the line impedance parameter when the non-delay circuit unit 20 is turned on can be noD_short_r, the value is a non-negative number (the unit is generally ohm), and the description is the line impedance when the non-delay circuit unit is turned on. The name of the line impedance parameter when the non-delay circuit unit 20 is turned off can be noD_open_r, the value is a non-negative number (the unit is generally terohm), and the description is the line impedance when the non-delay circuit unit is turned off.

[0087] In some example embodiments provided in the disclosure, the parameterized circuit unit further includes a third parameter configuration unit, the third parameter configuration unit is configured to define a second characteristic parameter, and the second characteristic parameter is configured to represent the characteristics of the device. The second characteristic parameter includes a second parameter name, a second parameter value, and a second parameter description.

[0088] In the embodiment, the second characteristic parameter is defined by the third parameter configuration unit, the characteristic of the device can be determined according to the second characteristic parameter, the input and output circuit is designed under the expected characteristic. According to the second parameter name and the second parameter description, the corresponding relationship of the device can be determined to select the device. According to the second parameter value, the selected device can be configured to achieve the expected characteristic. Since the third parameter configuration unit can determine the characteristic of the device in the form of the second characteristic parameter, the input and output circuit can achieve the expected effect, thereby improving the efficiency of the input and output circuit design.

[0089] In some example embodiments provided in the present disclosure, the second characteristic parameter includes a resistance parameter of the first resistor R1, a capacitance parameter of the first capacitor C1, a resistance parameter of the second resistor R2, a capacitance parameter of the second capacitor C2, a power supply parameter of the first power supply Vdd1, a power supply parameter of the second power supply Vss1, a power supply parameter of the third power supply Vdd2, and a power supply parameter of the fourth power supply Vss2.

[0090] In the embodiment, the uncertain data can be clamped by the first resistor and the second resistor, thereby pulling up the written and read data. The filtering can be realized by the capacitance parameters of the first capacitor and the second capacitor, thereby filtering the written and read data. The size of the data pull-up voltage and the power consumption of the first resistor and the second resistor can be determined by the power supply parameters of the first power supply, the second power supply, the third power supply and the fourth power supply. The pull-up, filtering and noise reduction effects of the designed input and output circuit can achieve the expectation by the resistance parameters of the first resistor and the second resistor, the capacitance parameters of the first capacitor and the second capacitor, and the power supply parameters of the first power supply, the second power supply, the third power supply and the fourth power supply, thereby improving the efficiency of the input and output circuit design.

[0091] Exemplarily, the resistance parameter of the first resistor R1 can include a resistance value, can be named as D_R, and can be a non-negative number (unit: ohm) which is described as a pull-up resistor of the delay circuit unit. The capacitance parameter of the first capacitor C1 can include a capacitance value, can be named as D_C, and can be a non-negative number (unit: picofarad) which is described as a matching capacitor of the delay circuit unit. The resistance parameter of the second resistor R2 can include a resistance value, can be named as noD_R, and can be a non-negative number (unit: ohm) which is described as a pull-up resistor of the non-delay circuit unit. The capacitance parameter of the second capacitor C2 can include a capacitance value, can be named as noD_C, and can be a non-negative number (unit: picofarad) which is described as a matching capacitor of the non-delay circuit unit. The power supply parameter of the first power supply Vdd1 can include a voltage value, can be named as D_vol, and can be a positive number (unit: volt) which is described as a power supply voltage value of the delay circuit unit. The power supply parameter of the second power supply Vss1 can include a voltage value, can be named as D_vols, and can be any value less than the first power supply (unit: volt) which is described as a common voltage value of the delay circuit unit. The power supply parameter of the third power supply Vdd2 can include a voltage value, can be named as noD_vol, and can be a positive number (unit: volt) which is described as a power supply voltage value of the non-delay circuit unit. The power supply parameter of the fourth power supply Vss2 can include a voltage value, can be named as noD_vols, and can be any value less than the third power supply (unit: volt) which is described as a common voltage value of the non-delay circuit unit.

[0092] It can be understood that, in addition to the resistance value, the resistance parameter of the first resistor R1 and the second resistor R2 can further include a rated power, a temperature coefficient, and an aging voltage, etc. In addition to the capacitance value, the capacitance parameter of the first capacitor C1 and the second capacitor C2 can further include a rated voltage, a temperature coefficient, and a frequency characteristic. In addition to the voltage value, the power supply parameter of the first power supply Vdd1, the second power supply Vss1, the third power supply Vdd2, and the fourth power supply Vss2 can further include a rated power, an efficiency, and a noise, etc.

[0093] In some exemplary embodiments provided in the present disclosure, the parameterized circuit unit further includes a fourth parameter configuration unit, and the fourth parameter configuration unit is configured to define a third characteristic parameter, and the third characteristic parameter is used to characterize a characteristic of a switch. The third characteristic parameter includes a third parameter name, a third parameter value, and a third parameter description.

[0094] In the embodiment, the third characteristic parameter is defined by the fourth parameter configuration unit, the characteristic of the switch can be determined according to the third characteristic parameter, the switch is designed under the expected characteristic to input and output circuit. According to the third parameter name and the third parameter description, the corresponding relationship of the switch can be determined to select the switch. According to the third parameter value, the selected switch can be configured to make the selected switch reach the expected characteristic. Since the fourth parameter configuration unit can determine the characteristic of the switch in the form of the third characteristic parameter, the switch of the designed input and output circuit can reach the expectation, thereby improving the efficiency of the input and output circuit design.

[0095] In some example embodiments provided in the disclosure, the third characteristic parameter includes the switch parameter of the first switch S1 and the switch parameter of the second switch S2. The switch parameter of the first switch S1 includes the number parameter and the type parameter of the first switch S1. The switch parameter of the second switch S2 includes the number parameter and the type parameter of the second switch S2.

[0096] In the embodiment, the switch parameter of the first switch and the second switch can determine the number and type of the switch, so that the designed input and output circuit contains the expected number and type of the switch. Through the switch parameter of the first switch and the second switch, the function of the designed input and output circuit can be expanded, thereby improving the efficiency of the input and output circuit design.

[0097] For example, the number parameter name of the first switch S1 can be numS1, the value is a positive number, and the description is the first switch number. The type parameter name of the first switch can be typeS1, the value is one of the preset values, and the description is the first switch type. The number parameter name of the second switch S2 can be numS2, the value is a positive number, and the description is the second switch number. The type parameter name of the second switch can be typeS2, the value is one of the preset values, and the description is the second switch type. For example, the preset values can be 0, 1, 2, 3, 0 represents N-channel enhancement mode MOS tube, 1 represents N-channel depletion mode MOS tube, 2 represents P-channel enhancement mode MOS tube, and 3 represents P-channel depletion mode MOS tube.

[0098] In some example embodiments provided in the disclosure, the parameterized circuit unit further includes a data parameter configuration unit. The data parameter configuration unit is used to define a data file parameter, and the data file parameter is used to represent the terminal of the parameterized circuit unit. The data file parameter includes a data parameter name, a data parameter value and a data parameter description.

[0099] In the embodiment, the data file parameters are defined by the data parameter configuration unit, the terminals of the parameterized circuit unit can be determined according to the data file parameters, so as to determine the data transmission direction of the designed input / output circuit during reading and writing. According to the data parameter name and the data parameter description, the corresponding relationship of the terminals can be determined, so as to select the terminals. According to the data parameter value, the terminals can be configured. Since the data parameter configuration unit can determine the terminals of the parameterized circuit unit by the data file parameters, the data transmission direction can be determined during the design of the input / output circuit, thereby improving the efficiency of the input / output circuit design.

[0100] In some example embodiments provided in the disclosure, the data file parameters include a first data parameter and a second data parameter, the first data parameter is a parameter of a first terminal of the parameterized circuit unit, and the second data parameter is a parameter of a second terminal of the parameterized circuit unit.

[0101] In the embodiment, the first data parameter and the second data parameter are used as the parameters of the two terminals of the parameterized circuit unit, so as to correspond to the direction of the input / output circuit data transmission, thereby improving the efficiency of the input / output circuit design.

[0102] For example, the name of the first data parameter can be inout1, the value can be an identifier corresponding to the first terminal of the parameterized unit, and the description can be signal data file 1. The name of the second data parameter can be inout2, the value can be an identifier corresponding to the second terminal of the parameterized unit, and the description can be signal data file 2.

[0103] For example, the parameters defined in the first parameter configuration unit, the second parameter configuration unit, the third parameter configuration unit, the fourth parameter configuration unit and the data parameter configuration unit in the parameterized circuit unit are all provided with default values. When the input / output circuit is formed according to the parameterized circuit unit, only the parameters expected to be adjusted can be configured, so as to improve the efficiency of the input / output circuit design.

[0104] For example, by designing the delay circuit unit 10, the non-delay circuit unit 20, the first resistance-capacitance unit 30, the second resistance-capacitance unit 40, the first parameter configuration unit, the second parameter configuration unit, the third parameter configuration unit, the fourth parameter configuration unit and the data parameter configuration unit, the parameterized circuit unit corresponding to the input / output circuit in step S100 is constructed.

[0105] For example, the circuit configuration parameters obtained in step S200 can be real-time input circuit configuration parameters, or can be circuit configuration parameters called from a server.

[0106] In some example embodiments provided in the disclosure, as shown in Figure 4 Figure 4 ​An example of the method flowchart of forming the input-output circuit of the memory according to the parameterized circuit unit and the circuit configuration parameters in step S300 is shown in the figure, which includes:

[0107] S310, creating a circuit matrix according to the parameterized circuit unit and the circuit configuration parameters.

[0108] S320, calling a circuit element according to the circuit matrix to form the input-output circuit.

[0109] In the embodiment, the parameterized circuit unit is configured according to the circuit configuration parameters to create a circuit matrix. The circuit element corresponding to the parameters is called according to the circuit matrix to build a circuit to form the input-output circuit. The input-output circuit is formed by the parameterized circuit unit to form the circuit matrix, which reduces the complexity of the input-output circuit design and improves the efficiency of the input-output circuit design. At the same time, the structure of the input-output circuit can be changed by only changing the circuit configuration parameters, which reduces the complexity of the input-output circuit adjustment.

[0110] An example of the method flowchart of creating the circuit matrix according to the parameterized circuit unit and the circuit configuration parameters in step S310 is shown in the figure, which includes:

[0111] In some example embodiments provided in the disclosure, as shown in Figure 5 Figure 5 An example of the method flowchart of creating the circuit matrix according to the parameterized circuit unit and the circuit configuration parameters in step S310 is shown in the figure, which includes:

[0112] ​S311, determine the first configuration parameter, the second configuration parameter and the third configuration parameter corresponding to the control signal parameter, the first characteristic parameter and the second characteristic parameter according to the circuit configuration parameter.

[0113] S312, call the parameterized circuit unit to determine the first parameter configuration unit, the second parameter configuration unit and the third parameter configuration unit.

[0114] S313, configure the first parameter configuration unit with the first configuration parameter, configure the second parameter configuration unit with the second configuration parameter, and configure the third parameter configuration unit with the third configuration parameter to create the circuit matrix.

[0115] In this embodiment, according to the circuit configuration parameter, the first configuration parameter, the second configuration parameter and the third configuration parameter are extracted as the parameters needed to configure the parameterized circuit unit. The first parameter configuration unit, the second parameter configuration unit and the third parameter configuration unit are determined as the units to be configured by calling the parameterized circuit unit. Each parameter configuration unit is configured with the corresponding configuration parameter to create the circuit matrix. By configuring the corresponding parameter configuration unit in the parameterized circuit unit according to each configuration parameter in the circuit configuration parameter, the complexity of the input and output circuit design is reduced, thereby improving the efficiency of the input and output circuit design.

[0116] In some exemplary embodiments provided in the present disclosure, as shown in Figure 6 Figure 6 The method flow chart of creating the circuit matrix according to the parameterized circuit unit and the circuit configuration parameter in step S310 is exemplarily shown, which includes:

[0117] S314, determine the first configuration parameter, the second configuration parameter, the third configuration parameter and the fourth configuration parameter corresponding to the control signal parameter, the first characteristic parameter, the second characteristic parameter and the third characteristic parameter according to the circuit configuration parameter.

[0118] S315, call the parameterized circuit unit to determine the first parameter configuration unit, the second parameter configuration unit, the third parameter configuration unit and the fourth parameter configuration unit.

[0119] S316, configure the first parameter configuration unit with the first configuration parameter, configure the second parameter configuration unit with the second configuration parameter, configure the third parameter configuration unit with the third configuration parameter, and configure the fourth parameter configuration unit with the fourth configuration parameter to create the circuit matrix.

[0120] ​In this embodiment, according to the circuit configuration parameters, the first configuration parameter, the second configuration parameter, the third configuration parameter and the fourth configuration parameter are extracted as the parameters required for configuring the parameterized circuit unit. The parameterized circuit unit is called to determine the first parameter configuration unit, the second parameter configuration unit, the third parameter configuration unit and the fourth parameter configuration unit as the units to be configured. The configuration parameters are used to configure the parameter configuration units to create the circuit matrix. The fourth configuration unit is configured by adding the fourth configuration parameter, which facilitates the adjustment of the structure of the delay circuit unit and the non-delay circuit unit and the characteristics of the first switch and the second switch, thereby improving the efficiency of the input and output circuit design.

[0121] Exemplarily, the configuration of the first parameter configuration unit with the first configuration parameter, the configuration of the second parameter configuration unit with the second configuration parameter, the configuration of the third parameter configuration unit with the third configuration parameter and the configuration of the fourth parameter configuration unit with the fourth configuration parameter in step S316 can be implemented in the following manner: the first switch and the delay unit are obtained. The first parameter configuration unit, the second parameter configuration unit and the fourth parameter configuration unit are configured according to the first configuration parameter, the second configuration parameter and the fourth configuration parameter, matched with the first switch and the delay unit to form a delay circuit matrix. The second switch is obtained. The first parameter configuration unit, the second parameter configuration unit and the fourth parameter configuration unit are configured according to the first configuration parameter, the second configuration parameter and the fourth configuration parameter, matched with the second switch to form a non-delay circuit matrix. The first power supply, the second power supply, the first resistor and the first capacitor are obtained. The third parameter configuration unit is configured according to the third configuration parameter, matched with the first power supply, the second power supply, the first resistor and the first capacitor to form a first resistance-capacitance matrix. The third power supply, the fourth power supply, the second resistor and the second capacitor are obtained. The third parameter configuration unit is configured according to the third configuration parameter, matched with the third power supply, the fourth power supply, the second resistor and the second capacitor to form a second resistance-capacitance matrix. The circuit matrix is created according to the delay circuit matrix, the non-delay circuit matrix, the first resistance-capacitance matrix and the second resistance-capacitance matrix.

[0122] In some exemplary embodiments provided in the present disclosure, the design method of the input and output circuit further includes the following step: verifying the circuit configuration parameters to determine whether the circuit configuration parameters are correct.

[0123] In this embodiment, after obtaining the circuit configuration parameters, the circuit configuration parameters may have errors, such as the parameter values being outside the value range. The circuit configuration parameters are verified to determine whether the circuit configuration parameters are correct, so as to avoid errors in the input and output circuit. The verification of the circuit configuration parameters through the verification link can increase the accuracy of the input and output circuit design, thereby improving the efficiency of the input and output circuit design.

[0124] In some exemplary embodiments provided in this disclosure, the design method for input / output circuits further includes the following step: establishing a circuit netlist file based on the input / output circuits.

[0125] In this embodiment, after the input / output circuits are formed, a circuit netlist file is created for easy retrieval during memory simulation design. By creating the circuit netlist file, it is not necessary to regenerate it for subsequent use, thereby improving the convenience of using the input / output circuits.

[0126] In some exemplary embodiments provided in this disclosure, such as Figure 7 As shown, the design methods for input / output circuits include:

[0127] S400, construct the parameterized circuit unit corresponding to the input and output circuit.

[0128] S410, Obtain circuit configuration parameters.

[0129] S420. Verify the circuit configuration parameters to determine if they are correct.

[0130] S430. When the circuit configuration parameters are correct, classify, organize and merge the circuit configuration parameters.

[0131] S440. Based on the circuit configuration parameters, determine the first configuration parameter, the second configuration parameter, and the third configuration parameter corresponding to the control signal parameter, the first characteristic parameter, and the second characteristic parameter.

[0132] S450: Call the parameterized circuit unit to determine the first parameter configuration unit, the second parameter configuration unit, and the third parameter configuration unit.

[0133] S460. Configure the first parameter configuration unit with the first configuration parameter, configure the second parameter configuration unit with the second configuration parameter, and configure the third parameter configuration unit with the third configuration parameter to create a circuit matrix.

[0134] S470. Based on the circuit matrix, select circuit elements to form input and output circuits.

[0135] S480. Based on the input and output circuits, create a circuit netlist file.

[0136] In the embodiment, the parameterized circuit unit corresponding to the input / output circuit is constructed as a template for forming the input / output circuit, thereby reducing the complexity of the input / output circuit design. The circuit configuration parameters are acquired and verified to determine whether the circuit configuration parameters are correct, thereby increasing the accuracy of the input / output circuit design. When the circuit configuration parameters are correct, the circuit configuration parameters are classified, sorted and merged, and the redundant parameters are removed for simplification, thereby reducing the time required for designing the input / output circuit. The corresponding parameter configuration units in the parameterized circuit unit are configured by the respective configuration parameters, and a circuit matrix is created, thereby improving the efficiency of the input / output circuit design. The circuit netlist file is established, and subsequent use does not require re-generation, thereby improving the convenience of the input / output circuit in use.

[0137] Exemplarily, in a memory, at least one input / output circuit formed according to the parameterized circuit unit is included.

[0138] Figure 8 A block diagram of a design device of an input / output circuit according to an exemplary embodiment is shown. As shown, the device at least includes a construction module 100, an acquisition module 200 and a template forming module 300. Figure 8

[0139] The construction module 100 is configured to construct a parameterized circuit unit corresponding to the input / output circuit.

[0140] The acquisition module 200 is configured to acquire circuit configuration parameters.

[0141] The template forming module 300 is configured to form an input / output circuit according to the parameterized circuit unit and the circuit configuration parameters.

[0142] The input / output circuit is used to write data into the memory after delaying the data when the memory receives a data write operation instruction. The data is read out from the memory when the memory receives a data read operation instruction.

[0143] In an exemplary embodiment, a design device of an input / output circuit is provided, in which the template forming module 300 is configured to:

[0144] According to the parameterized circuit unit and the circuit configuration parameters, a circuit matrix is created.

[0145] According to the circuit matrix, a circuit element is called to form the input / output circuit.

[0146] In an exemplary embodiment, a design device of an input / output circuit is provided, in which the template forming module 300 is configured to:

[0147] ​According to the circuit configuration parameters, first configuration parameters, second configuration parameters and third configuration parameters corresponding to the control signal parameters, the first characteristic parameters and the second characteristic parameters are determined.

[0148] The parameterized circuit units are called to determine the first parameter configuration unit, the second parameter configuration unit and the third parameter configuration unit.

[0149] The first parameter configuration unit is configured with the first configuration parameters, the second parameter configuration unit is configured with the second configuration parameters, and the third parameter configuration unit is configured with the third configuration parameters, to create the circuit matrix.

[0150] In an example embodiment, a design device of an input / output circuit is provided, in which a forming module 300 is configured to:

[0151] According to the circuit configuration parameters, first configuration parameters, second configuration parameters, third configuration parameters and fourth configuration parameters corresponding to the control signal parameters, the first characteristic parameters and the second characteristic parameters are determined.

[0152] The parameterized circuit units are called to determine the first parameter configuration unit, the second parameter configuration unit, the third parameter configuration unit and the fourth parameter configuration unit.

[0153] The first parameter configuration unit is configured with the first configuration parameters, the second parameter configuration unit is configured with the second configuration parameters, the third parameter configuration unit is configured with the third configuration parameters, and the fourth parameter configuration unit is configured with the fourth configuration parameters, to create the circuit matrix.

[0154] In an example embodiment, a design device of an input / output circuit is provided, which further comprises:

[0155] A checking module is configured to check the circuit configuration parameters to determine whether the circuit configuration parameters are correct.

[0156] In an example embodiment, a design device of an input / output circuit is provided, which further comprises:

[0157] A building module is configured to build a circuit netlist file according to the input / output circuit.

[0158] Figure 9 is a block diagram of a design device of an input / output circuit, i.e., a design device 400 of an input / output circuit, according to an example embodiment. For example, the design device 400 of an input / output circuit can be provided as a terminal device. Referring to Figure 9The input / output circuit design device 400 includes a processor 401, the number of which can be set to one or more as needed. The input / output circuit design device 400 also includes a memory 402 for storing instructions, such as an application program, executable by the processor 401. The number of memories can be set to one or more as needed. The application program stored therein can be one or more. The processor 401 is configured to execute the instructions to perform the above method.

[0159] Those skilled in the art will appreciate that embodiments of the disclosure can be provided as methods, apparatus (devices), or computer program products. Accordingly, the disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the disclosure can take the form of a computer program product on one or more computer-usable storage media (including volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data) embodying computer readable instructions, other data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it will be appreciated by those skilled in the art that a communication medium typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

[0160] In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 402 including instructions, is provided, which can be executed by the processor 401 of the apparatus 400 to complete the above method. For example, the non-transitory computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk and an optical data storage device, etc.

[0161] A non-transitory computer readable storage medium, when the instructions in the storage medium are executed by the processor of the input / output circuit design device, enable the input / output circuit design device to perform:

[0162] Constructing a parameterized circuit unit corresponding to the input / output circuit.

[0163] Obtaining circuit configuration parameters.

[0164] Forming the input / output circuit of the memory according to the parameterized circuit unit and the circuit configuration parameters.

[0165] The input and output circuit is configured to write the data into the memory after delaying the data when the memory receives a data write operation instruction, and read the data from the memory when the memory receives a data read operation instruction.

[0166] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, apparatus (devices) and computer program products according to embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and combinations of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus generate a means for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that tangibly embodies (or stores) the instructions for execution by a machine to produce a machine that, when executed by the machine, to cause the machine to perform the functions specified in the flowcharts and / or block diagrams.

[0167] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that tangibly embodies (or stores) the instructions for execution by a machine to produce a machine that, when executed by the machine, to cause the machine to perform the functions specified in the flowcharts and / or block diagrams.

[0168] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that tangibly embodies (or stores) the instructions for execution by a machine to produce a machine that, when executed by the machine, to cause the machine to perform the functions specified in the flowcharts and / or block diagrams.

[0169] In the present disclosure, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such article or device. Without more limitations, the elements defined by the statement "comprising" do not exclude the presence of additional identical elements in the article or device including the elements.

[0170] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true scope of the disclosure. In accordance with the provisions of the patent statutes, the principle and the preferred embodiments have been described above. It is to be understood, however, that the disclosure is not to be limited to the specific embodiments disclosed, and the disclosure includes all such as can come within the scope of the following claims, as well as R equivalents thereof.

[0171] It is therefore intended that this disclosure be interpreted to include all such modifications and alterations in keeping with the scope of the disclosure.

Claims

1. A design method for an input / output circuit, characterized in that, The design method for the input / output circuit includes: Construct parameterized circuit units corresponding to the input and output circuits; Obtain circuit configuration parameters; The input / output circuit of the memory is formed based on the parameterized circuit unit and the circuit configuration parameters; The input / output circuit is used to write data into the memory after a delay when the memory receives a data write operation instruction; wherein the arrival time of the delayed data is matched with the write clock signal inside the memory, the write clock signal is delayed relative to the external clock signal, and the write clock signal is a down-frequency signal of the external clock signal; when the memory receives a data read operation instruction, the data is read out of the memory.

2. The design method for the input / output circuit according to claim 1, characterized in that, The parameterization circuit unit includes: A delay circuit unit, the delay circuit unit comprising a first switch and a delay unit connected in series; A non-delay circuit unit, the non-delay circuit unit including a second switch; The delay circuit unit and the non-delay circuit unit are connected in parallel and coupled. The parameterization circuit unit further includes: The first RC unit includes a first resistor and a first capacitor disposed between the first power supply and the second power supply and coupled in series. The first RC unit is disposed in the delay circuit unit. The first terminal of the parameterization circuit unit is coupled between the first resistor and the first capacitor. The second RC unit includes a second resistor and a second capacitor disposed between the third power supply and the fourth power supply and coupled in series. The second RC unit is coupled to both the delay circuit unit and the non-delay circuit unit. The second terminal of the parameterized circuit unit is coupled between the second resistor and the second capacitor.

3. The design method for the input / output circuit according to claim 2, characterized in that, The parameterized circuit unit further includes a first parameter configuration unit, which is used to define control signal parameters, and the control signal parameters are used to control the conduction and shutdown of the delay circuit unit and the non-delay circuit unit.

4. The design method for the input / output circuit according to claim 3, characterized in that, The control signal parameters include a first control signal parameter for the first switch and a second control signal parameter for the second switch. The first control signal parameter includes a first switch identifier parameter for turning the first switch on and off and a delay time parameter for the first switch identifier parameter. The second control signal parameter includes a second switch identifier parameter for turning the second switch on and off and a delay time parameter for the second switch identifier parameter. When there are multiple first switches, the first control signal parameters also include execution order parameters for each first switch identifier parameter; when there are multiple second switches, the second control signal parameters also include execution order parameters for each second switch identifier parameter.

5. The design method for the input / output circuit according to claim 2, characterized in that, The parameterized circuit unit further includes a second parameter configuration unit, which is used to define a first characteristic parameter. The first characteristic parameter is used to characterize the characteristics of the unit and the line. The first characteristic parameter includes the delay time parameter of the delay unit, the line impedance parameter when the delay circuit unit is turned on and off, and the line impedance parameter when the non-delay circuit unit is turned on and off.

6. The design method for the input / output circuit according to claim 2, characterized in that, The parameterized circuit unit further includes a third parameter configuration unit, which is used to define a second characteristic parameter, and the second characteristic parameter is used to characterize the characteristics of the device. The second characteristic parameters include the resistance parameters of the first resistor, the capacitance parameters of the first capacitor, the resistance parameters of the second resistor, the capacitance parameters of the second capacitor, the power parameters of the first power supply, the power parameters of the second power supply, the power parameters of the third power supply, and the power parameters of the fourth power supply.

7. The design method of the input / output circuit according to any one of claims 1 to 6, characterized in that, The step of forming the input / output circuit of the memory based on the parameterized circuit unit and the circuit configuration parameters includes: Create a circuit matrix based on the parameterized circuit units and the circuit configuration parameters; Based on the circuit matrix, circuit elements are selected to form the input / output circuit.

8. A design device for an input / output circuit, characterized in that, The design apparatus for the input / output circuit includes: The building module is configured to build parameterized circuit units corresponding to the input / output circuits; The acquisition module is configured to acquire circuit configuration parameters; The forming module is configured to form the input / output circuit of the memory according to the parameterized circuit unit and the circuit configuration parameters; The input / output circuit is used to write data into the memory after a delay when the memory receives a data write operation instruction; wherein the arrival time of the delayed data is matched with the write clock signal inside the memory, the write clock signal is delayed relative to the external clock signal, and the write clock signal is a down-frequency signal of the external clock signal; when the memory receives a data read operation instruction, the data is read out of the memory.

9. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the input / output circuit design device, the input / output circuit design device is able to perform the following: Construct parameterized circuit units corresponding to the input and output circuits; Obtain circuit configuration parameters; The input / output circuit of the memory is formed based on the parameterized circuit unit and the circuit configuration parameters; The input / output circuit is used to write data into the memory after a delay when the memory receives a data write operation instruction; wherein the arrival time of the delayed data is matched with the write clock signal inside the memory, the write clock signal is delayed relative to the external clock signal, and the write clock signal is a down-frequency signal of the external clock signal; when the memory receives a data read operation instruction, the data is read out of the memory.

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