Layout power supply analysis method and device and storage medium

Abstract

The invention discloses a layout power supply analysis method and device and a storage medium, and belongs to the technical field of semiconductors, and the method comprises the steps: extracting physical parameters of each device and parasitic resistance parameters of a power supply network from imported integrated circuit layout data; calculating a current source-to-ground current distribution value of each device according to the physical parameters, and converting a topological structure of the power supply network into a circuit connection relationship netlist comprising power supply nodes and grounding nodes; and in the circuit connection relation netlist, replacing each device with a corresponding current source-to-ground current distribution value, loading parasitic resistance parameters, generating a simulation netlist, inputting the simulation netlist into a simulator to execute direct current analysis, and obtaining actually measured impedance voltage drop data of each power supply node. According to the method, the physical parameters are directly extracted in the layout design stage, the current source-parasitic netlist is dynamically constructed, early-stage high-precision power supply integrity analysis can be achieved without waiting for LVS verification, and the problems of a traditional method in analysis efficiency and precision are effectively solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a layout power analysis method, apparatus, and storage medium. Background Technology

[0002] IR drop (impedance drop) is the voltage drop (ΔV = I × R) caused by the interaction between the resistance (R) of the metal conductors in a power supply network (PDN) and the load current (I) as current flows through them. As process nodes shrink, conductor resistance increases, while increased chip integration leads to a surge in current demand, further exacerbating IR drop. In high-speed computing or low-voltage design scenarios in integrated circuits, IR drop can cause insufficient power supply to critical path transistors, leading to timing violations or even functional failures. Current technologies cannot accurately predict IR drop in the early stages of layout design, often requiring later adjustments by adding metal layers or decoupling capacitors, resulting in longer design cycles and significantly increased costs. Summary of the Invention

[0003] This invention provides a layout power analysis method, apparatus, and storage medium that enables efficient and accurate prediction of power network impedance voltage drop in the early stages of layout design through dynamic current source mapping and parasitic parameter retention techniques.

[0004] Firstly, a layout power analysis method is provided, including:

[0005] Extract the physical parameters of each device and the parasitic resistance parameters of the power network from the imported integrated circuit layout data;

[0006] Calculate the current source-to-ground distribution value of each device based on the physical parameters, and convert the topology of the power network into a circuit connection table containing power nodes and ground nodes.

[0007] In the circuit connection netlist, each device is replaced with the corresponding current source to ground current distribution value and the parasitic resistance parameter is loaded. After generating the simulation netlist, it is input into the simulator to perform DC analysis and obtain the measured impedance voltage drop data of each power supply node.

[0008] Secondly, a layout power analysis device is also provided, comprising:

[0009] The parameter extraction module is configured to extract the physical parameters of each device and the parasitic resistance parameters of the power network from the imported integrated circuit layout data.

[0010] The current distribution module is configured to calculate the current source-to-ground distribution value of each device based on the physical parameters, and convert the topology of the power network into a circuit connection relationship netlist containing power nodes and ground nodes.

[0011] The simulation module is configured to replace each device with the corresponding current source-to-ground current distribution value and load the parasitic resistance parameters in the circuit connection relationship netlist, generate a simulation netlist, and then input it into the simulator to perform DC analysis to obtain the measured impedance voltage drop data of each power supply node.

[0012] Thirdly, a computer-readable storage medium is also provided, on which a computer program is stored, the computer program being loaded by a processor to perform the steps in the layout power analysis method described in any one of the first aspects.

[0013] Beneficial effects:

[0014] This application directly extracts physical parameters from the layout data in the early stages of layout design (avoiding the dependence on traditional LVS verification), and uses dynamic current source mapping technology (converting device current characteristics into current distribution values ​​based on physical parameters) and parasitic parameter preservation technology (parasitic resistance) to construct a simulation netlist that simultaneously contains accurate current load distribution and actual parasitic effects. Thus, power supply impedance drop prediction can be achieved before the complete circuit verification is completed, shortening the analysis cycle compared to traditional methods.

[0015] Therefore, this application achieves high-precision power integrity analysis in the early stages by directly extracting physical parameters and dynamically constructing current source-parasitic netlists (i.e., simulation tables) during the layout design phase, without waiting for LVS verification, effectively solving the problems of analysis efficiency and accuracy of traditional methods. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a simplified schematic diagram of a chip power network provided in some embodiments of this application;

[0018] Figure 2 This is a schematic flowchart of a layout power analysis method provided in some embodiments of this application;

[0019] Figure 3 This is a symmetrical current distribution diagram of NMOS provided in some embodiments of this application;

[0020] Figure 4 This is an NMOS asymmetric current distribution diagram provided in some embodiments of this application;

[0021] Figure 5This is a current distribution diagram of NMOS and PMOS combinations provided in some embodiments of this application;

[0022] Figure 6 This is a structural block diagram of a layout power analysis device provided in some embodiments of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0026] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0027] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0028] The following explains the technical terms used in this application.

[0029] Integrated circuit layout: This is the physical realization of chip design, precisely describing the spatial distribution of all transistors, interconnects, vias, and other devices on a silicon wafer in geometric form. It contains graphic information from multiple layers (such as metal layers, polysilicon layers, and diffusion layers) and must conform to the Design Rules (DRC) of the manufacturing process. The layout power analysis method in this application can be used in LVS (Layout and Schematic) before the layout is completed. Figure 1 The quality of the power network is assessed in advance during consistency checks and verification to reduce the cost of later design iterations.

[0030] A Power Delivery Network (PDN) is a metal interconnect system within a chip that provides stable voltage to all functional units (such as logic gates and memory). It typically employs a mesh or tree structure. Key parameters include metal linewidth, thickness, and the number of vias, directly impacting IR drop and power supply uniformity. For example, in a 5nm process, the PDN needs to carry tens of amperes of total current, and the resistance of the wires (ΔV = I × R) can cause localized voltage drops. The purpose of this application is to optimize the PDN design through early analysis (Floorplan stage) to avoid chip failures caused by IR drop issues later on.

[0031] IR Drop (Impedance Drop): This refers to the voltage drop (ΔV = I × R) caused by the resistance (R) of the metal in the power supply network when current flows through it, resulting in a lower actual supply voltage than the design value. This application rapidly evaluates IRDrop through DC simulation and accurately allocates the current source by combining transistor characteristic dimension parameters, thus improving analysis efficiency.

[0032] Early Design Stage (LVS Not Clean): During the "LVS Not Clean" stage, the layout may contain device connection errors or dimensional deviations, making accurate power supply analysis impossible using traditional methods. This application overcomes this limitation by extracting the physical parameters (such as the aspect ratio or source-drain area) and parasitic resistance parameters of each transistor in the layout, enabling power supply integrity assessment even before LVS is completed, thus shortening the design cycle.

[0033] Floorplan Stage: Floorplan is the initial stage of chip physical design, used to plan the location of macro-modules (such as CPU cores and SRAM), power network architecture, and routing paths. Detailed placement and routing are not yet complete at this stage, but this application can predict IR drop distribution using a pre-defined behavioral current source model.

[0034] like Figure 1 As shown, Figure 1 This is a simplified schematic diagram of a chip power network. It illustrates how, within the chip region, power (represented by a voltage source V) is connected to cells within the chip via a series of parasitic resistances (represented by multiple R's). It demonstrates the path of power from external input to internal chip cells and the distribution of parasitic resistances, which can be used to analyze power integrity-related issues such as voltage drops caused by parasitic resistances during power transmission within the chip.

[0035] The layout power analysis method proposed in this application aims to solve the problems of traditional IR Drop analysis techniques: 1) Existing techniques require the layout to be fully matched with the schematic (LVS Clean) before power analysis can be performed, while this application can perform early evaluation by extracting transistor data from the layout in the early stages of design (before LVS is completed), shortening the design cycle; 2) Traditional netlists can cause distortion in IR (current-resistance voltage drop) analysis. This application accurately allocates current sources by using transistor feature dimensions (such as aspect ratio or source-drain area) and transistor types (such as N-type, P-type, or high threshold voltage transistors), and improves the accuracy of DC simulation by combining preset behavioral current source models (such as VerilogA, a language for behavioral modeling of analog circuits); 3) Existing tools are inefficient for large-scale circuit simulation. This application reduces the number of netlist nodes by using current sources to equivalently replace transistor loads, enabling rapid identification of power network bottlenecks in the floorplan stage, achieving early, high-precision, and low-cost power integrity verification, and reducing the risk of chip failure due to IR Drop.

[0036] On the one hand, this embodiment provides a layout power analysis method, such as Figure 2 As shown, it includes:

[0037] S210: Extract the physical parameters of each device and the parasitic resistance parameters of the power network from the imported integrated circuit layout data.

[0038] For example, the device includes a transistor; the physical parameters include: characteristic size parameters of the transistor, transistor type parameters, and transistor operating state parameters; wherein the characteristic size parameters are the aspect ratio or source-drain area of ​​the transistor, the transistor type parameters include N-type transistor, P-type transistor, or high threshold voltage transistor, and the operating state parameters are on, off, or undefined state.

[0039] Understandably, characteristic dimension parameters, including gate width (W), length (L), source / drain area (S / DArea), and via count, are used to accurately calculate the current load of each transistor, replacing the simplified current estimation in traditional methods. Transistor type parameters, including polarity type (e.g., N / P transistor) and threshold voltage type (e.g., low threshold voltage (LVT), standard threshold voltage (SVT), or high threshold voltage (HVT)), are used to distinguish the current characteristics of different transistors. Operating state parameters, including ON, OFF, and Undefined states, are used to dynamically adjust the current source weights. Parasitic resistance parameters are obtained based on the characteristics of the power network's metal traces (e.g., resistance per unit area) and via connection resistance, and are used to accurately calculate IR Drop (impedance drop). Compared to traditional methods that ignore parasitic parameters, this application improves the accuracy of simulation and avoids power network design deviations caused by insufficient estimation of parasitic effects.

[0040] S220: Calculate the current source-to-ground current distribution value of each device based on the physical parameters, and convert the topology of the power network into a circuit connection relationship netlist containing power nodes and ground nodes.

[0041] Understandably, based on the physical parameters of the transistors extracted in step S210, the equivalent current load value to ground for each transistor is dynamically calculated and converted into a preset behavioral-level current source model (such as Verilog A), replacing the traditional SPICE (a key simulation program for integrated circuits) transistor-level model. Simultaneously, the power network topology (such as power grid and via distribution) is converted into a netlist of circuit connections with parasitic resistance, explicitly marking the VDD / GND (power supply voltage / ground) node connections. This ensures that: current allocation values ​​are correlated with the actual transistor dimensions (e.g., source-drain area affects contact resistance), avoiding distortion problems; current sources replace transistors, reducing the number of netlist nodes (e.g., 100 million transistors can be simplified to tens of millions of power supply nodes), overcoming the bottleneck of large-scale circuit simulation; and a simulable netlist is generated directly in the Floorplan stage without waiting for LVS to complete.

[0042] S230: In the circuit connection relationship netlist, each device is replaced with the corresponding current source to ground current distribution value and the parasitic resistance parameter is loaded. After generating the simulation netlist, it is input into the simulator to perform DC analysis and obtain the measured impedance voltage drop data of each power supply node.

[0043] Understandably, the current distribution values ​​calculated in S220 based on transistor characteristic dimensions (such as source-drain area) and operating states (such as on-state and off-state) are converted into preset behavioral-level current sources (such as NMOS turn-on current modeled as I=K*W / L*(Vgs-Vth)^2, where I represents the drain turn-on current of the NMOS transistor, K represents the process transconductance parameter, W / L represents the aspect ratio of the transistor, Vgs represents the gate-source voltage, and Vth represents the threshold voltage), replacing the traditional SPICE transistor-level model, thus avoiding the efficiency bottleneck of existing technologies. The layout parasitic resistance parameters extracted in step S210 are embedded into the circuit connection relationship netlist, preserving the physical impedance characteristics of the power network and solving the distortion problem caused by simplification in existing technologies. The generated circuit connection relationship netlist contains a simplified topology of current sources + parasitic resistance parameters, which greatly reduces the number of nodes. It is input into the simulator for fast DC analysis and outputs the measured impedance voltage drop data of each power node. This application does not require waiting for LVS to complete and supports PDN evaluation in the Floorplan stage; the current source allocation is associated with the physical parameters of transistors in the actual layout, avoiding the oversimplification of existing technologies, and can also improve simulation speed through Verilog A model abstraction.

[0044] For example, in the circuit connection relationship netlist, replacing each transistor with the corresponding current source to ground current allocation value and loading the parasitic resistance parameter to generate the simulation netlist includes: abstracting the topology of the power network into a graph structure containing node coordinates and connection relationships; assigning the current source to ground current allocation value to each node; and calculating the parasitic resistance parameter based on the geometric parameters and process resistivity of the metal trace.

[0045] Understandably, the power network in the layout is abstracted into a graph structure with coordinate information (e.g., nodes correspond to transistor connection points, and edges represent metal connections); then, based on the transistor type (e.g., NMOS / PMOS), feature size (e.g., W / L / area), and operating state, each transistor is replaced with a precisely calculated current source value (e.g., 1μm). 2NMOS allocation +0.1mA); finally, based on the geometric parameters such as the length / width / thickness of the metal trace and the impedance of the via, and the process resistivity (ρ), the parasitic resistance is calculated (R = ρ·L / WT, where R represents the parasitic resistance, L represents the length of the metal trace, W represents the width of the metal trace, and T represents the thickness of the metal layer), ultimately generating a simulation netlist containing the actual current load and parasitic parameters. This application can achieve high-precision DC IR analysis using VerilogA current sources even before LVS is completed. Compared with traditional methods (such as Totem / Voltus which require a complete transistor model), it preserves the layout geometry to avoid distortion and significantly improves simulation efficiency by simplifying the current source nodes.

[0046] For example, the layout power analysis method further includes: when the layout and schematic... Figure 1 If the consistency check is not completed, the aspect ratio or source-drain area of ​​the transistor is extracted from the layout polygon data as a feature size parameter; based on the preset metal parameter table, the parasitic resistance parameter is obtained by interpolation calculation.

[0047] Understandably, in traditional processes, device parameters can only be extracted after LVS verification is completed. However, this application extracts the physical dimensions of transistors (width / length ratio or source / drain area) by directly analyzing the polygonal data of the layout (such as diffusion region / contact hole patterns). Simultaneously, based on a pre-set metal process parameter table (including the thickness / resistivity of different metal layers), the parasitic resistance of irregular traces is calculated in real time using a spatial interpolation algorithm (e.g., piecewise linear interpolation for trapezoidal traces). This avoids the device identification obstacles when LVS is not completed and can quickly build a simulation model containing device dimensions and parasitic parameters based on the actual layout geometry. This allows power integrity analysis to be performed in the early stages of physical design, shortening the cycle compared to existing technologies.

[0048] In some embodiments, the layout power analysis method further includes:

[0049] S240: Based on the measured impedance voltage drop data, perform at least one of the following verification operations: voltage compliance verification, power supply uniformity verification, and parameter matching verification.

[0050] For example, the voltage compliance verification includes: comparing the measured impedance voltage drop values ​​of each power node with the rated voltage tolerance range of the corresponding process node to verify whether they meet the preset voltage integrity index; the uniformity verification includes: verifying whether the power supply uniformity of the power network meets the design specification requirements based on the spatial distribution characteristics of the impedance voltage drop data on the layout plane; the parameter matching verification includes: verifying the degree of matching between the power network parameter configuration and the device load by analyzing the correlation characteristics between impedance voltage drop and parasitic resistance parameters.

[0051] Understandably, this application overcomes the distortion problem of existing technologies by replacing transistors with current sources and retaining node voltages generated by parasitic resistance. Voltage compliance verification includes comparing the measured impedance voltage drop data of each power node with process standards (such as ΔV < 5% VDD for 3nm process) to ensure that the impedance voltage drop data does not exceed the rated voltage tolerance range. Power supply uniformity verification includes analyzing the spatial distribution of voltage drop data to solve the power supply imbalance problem caused by existing technologies, ensuring that the overall performance of the power network meets design specifications. Parameter matching verification includes verifying whether the current distribution value accurately matches the characteristic dimensions of the transistor, such as aspect ratio (W / L) or source-drain (SD) area, through correlation analysis of impedance voltage drop and parasitic resistance (such as metal layers and vias).

[0052] In some embodiments, step S220, calculating the current source-to-ground current allocation value of each transistor based on the physical parameters, includes: establishing a basic current component based on the product of the characteristic size parameter and the current weight of the transistor type; introducing a compensation current component according to Kirchhoff's first law; performing a weighted synthesis calculation on the basic current component and the compensation current component, and outputting the total current allocation value.

[0053] For example, the current weighting includes: N-type transistors using a first current weight; P-type transistors using a second current weight; and high threshold voltage types using a third current weight.

[0054] For example, in step S230, the calculation principle of the current distribution value from the current source to ground is as follows:

[0055] (1) Different transistor types correspond to different current weights:

[0056]

[0057] Where K(n) is the current weight of the MOS transistor, and Para(n) is the feature size of the MOS transistor. Equation 1 represents the port current I of different MOS transistors (from mos(1) to mos(n)) under the same circuit environment (for the set of MOS transistors analyzed). mos(i) There is a fixed proportional relationship between the transistor (i = 1, n-1, n, etc.) and the product of their respective current weights K(i) and characteristic dimensions Para(i). In other words, the basic current components are established based on the product of the transistor characteristic dimensions (such as Para(n), which is the characteristic dimension of a MOS transistor) and the transistor's current weights (such as K(n)).

[0058] Specifically, K(n) represents the current weight of the MOS transistor, reflecting the characteristic differences in current distribution between different types of MOS transistors (such as N-type and P-type). (For example, N-type and P-type MOS transistors have equal absolute current weights but opposite polarities, reflecting their different current directions in the circuit.) Para(n) represents the feature size of the MOS transistor (e.g., the S / D area), indicating the physical structural dimensions of the MOS transistor itself. This proportional relationship means that the current distribution of MOS transistors is determined by the combined effect of their respective current weights and feature sizes; that is, the current weight and feature size jointly determine the current allocation value that each MOS transistor should receive in the circuit. For example, if a MOS transistor has a larger current weight or a larger feature size, under the same conditions, it will receive a larger share of the current.

[0059] (2) Kirchhoff's First Law (KCL, i.e., the law of node currents):

[0060]

[0061] Kirchhoff's first law states that in a lumped circuit, at any given moment, for any node, the algebraic sum of all currents flowing into and out of the node is always equal to zero.

[0062] Among them, I mos(n) For each MOS port current, representing the current flowing into or out of the MOS transistor from the power supply; I supply External supply current represents the current supplied by the external power source to the entire circuit node. Kirchhoff's first law embodies the balance relationship of current distribution; that is, in actual current distribution, the overall current balance, a compensating current component, must be considered.

[0063] Formula 2 states that the algebraic sum of the port currents of all MOS transistors and the external supply current should result in zero. This reflects the current conservation principle of the entire circuit node, meaning that the external supply current is distributed to each MOS transistor to satisfy the current inflow and outflow balance. For example, if the external supply current I... supply If it is a positive value (indicating current flowing into the node), then each I... mos(n) The sum of these currents should be negative, making their algebraic sum zero. This means that the port currents of these MOS transistors are generally flowing out of the nodes, balancing the inflow of external power supply current.

[0064] (3) Current at each MOS port:

[0065] PMOS port current formula:

[0066]

[0067] Wherein, SD_AREA(n) is the S / D area (source-drain area, representing its characteristic dimensions) of the nth PMOS, which can be obtained through a preset tool (such as LVS Extract). It reflects the basic current-carrying capacity of the physical structure of the PMOS itself. Kp is the current weight of the PMOS (reflecting the current distribution characteristics of the P-type MOS), I supply This is the external supply current. NMOS_total_area-PMOS_total_area represents the difference between the total feature size of the N-type MOS (such as the total area of ​​the S / D converter) and the total feature size of the P-type MOS.

[0068] Formula 3 indicates that by combining the characteristic size SD_AREA(n) of a single PMOS with the current weight Kp and the external supply current I... supply The current IPMOS(n) at the PMOS port is obtained by multiplying the difference in the total characteristic dimensions of the N-type and P-type MOS by a scaling factor. This calculation takes into account the individual characteristics of the PMOS (characteristic dimension), the overall current distribution characteristics of the P-type MOS (current weight), and the relative characteristic dimension relationship with the N-type MOS (denominator). For example, if the total characteristic dimension of the P-type MOS is smaller than that of the N-type MOS (the denominator is positive and larger), the calculated IPMOS(n) will be relatively smaller, all other things being equal.

[0069] NMOS port current formula:

[0070]

[0071] Where SD_AREA(n) is the S / D area (feature size) of the nth NMOS, and Kn is the current weight of the NMOS (reflecting the current distribution characteristics of the N-type MOS).

[0072] Formula 4 also modifies the feature size SD_AREA(n) of a single NMOS by weighting Kn and the external supply current I. supply The current INMOS(n) at the NMOS port is obtained by multiplying the difference in the total characteristic dimensions of the N-type and P-type MOS by a proportional coefficient. Similarly, the port current is calculated by combining the individual characteristics of the NMOS (characteristic dimension), the overall current distribution characteristics of the N-type MOS (current weight), and the relative characteristic dimension relationship with the P-type MOS (denominator). For example, when the total characteristic dimension of the N-type MOS is larger than that of the P-type MOS (the denominator is positive and larger), all other things being equal, INMOS(n) will be relatively larger.

[0073] As can be seen, Formulas 3 and 4 use the current weights corresponding to the transistor type (such as the current weight Kn for N-type MOS and the current weight Kp for P-type MOS) to perform weighted synthesis calculations on the basic current component (reflected by the relationship between Para(n) and K(n)) and the compensation current component (reflected by the balance relationship embodied in the Kirchhoff's first law formula).

[0074] Therefore, by combining the type characteristics of MOS transistors (such as through weights), physical structure features (such as through S / D area), and the current conservation law of the circuit (such as Kirchhoff's first law), the current at each MOS transistor port can be calculated, providing accurate current input parameters for subsequent layout power analysis (such as voltage compliance verification, uniformity verification, parameter matching verification, etc.).

[0075] The following are examples of current allocation based on different transistor types.

[0076] Suppose we classify transistors into four categories based on their polarity (N-type and P-type) and voltage (hv and lv): N-type transistors, P-type transistors, high threshold voltage transistors (hv), and low threshold voltage transistors (lv). These four types of transistors have different current weights k. The current weight k is polarized: the current weight for N-type transistors is positive, representing the sink current; the current weight for P-type transistors is negative, representing the source current. Furthermore, we tentatively assume that high threshold voltage transistors (hv) and low threshold voltage transistors (lv) have the same current weight.

[0077] First, in the LVS rule (layout and principle) Figure 1 In the consistency check rules, the four types of transistors mentioned above are created. When using calibre (a chip design verification tool) for extraction, the S / D area parameters can be calculated. Then, for each MOS connected to the power supply, its current I is equal to its S / D area (denoted as Area_mos) multiplied by the corresponding current weight k (denoted as k_mos), i.e., Formula 5: I = Area_mos * k_mos. From this formula, we can see that: 1) The larger the S / D area, the larger the current of the MOS. 2) The higher the current weight, the larger the current. 3) Different types of MOS transistors (N-type and P-type) have different current directions. Although the actual current is also related to the gate voltage and the potential at the other end, in simulations based solely on layout data, this method of calculating the current using I = Area_mos * k_mos is still somewhat relevant.

[0078] Secondly, a forced current constraint is added. According to Kirchhoff's first law (KCL, that is, the sum of the currents flowing into any node in a circuit is equal to the sum of the currents flowing out of the node), this is reflected here as Itotal = 0 (Equation 6). The purpose is to introduce a compensating current component into the current calculation so that the current relationship of the entire circuit conforms to the basic circuit laws.

[0079] Finally, by combining Equations 5 and 6 above, we can calculate the current to the power supply at the source / drain of each MOS. This involves a weighted calculation considering both the inherent characteristics of the MOS (the basic current component represented by I = Area_mos * k_mos) and the overall current constraint of the circuit (the compensation current component represented by Itotal = 0).

[0080] like Figure 3 As shown, Figure 3 This diagram shows the symmetrical current distribution of an NMOS transistor (0.05A-0.05A). There are two N-type MOS transistors (NMOS), both with an area of ​​1. The module port current is -0.1A (the negative sign indicates the current direction; for N-type, this is sink current, meaning current flows out of the module port). The current distribution for both NMOS transistors is 0.05A (because they have the same area, according to the previous current distribution formula, it is evenly distributed when the total current is constant), demonstrating the current distribution of the same type (N-type) MOS transistors with the same feature size (e.g., S / D area) under a specific port current.

[0081] like Figure 4 As shown, Figure 4 The diagram shows the asymmetric current distribution of an NMOS transistor (0.025A-0.075A). There are two N-type MOS transistors (NMOS), one with an area of ​​1 and the other with an area of ​​3. The module port current is also -0.1A. The NMOS with area 1 receives 0.025A of current, and the NMOS with area 3 receives 0.075A of current. This demonstrates that among N-type MOS transistors, the port current is distributed according to the ratio of their characteristic dimensions (areas) (1:3) (i.e., the total current -0.1A is distributed proportionally). This further reflects the influence of characteristic dimensions (areas) on current distribution. In other words, based on formula five, I = Area_mos * k_mos, when k is the same, the area determines the current magnitude.

[0082] like Figure 5 As shown, Figure 5The diagram shows the current distribution of an NMOS and PMOS combination (0.1A--0.1A). There are two N-type MOS transistors (NMOS, each with an area of ​​1) and one P-type MOS transistor (PMOS, with an area of ​​1). The module port current is 0.1A (N-type sink current is positive, P-type source current is negative; the overall port current is a combination of both). The current distribution for both NMOS transistors is 0.1A (sink current, flowing into the corresponding node), and the current distribution for the PMOS transistor is -0.1A (source current, flowing out of the corresponding node). The current distribution of different types (N-type and P-type) MOS transistors at the same port current demonstrates the influence of type (through current weight polarity) on the current direction and magnitude (combining formulas five and six above, with the same area, the different current weight polarities of N-type and P-type transistors lead to different current directions, and the simultaneous calculation satisfies Itotal = 0).

[0083] This application takes into account the combined influence of transistor feature size (area) and transistor type (current weight polarity) on current distribution. That is, when the port current is negative, the area of ​​the NMOS connected to the power supply is larger than that of the PMOS. Furthermore, under the same port current, the greater the difference in area between the NMOS and PMOS connected to the power supply, the smaller the node distribution current, thereby achieving optimization and control of current distribution.

[0084] The layout power analysis apparatus provided in this application is described below. The layout power analysis apparatus described below can be referred to in correspondence with the layout power analysis method described above.

[0085] On the other hand, such as Figure 6 As shown, this embodiment provides a layout power analysis device, including a feature extraction module 601, a current distribution module 602, and a simulation module 603.

[0086] For example, the parameter extraction module 601 is configured to extract the physical parameters of each device and the parasitic resistance parameters of the power network from the imported integrated circuit layout data.

[0087] For example, the current distribution module 602 is configured to calculate the current source-to-ground current distribution value of each device according to the physical parameters, and convert the topology of the power network into a circuit connection relationship netlist containing power nodes and ground nodes.

[0088] For example, the simulation module 603 is configured to replace each device with the corresponding current source to ground current distribution value and load the parasitic resistance parameters in the circuit connection relationship netlist, generate a simulation netlist, and then input it into the simulator to perform DC analysis to obtain the measured impedance voltage drop data of each power supply node.

[0089] Understandably, this application achieves accurate power network analysis in the early stages of layout design by replacing each device with the corresponding current source-to-ground current allocation value and loading the parasitic resistance parameters: the parameter extraction module directly parses the layout polygon data (such as diffusion regions / contact holes) and dynamically extracts transistor feature dimensions (such as W / L, S / D area) and metal trace geometry parameters that have not been verified by LVS; the current allocation module calculates the device current in real time based on physical parameters, transforming the transistor into a current source node with weighted characteristics; the simulation module constructs a simulation netlist that reflects both the real current load distribution and geometric parasitic effects by retaining the parasitic resistance network of the original layout and coupling it with the dynamic current source. This application breaks through the limitation of traditional processes that must wait for LVS to complete, and by simplifying the device model into a current source while maintaining the physical characteristics of the layout at the abstraction layer, it achieves IR Drop prediction accuracy in the early design stage and shortens the power integrity verification cycle.

[0090] This embodiment also provides a computer-readable storage medium having a computer program stored thereon, the computer program being loaded by a processor to execute the arrangement in any of the methods described above.

[0091] In the embodiments of this application, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0092] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0093] The above provides a detailed description of a layout power analysis method, apparatus, and storage medium provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A layout power analysis method, characterized in that, include: Extract the physical parameters of each device and the parasitic resistance parameters of the power network from the imported integrated circuit layout data; Calculate the current source-to-ground current distribution value of each device based on the physical parameters, and convert the topology of the power network into a circuit connection relationship net table containing power nodes and ground nodes; In the circuit connection netlist, each device is replaced with the corresponding current source to ground current distribution value and the parasitic resistance parameter is loaded. After generating the simulation netlist, it is input into the simulator to perform DC analysis and obtain the measured impedance voltage drop data of each power supply node.

2. The layout power analysis method according to claim 1, characterized in that, Also includes: Based on the measured impedance voltage drop data, perform at least one of the following verification operations: voltage compliance verification, power supply uniformity verification, and parameter matching verification.

3. The layout power analysis method according to claim 2, characterized in that, The voltage compliance verification includes: comparing the measured impedance voltage drop data of each power node with the rated voltage tolerance range of the corresponding process node to verify whether it meets the preset voltage integrity index. The uniformity verification includes: verifying whether the power supply uniformity of the power network meets the design specifications based on the spatial distribution characteristics of the impedance voltage drop data on the layout plane; The parameter matching verification includes: verifying the degree of matching between the power network parameter configuration and the device load by analyzing the correlation characteristics between impedance voltage drop and parasitic resistance parameters.

4. The layout power analysis method according to claim 1, characterized in that, The device includes a transistor; the physical parameters include: characteristic size parameters of the transistor, transistor type parameters, and transistor operating state parameters; wherein the characteristic size parameters are the aspect ratio or source-drain area of ​​the transistor, the transistor type parameters include N-type transistor, P-type transistor, or threshold voltage type, and the operating state parameters are on, off, or undefined state.

5. The layout power analysis method according to claim 4, characterized in that, The calculation of the current source-to-ground current distribution value of each transistor based on the physical parameters includes: The basic current component is established based on the product of the characteristic size parameter and the current weight of the transistor type; A compensation current component is introduced based on Kirchhoff's first law; The weighted synthesis calculation of the basic current component and the compensation current component is performed to output the total current distribution value.

6. The layout power analysis method according to claim 5, characterized in that, The current weights include: N-type transistors use a first current weight; P-type transistors use a second current weight; and high threshold voltage types use a third current weight.

7. The layout power analysis method according to claim 4, characterized in that, In the circuit connection netlist, replacing each transistor with the corresponding current source-to-ground current distribution value and loading the parasitic resistance parameters to generate the simulation netlist includes: The topology of the power network is abstracted into a graph structure that includes node coordinates and connection relationships; Assign the current source-to-ground allocation value to each node; Parasitic resistance parameters are calculated based on the geometric parameters and process resistivity of the metal traces.

8. The layout power analysis method according to claim 7, characterized in that, Also includes: When the layout and schematic consistency check is not completed, the aspect ratio or source-drain area of ​​the transistor is extracted from the layout polygon data as a feature size parameter. Based on a preset metal parameter table, parasitic resistance parameters are obtained through interpolation calculation.

9. A layout power analysis device, characterized in that, include: The parameter extraction module is configured to extract the physical parameters of each device and the parasitic resistance parameters of the power network from the imported integrated circuit layout data. The current distribution module is configured to calculate the current source-to-ground distribution value of each device based on the physical parameters, and convert the topology of the power network into a circuit connection relationship netlist containing power nodes and ground nodes. The simulation module is configured to replace each device with the corresponding current source-to-ground current distribution value and load the parasitic resistance parameters in the circuit connection relationship netlist, generate a simulation netlist, and then input it into the simulator to perform DC analysis to obtain the measured impedance voltage drop data of each power supply node.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which is loaded by a processor to perform the steps in the layout power analysis method according to any one of claims 1-8.

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