High-reliability groove type silicon carbide field effect transistor device and preparation process thereof

Abstract

The invention relates to a semiconductor device, in particular to a high-reliability groove-type silicon carbide field effect transistor device and a preparation process thereof.The device comprises drain electrode metal and an N-type drain electrode, an N-type epitaxial layer is arranged on the N-type drain electrode to serve as a drift region of the device, a longitudinal groove is formed in the upper surface of the N-type epitaxial layer, and an insulating medium is arranged in the longitudinal groove; the periphery of the longitudinal groove is wrapped by a P-type well region, the P-type well region is located in the N-type epitaxial layer, metal silicide is arranged at the bottom of the longitudinal groove, the metal silicide makes contact with the P-type well region and is further connected with grid metal, a heavily-doped N-type source electrode and source electrode metal are further arranged on the surface of the N-type epitaxial layer, the source electrode metal makes contact with the metal silicide located on the upper surface of the N-type source electrode, and the P-type well region is located in the N-type epitaxial layer. A P-type buried layer is further arranged in the N-type epitaxial layer, and the junction depth of the P-type buried layer is larger than that of the P-type well region. According to the invention, the pinch-off voltage of the device cannot be gradually increased along with the increase of the leakage voltage, and the stability of the device under various voltages is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, in particular to a high-reliability trench-type silicon carbide field effect transistor device and a preparation process thereof. BACKGROUND

[0002] As a third-generation semiconductor material, silicon carbide (SiC) has the advantages of wide band gap, high critical breakdown field and high saturation drift speed compared with the existing silicon material. The MOSFET device prepared by SiC material has the advantages of low on-resistance, small size and fast switching speed compared with the silicon-based MOSFET of the same voltage level.

[0003] The traditional trench-type junction field effect transistor has the risk of increasing pinch-off voltage under high voltage, and even in some cases, the device cannot be turned off, eventually leading to device burnout as the current continues to increase. SUMMARY

[0004] The purpose of the present application is to overcome the deficiencies in the prior art and provide a high-reliability trench-type silicon carbide field effect transistor device and a preparation process thereof. The high-reliability trench-type silicon carbide field effect transistor device provided by the present application aims to ensure that the pinch-off voltage of the device will not gradually rise with the increase of the drain voltage, improve the stability of the device under various voltages, and thus improve the reliability of the entire power system.

[0005] To achieve the above technical purposes, the technical solutions adopted by the embodiments of the present application are as follows: In a first aspect, the embodiments of the present application provide a high-reliability trench-type silicon carbide field effect transistor device, which comprises a drain metal and an N-type drain on the upper surface of the drain metal. An N-type epitaxial layer is provided on the N-type drain as a drift region of the device. A longitudinal trench is provided on the upper surface of the N-type epitaxial layer. An insulating medium is provided inside the longitudinal trench. The longitudinal trench is surrounded by a P-type well region. The P-type well region is located in the N-type epitaxial layer. A metal silicide is provided at the bottom of the longitudinal trench. The metal silicide is in contact with the P-type well region. The metal silicide is also connected with a gate metal. A heavily doped N-type source and a source metal are also provided on the surface of the N-type epitaxial layer. The source metal is in contact with the metal silicide on the upper surface of the N-type source. A P-type buried layer is also provided in the N-type epitaxial layer. The junction depth of the P-type buried layer is greater than the junction depth of the P-type well region.

[0006] Further, the doping concentration of the N-type drain is greater than the doping concentration of the N-type epitaxial layer. The doping concentration of the N-type drain is 1e18~1e22cm -3 The doping concentration of the N-type epitaxial layer is 1e12~1e17cm -3 .

[0007] Further, the doping concentration of the N-type source is 1e18~1e24cm -3 .

[0008] Further, the P-type buried layer is arranged in the N-type epitaxial layer between the longitudinal trenches, and the junction depth of the P-type buried layer is greater than the depth of the longitudinal trenches.

[0009] Further, the N-type epitaxial layer comprises an upper N-type epitaxial layer and a lower N-type epitaxial layer.

[0010] Further, the doping concentration of the upper N-type epitaxial layer is not less than the doping concentration of the lower N-type epitaxial layer.

[0011] In a second aspect, the present application provides a preparation process of the high-reliability trench-type silicon carbide field effect transistor device of the first aspect, comprising the following steps: Step one: selecting an N-type substrate material as an N-type drain, and epitaxially growing an N-type epitaxial layer on the upper surface of the N-type drain; Step two: using a mask, implanting P-type ions at an energy of 500keV~4MeV on the wafer surface to form a P-type buried layer; Step three: using a mask, implanting N-type ions on the wafer surface to form an N-type source; Step four: after removing the mask in step three, using a new mask to etch longitudinal trenches on the wafer surface; Step five: retaining the mask of the etched trenches in step four, performing angle and vertical implantation of P-type ions into the longitudinal trenches to form a P-type well region, then removing the mask, and subsequently performing high-temperature annealing at 1300~2000℃ to activate the implanted impurity ions; Step six: depositing an insulating medium on the wafer surface and in the longitudinal trenches, then using dry etching to etch away the insulating medium on the wafer surface and the bottom of the longitudinal trenches, and retaining the insulating medium on the sidewalls of the longitudinal trenches; Step seven: depositing metal, and performing high-temperature treatment at 500~1000℃ to make the metal react with the silicon carbide material on the bottom of the longitudinal trenches and the wafer surface to form metal silicide, and then removing the metal that does not react with silicon carbide by etching; Step eight: forming an insulating medium layer on the wafer surface, selectively etching the insulating medium layer on the wafer surface to form a contact hole, then depositing metal and selectively etching the metal to form a source metal, a gate metal, and a drain metal deposited on the back of the wafer.

[0012] In a third aspect, the present application provides a preparation process of the high-reliability trench-type silicon carbide field effect transistor device of the first aspect, comprising the following steps: Step S1, selecting N-type substrate material as N-type drain, and epitaxially growing lower N-type epitaxial layer on the upper surface of the N-type drain; Step S2, using mask plate to implant P-type ions on the wafer surface to form P-type buried layer, and continuing to epitaxially grow upper N-type epitaxial layer; Step S3, using mask plate to implant N-type ions on the wafer surface to form N-type source; Step S4, after removing the mask plate in step S3, using new mask plate to etch longitudinal trench on the wafer surface; Step S5, retaining the mask plate of step S4, performing inclined and vertical implantation of P-type ions into the longitudinal trench to form P-type well region, and then removing the mask plate, and then performing high-temperature annealing at 1300-2000 DEG C to activate the implanted impurity ions; Step S6, depositing insulating medium on the wafer surface and in the longitudinal trench, and then using dry etching to etch away the insulating medium on the wafer surface and the bottom of the longitudinal trench, and retaining the insulating medium on the sidewall of the longitudinal trench; Step S7, depositing metal, reacting the metal with the silicon carbide material on the bottom of the longitudinal trench and the wafer surface through high-temperature process to form metal silicide, and then removing the metal which does not react with silicon carbide through etching means; Step S8, forming insulating medium layer on the wafer surface, selectively etching the insulating medium layer on the wafer surface to form contact hole, and then depositing metal and selectively etching the metal to form source metal, gate metal, and depositing metal on the back of the wafer to form drain metal.

[0013] The technical scheme provided by the embodiment of the present application has the following beneficial effects: 1. The present application can improve the stability of pinch-off voltage of the trench-type silicon carbide field effect transistor device under different drain voltages, avoid the increase of pinch-off voltage of the device under high drain voltage, ensure the smooth turn-off of the device under high drain voltage, and improve the reliability of the power device.

[0014] 2. The trench-type silicon carbide field effect transistor device of the present application is additionally provided with P-type buried layer, which can assist in depleting the N-type epitaxial layer in the middle of the P-type well region, so that the concentration of this region can be appropriately increased to reduce the on-resistance of the device.

[0015] 3. The preparation process of the trench-type silicon carbide field effect transistor device of the present application is compatible with the existing process, and the manufacturing method is simple. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a cross-sectional view of a conventional trench-type silicon carbide field effect transistor device.

[0017] Figure 2is a cross-sectional view of a trench type silicon carbide field effect transistor device according to Embodiment 1 of the present application.

[0018] Figure 3 is a cross-sectional view of a trench type silicon carbide field effect transistor device according to Embodiment 2 of the present application.

[0019] Figure 4 is a cross-sectional view after forming a lower N-type epitaxial layer in Embodiment 1 of the present application.

[0020] Figure 5 is a cross-sectional view after forming a P-type buried layer and an upper N-type epitaxial layer in Embodiment 1 of the present application.

[0021] Figure 6 is a cross-sectional view after forming an N-type source in Embodiment 1 of the present application.

[0022] Figure 7 is a cross-sectional view after forming a longitudinal trench in Embodiment 1 of the present application.

[0023] Figure 8 is a cross-sectional view after forming a P-type well region and high temperature annealing in Embodiment 1 of the present application.

[0024] Figure 9 is a cross-sectional view after depositing an insulating medium and completing dry etching in Embodiment 1 of the present application.

[0025] Figure 10 is a cross-sectional view after forming a metal silicide in Embodiment 1 of the present application.

[0026] Figure 11 is a cross-sectional view after forming a P-type buried layer in Embodiment 2 of the present application.

[0027] BRIEF DESCRIPTION OF DRAWINGS DETAILED DESCRIPTION

[0028] In the description of the present application, it should be understood that the orientation words such as "inner", "outer", "upper", "lower", "left", "right" and the like indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Without being contrary, these orientation words do not indicate and imply that the indicated device or element must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the scope of protection of the present application.

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0030] Example 1 A high-reliability trench silicon carbide field-effect transistor device, such as Figure 2 As shown, the device includes a drain metal 9 and an N-type drain 8 located on the upper surface of the drain metal 9. An N-type epitaxial layer 3 is provided on the upper surface of the N-type drain 8 as a drift region of the device. A longitudinal trench 7 is provided on the upper surface of the N-type epitaxial layer 3. An insulating dielectric 6 is provided inside the longitudinal trench 7. The longitudinal trench 7 is surrounded by a P-type well region 4 located in the N-type epitaxial layer 3. A metal silicide 1 is also provided at the bottom of the longitudinal trench 7. The metal silicide 1 is in contact with the P-type well region 4 and is also connected to the gate metal. A heavily doped N-type source 2 is provided on the surface of the N-type epitaxial layer 3. A P-type buried layer 5 is also provided in the N-type epitaxial layer 3. The junction depth of the P-type buried layer 5 is greater than the junction depth of the P-type well region 4. A source metal 10 is also provided on the surface of the N-type epitaxial layer 3. The source metal 10 is in contact with the metal silicide 1 located on the upper surface of the N-type source 2.

[0031] The junction depth of the P-type buried layer 5 is 0.7~3.5μm, and the junction depth of the P-type well region 4 is 0.5~3.0μm.

[0032] The doping concentration of the N-type drain 8 is greater than that of the N-type epitaxial layer 3.

[0033] Specifically, the doping concentration of the N-type drain 8 is 1e18~1e22cm. -3 The doping concentration of the N-type epitaxial layer 3 is 1e12~1e17 cm⁻¹ -3 .

[0034] The doping concentration of the N-type source 2 is 1e18~1e24cm. -3 .

[0035] The P-type buried layer 5 is disposed in the N-type epitaxial layer 3 between the longitudinal trenches 7, and the depth of the P-type buried layer 5 is greater than the depth of the longitudinal trenches 7.

[0036] The N-type epitaxial layer 3 includes an upper N-type epitaxial layer 3b and a lower N-type epitaxial layer 3a. The P-type buried layer 5 is disposed in the upper N-type epitaxial layer 3b and / or the lower N-type epitaxial layer 3a.

[0037] To reduce the on-resistance of the device, the doping concentration of the upper N-type epitaxial layer 3b is higher than that of the lower N-type epitaxial layer 3a.

[0038] Specifically, the doping concentration of the upper N-type epitaxial layer 3b is 5e16~5e17cm. -3The doping concentration of the lower N-type epitaxial layer 3a is 1e¹⁵~5e¹⁶ cm⁻¹. -3 .

[0039] The fabrication process of the aforementioned high-reliability trench silicon carbide field-effect transistor device includes the following steps: Step 1: As Figure 4 As shown, an N-type substrate material is selected as the N-type drain 8, and a lower N-type epitaxial layer 3a is epitaxially grown on the upper surface of the N-type drain 8. Step Two: As Figure 5 As shown, using a mask, P-type ions are implanted on the wafer surface to form a P-type buried layer 5, and epitaxial growth is continued to form an upper N-type epitaxial layer 3b. The lower N-type epitaxial layer 3a and the upper N-type epitaxial layer 3b together constitute the N-type epitaxial layer 3. Step 3: As Figure 6 As shown, N-type ions are implanted on the wafer surface using a mask for N-type source 2 to form N-type source 2; Step Four: As Figure 7 As shown, after removing the mask in step three, a new mask 11 is used to etch longitudinal trenches 7 on the wafer surface. Step 5: As Figure 8 As shown, the mask 11 for etching the trench in step four is retained, and P-type ions are implanted into the trench at an angle and vertically to form a P-type well region 4. Then the mask 11 is removed, and high-temperature annealing is performed to activate the implanted impurity ions. For silicon carbide products, the annealing temperature is generally high, typically between 1300 and 2000℃.

[0040] Step Six: As Figure 9 As shown, insulating medium 6 is deposited on the wafer surface and in the trench, and then dry etching is used to etch away the insulating medium 6 on the wafer surface and the bottom of the longitudinal trench 7, while retaining the insulating medium 6 on the sidewall of the longitudinal trench 7. The insulating medium 6 uses silicon compounds, such as silicon oxide, silicon nitride, TEOS (Tetraethoxysilane), BPSG (Boro-phospho-silicate glass), USG (Undoped Silicate Glass), and other materials.

[0041] Step Seven: As Figure 10 As shown, metal is deposited, and through a high-temperature process (500~1000℃), the metal reacts with the silicon carbide material at the bottom of the longitudinal trench 7 and the wafer surface to form metal silicide 1. Then, the metal that did not react with silicon carbide is removed by etching. Metal silicide 1 includes substances such as titanium silicide, nickel silicide, and platinum silicide.

[0042] Step 8: As Figure 2 As shown, an insulating dielectric 6 is deposited on the wafer surface to form an insulating dielectric layer. The insulating dielectric 6 fills the longitudinal trench 7 and covers the wafer surface. The insulating dielectric layer on the wafer surface is selectively etched to form contact holes. Then, metal is deposited and selectively etched to form source metal 10 and gate metal. Metal is deposited on the back side of the wafer to form drain metal 9.

[0043] The metals used include W, Ti, TiN, Ni, Al, and Cu.

[0044] For silicon carbide devices, N-type doped regions are generally achieved by doping with nitrogen or phosphorus, while P-type doped regions are generally achieved by doping with aluminum or boron.

[0045] The above-mentioned field-effect transistor device is an N-type device. If the N-type region and the P-type region are interchanged, a P-type device can be formed.

[0046] Example 2 A high-reliability trench silicon carbide field-effect transistor device, such as Figure 3 As shown, the device includes a drain metal 9 and an N-type drain 8 located on the upper surface of the drain metal 9. An N-type epitaxial layer 3 is provided on the N-type drain 8 as the drift region of the device. The N-type epitaxial layer 3 consists of an upper N-type epitaxial layer 3b and a lower N-type epitaxial layer 3a. The doping concentration of the upper N-type epitaxial layer 3b is equal to that of the lower N-type epitaxial layer 3a. A longitudinal trench 7 is provided above the N-type epitaxial layer 3. An insulating dielectric 6 is provided inside the longitudinal trench 7, and the longitudinal trench 7 is surrounded by a P-type well region 4. 4 is located in the N-type epitaxial layer 3. The bottom of the longitudinal trench 7 is provided with metal silicide 1. The metal silicide 1 is in contact with the P-type well region 4. The metal silicide 1 in the longitudinal trench 7 is also connected to the gate metal. The surface of the N-type epitaxial layer 3 is also provided with a heavily doped N-type source 2. The lower N-type epitaxial layer 3a is also provided with a P-type buried layer 5. The junction depth of the P-type buried layer 5 is greater than the junction depth of the P-type well region 4. The surface of the N-type epitaxial layer 3 is also provided with a source metal 10. The source metal 10 is in contact with the metal silicide 1 located on the upper surface of the N-type source 2.

[0047] The junction depth of the P-type buried layer 5 is 0.7~3.5μm, and the junction depth of the P-type well region 4 is 0.5~3.0μm.

[0048] The doping concentrations of both the upper N-type epitaxial layer 3b and the lower N-type epitaxial layer 3a are 1e14~1e17 cm⁻¹. -3 .

[0049] The doping concentration of the N-type drain 8 is greater than that of the N-type epitaxial layer 3; Specifically, the doping concentration of the N-type drain 8 is 1e18~1e22cm.-3 The doping concentration of the N-type epitaxial layer 3 is 1e12~1e17 cm⁻¹ -3 .

[0050] The doping concentration of the N-type source 2 is 1e18~1e24cm. -3 .

[0051] Since the doping concentration of the upper N-type epitaxial layer 3b is equal to that of the lower N-type epitaxial layer 3a, the N-type epitaxial layer 3 can be formed by a single epitaxial growth, thus reducing the device manufacturing cost.

[0052] The fabrication process of the aforementioned high-reliability trench silicon carbide field-effect transistor device includes the following steps: Step 1: Select an N-type substrate material as the N-type drain 8, and epitaxially grow a lower N-type epitaxial layer 3a on the upper surface of the N-type drain 8; Step Two: As Figure 11 As shown, using a mask, P-type ions are implanted on the wafer surface using a high-energy implantation method to form a P-type buried layer 5, with an implantation energy of 500keV~4MeV; Step 3: Using the mask of N-type source 2, N-type ions are implanted on the wafer surface to form N-type source 2; Step 4: After removing the mask from Step 3, use the new mask 11 to etch longitudinal trenches 7 on the wafer surface; Step 5: Retain the mask 11 for etching the longitudinal trench 7 in Step 4, and implant P-type ions into the longitudinal trench 7 at an angle and vertically to form a P-type well region 4. Then remove the mask 11 and perform high-temperature annealing to activate the implanted impurity ions. For silicon carbide products, the annealing temperature is generally high, typically between 1300 and 2000℃.

[0053] Step 6: Deposit insulating medium 6 on the wafer surface and in the longitudinal trench 7, and then use dry etching to etch away the insulating medium 6 on the wafer surface and the bottom of the longitudinal trench 7, leaving the insulating medium 6 on the sidewall of the longitudinal trench 7. The insulating medium 6 is made of silicon compounds, such as silicon oxide, silicon nitride, TEOS, BPSG, USG and other materials.

[0054] Step 7: Deposit metal. Through a high-temperature process (500~1000℃), the metal reacts with the silicon carbide material at the bottom of the longitudinal trench 7 and on the wafer surface to form metal silicide 1. Then, the metal that did not react with the silicon carbide is removed by etching. Metal silicide 1 uses substances such as titanium silicide, nickel silicide, and platinum silicide.

[0055] Step 8: As Figure 3As shown, the insulating medium 6 is deposited on the wafer surface to form an insulating medium layer, the insulating medium 6 fills the longitudinal trench 7 and covers the wafer surface, the insulating medium layer on the wafer surface is selectively etched to form a contact hole, and then metal is deposited and selectively etched to form the source metal 10 and the gate metal. The metal is deposited on the back surface of the wafer to form the drain metal 9.

[0056] The metal is W, Ti, TiN, Ni, Al, Cu or the like.

[0057] Comparative example As Figure 1 is a conventional trench-type silicon carbide field effect transistor device, which comprises a drain metal 9 and an N-type drain 8 located on the upper surface of the drain metal 9, an N-type epitaxial layer 3 serving as a drift region of the device is arranged on the upper surface of the N-type drain 8, a longitudinal trench 7 is arranged above the N-type epitaxial layer 3, an insulating medium 6 is arranged inside the longitudinal trench 7, and the periphery of the longitudinal trench 7 is wrapped by a P-type well region 4, the P-type well region 4 is located in the N-type epitaxial layer 3, a metal silicide 1 is further arranged at the bottom of the longitudinal trench 7, the metal silicide 1 is in contact with the P-type well region 4, the metal silicide 1 inside the longitudinal trench 7 is further connected with the gate metal, a heavily doped N-type source 2 is further arranged on the surface of the N-type epitaxial layer 3, and a source metal 10 is further arranged on the surface of the N-type epitaxial layer 3, the source metal 10 is in contact with the N-type source 2.

[0058] The doping concentration of the N-type drain 8 is greater than the doping concentration of the N-type epitaxial layer 3; Specifically, the doping concentration of the N-type drain 8 is 1e18~1e22cm -3 , and the doping concentration of the N-type epitaxial layer 3 is 1e12~1e17cm -3 .

[0059] The doping concentration of the N-type source 2 is 1e18~1e24cm -3 .

[0060] For a field effect transistor, especially the junction field effect transistor of the present application, if the gate and the source are connected to the same potential and the drain voltage is higher than the source voltage, the device is turned on and the current flows from the source to the drain. If the voltage between the gate and the source is negative, when the voltage value is less than the pinch-off voltage of the device, the channel of the device is pinched off, and the transistor device is turned off.

[0061] For a conventional device, the device is pinched off by depleting the N-type epitaxial layer 3 between the P-type well region 4 and the P-type well region to pinch off the channel, the N-type epitaxial layer in the middle of the P-type well region 4 is pinched off, i.e. the current path is pinched off, at this time the device is in an off state.

[0062] When the drain voltage of the device is high, for power devices, the drain voltage can be greater than 1000V, at this time the P-type well region will preferentially deplete the N-type epitaxial layer under the longitudinal trench 7 to support the high drain voltage, in contrast, only less P-type well region and N-type epitaxial layer in the middle of the P-type well region 4 is depleted to pinch off the current path, so a higher gate-source voltage device is needed to pinch off, for example, when the drain voltage is 20V, the pinch-off voltage of the device is 10V, but if the drain voltage increases to 800V, the pinch-off voltage of the device can exceed 20V, in more severe cases, the device can not be able to pinch off the current and thus cannot be turned off.

[0063] For the present application, on the one hand, the floating P-type buried layer 5 can assist the depletion of the P-type well region 4 and the N-type epitaxial layer 3 in the middle of the P-type well region 4; on the other hand, when the drain voltage is high, the P-type buried layer 5 will also participate in the depletion of the N-type epitaxial layer 3 under the longitudinal trench 7 to support the high drain voltage. Therefore, the P-type buried layer 5 can reduce the influence of the N-type epitaxial layer 3 under the longitudinal trench 7 on the channel region (i.e. the N-type epitaxial layer 3 in the middle of the P-type well region 4) under high drain voltage, so that the pinch-off voltage of the device remains unchanged under different drain voltages, avoiding the phenomenon of the device not being able to be turned off under high drain voltage, and improving the reliability of the device and the power system.

[0064] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present application and not to limit it, although the present application has been described in detail with reference to examples, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

1. A high-reliability trench-type silicon carbide field effect transistor device, comprising a drain metal (9) and an N-type drain (8) on the upper surface of the drain metal (9), an N-type epitaxial layer (3) is provided on the upper surface of the N-type drain (8) as the drift region of the device, a longitudinal trench (7) is provided on the upper surface of the N-type epitaxial layer (3), an insulating medium (6) is provided inside the longitudinal trench (7), the peripheral part of the longitudinal trench (7) is wrapped by a P-type well region (4), the P-type well region (4) is located in the N-type epitaxial layer (3), a metal silicide (1) is provided at the bottom of the longitudinal trench (7), the metal silicide (1) is in contact with the P-type well region (4), the metal silicide (1) is also connected with the gate metal, the surface of the N-type epitaxial layer (3) is also provided with a heavily doped N-type source (2) and a source metal (10), the source metal (10) is in contact with the metal silicide (1) on the upper surface of the N-type source (2), characterized in that, The N-type epitaxial layer (3) is further provided with a P-type buried layer (5), and the junction depth of the P-type buried layer (5) is greater than the junction depth of the P-type well region (4).

2. The high-reliability trench-type silicon carbide field effect transistor device according to claim 1, characterized by, The doping concentration of the N-type drain (8) is greater than the doping concentration of the N-type epitaxial layer (3); The doping concentration of the N-type drain (8) is 1e18~1e22cm -3 The doping concentration of the N-type epitaxial layer (3) is 1e12~1e17cm -3 .

3. The high-reliability trench silicon carbide field effect transistor device of claim 1, wherein, The N-type source (2) has a doping concentration of 1e18~1e24cm -3 .

4. The high-reliability trench silicon carbide field effect transistor device of claim 1, wherein, The P-type buried layer (5) is disposed in the N-type epitaxial layer (3) between the longitudinal trenches (7), and the depth of the P-type buried layer (5) is greater than the depth of the longitudinal trenches (7).

5. The high-reliability trench silicon carbide field effect transistor device according to one of claims 1 to 4, characterized in that The N-type epitaxial layer (3) includes an upper N-type epitaxial layer (3b) and a lower N-type epitaxial layer (3a).

6. The high-reliability trench-type silicon carbide field effect transistor device according to claim 5, characterized by, The doping concentration of the upper N-type epitaxial layer (3b) is not lower than the doping concentration of the lower N-type epitaxial layer (3a).

7. The process for producing a high-reliability trench-type silicon carbide field effect transistor device as claimed in any one of claims 1 to 4, characterized by, Includes the following steps: Step 1: Select an N-type substrate material as the N-type drain (8), and grow an N-type epitaxial layer (3) on the upper surface of the N-type drain (8). Step 2: Using a mask, P-type ions are injected into the wafer surface at a high energy of 500keV~4MeV to form a P-type buried layer (5). Step 3: Using a mask, N-type ions are implanted on the wafer surface to form an N-type source (2); Step 4: After removing the mask from step 3, use the new mask (11) to etch longitudinal trenches (7) on the wafer surface. Step 5: Retain the mask (11) for etching the trench in Step 4, and implant P-type ions into the longitudinal trench (7) at an angle and vertically to form a P-type well region (4). Then remove the mask (11) and perform high-temperature annealing at 1300~2000℃ to activate the implanted impurity ions. Step 6: Deposit insulating medium (6) on the wafer surface and in the longitudinal trench (7), and then use dry etching to etch away the insulating medium (6) on the wafer surface and the bottom of the longitudinal trench (7), leaving the insulating medium (6) on the sidewall of the longitudinal trench (7). Step 7: Deposit metal, and treat it at a high temperature of 500~1000℃ to make the metal react with the silicon carbide material at the bottom of the longitudinal trench (7) and the wafer surface to form metal silicide (1). Then, remove the metal that has not reacted with silicon carbide by etching. Step 8: An insulating dielectric layer is formed on the surface of the wafer. The insulating dielectric layer on the surface of the wafer is selectively etched to form a contact hole. Then, metal is deposited and selectively etched to form source metal (10) and gate metal. Metal is deposited on the back side of the wafer to form drain metal (9).

8. The fabrication process of the high-reliability trench silicon carbide field-effect transistor device according to claim 5 or 6, characterized in that, Includes the following steps: Step S1: Select an N-type substrate material as the N-type drain (8), and grow a lower N-type epitaxial layer (3a) on the upper surface of the N-type drain (8). Step S2: Using a mask, P-type ions are implanted on the wafer surface to form a P-type buried layer (5), and epitaxial growth is continued to form an upper N-type epitaxial layer (3b). Step S3: Using a mask, N-type ions are implanted on the wafer surface to form an N-type source (2). Step S4: After removing the mask from step S3, use the new mask (11) to etch longitudinal trenches (7) on the wafer surface. Step S5: Retain the mask (11) from step S4, and inject P-type ions into the longitudinal trench (7) at an angle and vertically to form a P-type trap region (4). Then remove the mask (11) and perform high-temperature annealing at 1300~2000℃ to activate the injected impurity ions. Step S6: Deposit insulating medium (6) on the wafer surface and in the longitudinal trench (7), and then use dry etching to etch away the insulating medium (6) on the wafer surface and the bottom of the longitudinal trench (7), leaving the insulating medium (6) on the sidewall of the longitudinal trench (7). Step S7: Deposit metal. Through a high-temperature process, the metal reacts with the silicon carbide material at the bottom of the longitudinal trench (7) and on the wafer surface to form metal silicide (1). Then, the metal that did not react with the silicon carbide is removed by etching. Step S8: An insulating dielectric layer is formed on the surface of the wafer. The insulating dielectric layer on the surface of the wafer is selectively etched to form a contact hole. Then, metal is deposited and selectively etched to form source metal (10) and gate metal. Metal is deposited on the back side of the wafer to form drain metal (9).

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