Frequency conversion oscillation anti-interference system and interference signal acquisition method

Abstract

The invention discloses a variable-frequency oscillation anti-interference system and an interference signal acquisition method, and belongs to the technical field of charging piles. The system comprises a fluxgate current acquisition module, an edge jump catcher unit, an upward counter unit, a random number generator unit, a data comparator unit, a high-low level state latch unit, an arithmetic unit, a digital-to-analog conversion unit and a low-pass filter circuit. Time delay controlled by a random number is introduced in the switching process of forward and reverse charging of the magnetic core, so that the sampling phase of the system is randomized, and the fixed harmonic relation between the sampling frequency and an interference signal of a specific frequency band is broken, and therefore, low-frequency conducted interference of the frequency band of 15kHz-150kHz is effectively inhibited, and misoperation caused by the fact that the low-frequency conducted interference is misjudged as a direct-current leakage signal is avoided. According to the invention, the accuracy and reliability of residual current detection in high-interference environments such as automobile charging piles and photovoltaic power generation are obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of charging piles, more specifically, it relates to a variable-frequency oscillation anti-interference system and an interference signal acquisition method. BACKGROUND

[0002] As a charging pile in the field of automobile charging, a vehicle-mounted OBC, and a residual current protection device for photovoltaic power generation, etc., the use environment of the device is full of high-power radio frequency interference and low-frequency conducted wave interference. Sometimes the intensity of these interference wave signals is very high. After the interference wave enters the internal residual current detection sensor through conduction and radiation, it will cause collection errors due to the collection resolution of the sensor itself.

[0003] At present, the magnetic flux gate acquisition circuit used in most products on the market is a Smitt back difference oscillation circuit. The time ratio of the current flowing through the magnetic core coil after the magnetic core of the positive and negative two surfaces of the magnetic core is saturated is used to determine the measured current. The positive surface is collected immediately after the test, and the whole process is completed automatically by hardware. The conversion process has a fixed flip time. When the measured current is fixed, the coil oscillation frequency is also basically fixed. There is no time to stay between the flip and the retest. It is a continuous test mode. There is no problem in testing power frequency current and direct current. However, due to the limitations of the collection accuracy and the inherent oscillation frequency of the hardware, the collection frequency usually does not exceed 10KHZ. When low-frequency 1.5KHz~150KHZ, especially 15KHZ~150KHZ frequency band (such as high-power switching power supply), a large amplitude current interference wave is coupled or conducted to the sensor, the low collection resolution of the collection system itself will cause the collected interference signal to have a certain current amplitude and a single direction characteristic at some frequency points. Since the automobile charging pile generally follows the A+6 standard, that is, the effective value of 30mA A type + 6mA rectified wave action standard, when the interference signal current is large, such as 100mA 15KHZ~150KHZ frequency band, it can be determined by experiments that the collected current at some frequency points shows a single direction and has a smooth direct current characteristic with an amplitude of 8~16mA. Therefore, at these frequency points, the 6mA rectified wave judgment standard will trigger the direct current alarm and tripping action. However, it is not a power supply network power supply leakage or a direct current leakage. Therefore, customers often complain about the poor user experience. The user charges at night and finds that the electricity is not charged the next day, affecting normal travel and other complaints.

[0004] In the actual application process, after in-depth research, it is found that when the collection resolution is 2KHZ~10KHZ, the 15KHZ~150KHZ conducted interference signal will have an equivalent collection phenomenon. After thousands of experiments, a transformation scheme is finally found to solve the problem.

[0005] Low frequency interference phenomenon: The acquisition system collects sinusoidal signals several times or tens of times higher than its own resolution frequency, which will produce the situation as shown in the figure. Figure 1 As can be seen from the figure: Figure 1 Acquisition frequency 1: the frequency of the collected interference signal is 5 times the acquisition frequency of the acquisition system, and when the odd multiple is present, every interval of the collected signal will present the phenomenon of positive and negative phase inversion with the same amplitude, and after the subsequent low-frequency filtering, the interference signal will also be filtered out after the acquisition system acquires the pulse. Acquisition frequency 3: 5.5 times, showing a phenomenon of two positives and two negatives repeating, and after the subsequent low-frequency filter, the interference signal will also be filtered out. But acquisition frequency 2: the frequency of the collected interference signal is 6 times the acquisition frequency of the acquisition system, and the even multiple relationship is present, and every positive and negative dividing line is at the same phase point of the collected signal. When this dividing point is in the positive direction, the positive current will be continuously collected, and when this dividing point is in the negative direction, the negative current will be continuously collected. When the measured signal frequency remains unchanged for a long time (such as authentication test), even after the subsequent low-frequency filter, the collected current will still be positive or negative, and it will be in one direction, which is exactly the same as the smoothed direct current. In this case, as long as the filtered direct current reaches 6mA, it will inevitably lead to alarm tripping action. After repeated tests, the interference frequency of the low-frequency conducted signal acquisition to generate equivalent direct current is basically an integer multiple of the acquisition frequency or near the integer multiple, and it does not matter whether it is odd or even. When it is near the integer multiple, due to the phase of the interference coupling signal being ahead of or lagging behind the original oscillation signal phase, when the coupling signal is very strong, it will cause the coil oscillation frequency to deviate, and finally it will be locked to the oscillation frequency that presents an integer multiple relationship with the strong interference signal frequency.

[0006] Since the reason why the acquisition system interference signal frequency is an integer multiple of the acquisition interval frequency will produce equivalent smoothed direct current is that the acquisition system fixed oscillation frequency collects the same phase point of the interference signal, so a magnetic flux gate oscillation acquisition circuit that can randomly move the phase or transform the acquisition oscillation frequency can solve this problem.

[0007] Summary of the application In view of the deficiencies of the prior art, the purpose of the present application is to provide a system and method for converting low-frequency conducted interference signals by variable-frequency oscillation acquisition, which introduces a random delay time and phase shift frequency control mechanism to disrupt the phase sampling point of the interference signal during the acquisition process, realizes bidirectional symmetric acquisition of the signal, and effectively filters out low-frequency interference to realize high-precision direct current anti-interference acquisition.

[0008]

[0009] ​To achieve the above object, the present application provides the following technical solutions: A variable frequency oscillation anti-interference system comprises: A magnetic flux gate current acquisition module is configured to charge a magnetic core coil in a forward direction and a reverse direction to obtain a magnetic core saturation time; An edge jump capture unit is configured to detect a high-low level flip of a comparator output signal and output a trigger pulse; An up counter unit one is configured to start counting when the trigger pulse falls; A pulse width capture latch unit is configured to read a count value of the up counter unit one when the trigger pulse rises and lock the count value when the trigger pulse falls; A random number generator unit is configured to constantly generate a random data; A random number latch unit is configured to load the random data when the random number latch unit rises and lock the random data when the random number latch unit falls; An up counter unit two is configured to start counting when the trigger pulse falls and compare with the random number latch unit; A data comparator unit is configured to output a control pulse when the up counter unit two is equal to the random number latch unit; A high-low level state latch unit is configured to update a driving output state according to the control pulse to drive a coil oscillation circuit to realize phase shifting and variable frequency; An operator unit is configured to calculate a duty cycle based on the forward and reverse charging time and output to a digital-to-analog conversion unit; The digital-to-analog conversion unit is configured to convert the duty cycle result into an analog signal output; A low-pass filter circuit is configured to filter out interference signals and output a power frequency current signal or a direct current signal.

[0010] Further, the random number generator unit outputs a 16-bit random number, which is kept by the random number latch unit until the comparison is completed.

[0011] Further, the operator unit calculates the duty cycle based on the high-low level time and the period time with 12-bit precision.

[0012] Further, the magnetic flux gate current acquisition module comprises a forward driving circuit and a reverse driving circuit, which respectively provide a forward 4.6V driving voltage and a reverse 0.4V driving voltage.

[0013] A variable frequency oscillation anti-interference system for interference signal acquisition method comprises the following steps: Step 1: charging a magnetic core coil in a forward direction to obtain a magnetic core saturation time; Step 2: detecting a high-low level flip of a data comparator unit output level by an edge jump capture unit and outputting a trigger pulse; Step 3, at the rising edge of the trigger pulse, read and latch the forward charging saturation time; Step 4, at the falling edge of the trigger pulse, start counting the upward counter unit 2, and latch the random number generated by the random number generator unit; Step 5, compare the values of the upward counter unit 2 and the random number latch unit, and when they are equal, output a control pulse; Step 6, according to the control pulse, update the high-low level state latch output, drive the magnetic core coil into the reverse charging process; Step 7, repeat steps 2 to 6 to complete the reverse charging saturation time acquisition; Step 8, calculate the duty cycle of the forward and reverse charging time, and output an analog signal through digital-to-analog conversion; Step 9, low-pass filter the analog signal to obtain a power frequency current or DC signal output.

[0014] Further, the low-pass filtering step includes attenuating and filtering out interference signals higher than 800Hz.

[0015] Further, the method of the present application is suitable for effective acquisition of 50Hz, 60Hz power frequency current and DC current, while suppressing 15kHz~150kHz band interference.

[0016] Through the above technical solution, the present application has the following advantages: Random frequency phase shift sampling: by introducing a random delay time, the sampling phase point is randomly distributed, avoiding the equivalent DC misjudgment at integer multiple or adjacent integer multiple frequency points.

[0017] Strong anti-interference ability: can effectively filter out low-frequency conducted interference in the range of 15kHz~150kHz, and maintain the true response to power frequency and DC signals.

[0018] Flexible structure implementation: both discrete logic circuits and single-chip integrated implementations can be used, with low cost and strong versatility.

[0019] Stable signal output: output analog quantities through DAC and RC filter, which can directly drive the residual current detection module to control the protection relay.

[0020] High system reliability: symmetrical hardware structure, simple software control, strong anti-misoperation ability, suitable for high interference application scenarios such as automobile charging piles and photovoltaic inverters, especially in IEC62955 and IEC62752 application scenarios DC6mA, leakage protection item judgment. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1This is a schematic diagram of the waveform generated by a sinusoidal signal with a frequency higher than its own resolution.

[0022] Figure 2 A schematic diagram illustrating the timing control approach for delay-shifting frequency conversion acquisition to address low-frequency interference.

[0023] Figure 3 This is a schematic diagram of the time-delay phase-shift frequency conversion function module.

[0024] Figure 4 This is a schematic diagram to simulate the application scenario.

[0025] Figure 5 This is a schematic diagram of a fluxgate current acquisition and conversion module.

[0026] Figure 6 This is a schematic diagram of the analog signal output filtering circuit for the acquired results. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0029] To address the issue of timing control in oscillation circuits, this invention proposes the following concept: After the magnetic core undergoes forward and reverse charging tests to achieve magnetic saturation, a delay time is artificially inserted. This ensures that the start time of the next test is no longer determined by the oscillation circuit itself, but rather by a digital circuit generating a random delay time through a random time generator. This makes the test start time a random phase, offsetting the characteristics of in-phase acquisition, while simultaneously ensuring bidirectional symmetry in the acquired values. Figure 2 (The timing control approach for solving low-frequency interference through time-delayed phase-shifting frequency conversion acquisition) is shown below: Ta 1~Ta n, where odd numbers such as 1 and 3 represent the forward magnetization saturation time of the magnetic core, and even numbers such as 2 and 4 represent the reverse magnetization saturation time of the magnetic core.

[0030] Td 1'Tdn, odd numbers such as 1 and 3 indicate that a random delay time needs to be inserted after the magnetic core is saturated in the forward direction, while even numbers such as 2 and 4 indicate that a random delay time needs to be inserted after the magnetic core is saturated in the reverse direction.

[0031] Td1~Tdn, the random delay time is a random number, but the maximum time does not exceed 100uS. The purpose is to change the phase difference between the previous and subsequent acquisition scans so that each acquisition starts from a different phase point.

[0032] After random delayed acquisition, for interference signals with a scanning acquisition frequency several times higher, the acquisition results are uniformly dispersed in terms of positive and negative limits. After performing R-integral low-frequency filtering on the acquisition results, these interference signals can be filtered out.

[0033] Since the random delay time is controlled to a maximum of 100 seconds, the scanning interval can still be greater than 2KHz. When collecting 50Hz power frequency current, 40 points can still be scanned in one cycle. Therefore, the scanning result is still a 50Hz AC waveform current after low-frequency RC filtering. However, at scanning frequencies higher than 10KHz-150KHz, the scanning result is a dense point with extreme dispersion in both directions, which is almost zero after low-frequency RC filtering.

[0034] This invention relates to a method and system for acquiring and converting low-frequency conducted interference signals through frequency conversion oscillation to achieve DC anti-interference, which can be implemented through logic circuits or an MCU microcontroller. The system includes a time-delay phase-shift frequency conversion module, a fluxgate current acquisition and conversion module, an analog signal output module, and an external low-frequency filtering module.

[0035] like Figure 3 As shown, the delay-phase-shift frequency conversion module constitutes the core control logic of this invention, mainly including: an edge transition catcher unit, a pulse width capture latch unit, an up-counter unit one, an up-counter unit two, a random number generator unit, a random number latch unit, a data comparator unit, a high / low level state latch unit, an arithmetic unit, and a digital-to-analog converter (DAC) unit. This module uses a 48MHz clock source as its logic reference and completes closed-loop frequency conversion adjustment of signal sampling and delay control by detecting the high / low level transitions of the analog comparator output signal.

[0036] Edge transition capture unit: composed of 1 shift register (2 bits) + 1 XOR gate; specifically, 74HC164 (8 bits) shift register can be used, only QA and QB are used, CLEAR is fixed high; AB is connected as the input end of the (edge transition capture unit), CLOCK is connected to the 48MHZ system clock; the XOR gate chip can use 74HC86, only one group is used, 1A is connected to QA, 1B is connected to QB, and 1Y is connected as the output of the edge transition capture unit. Its working principle: the shift register is driven to shift once at one rising edge, when the input end of the shift register remains at a level state 1 or 0, after being driven by multiple 48MHZ system clocks, QA=QB, the XOR output is low, that is, the normal state of the (edge transition capture unit) is low; when the input end of the shift register suddenly changes, the 48MHZ system clock rising edge comes, QA first = input, at this time QA!=QB, the XOR gate output is high, that is, the (edge transition capture unit) output is high; when the 48MHZ system clock rising edge comes again, QB=QA=input, the XOR gate output is low, that is, the edge transition capture unit output returns to low, that is, only a high level time of one system clock period is output, achieving the purpose of input change and outputting a high level pulse. The edge transition capture unit is used to detect the high and low level transitions of the output of the analog comparator (VC1). When the transition from high to low or from low to high is detected, the edge transition capture unit outputs a pulse signal that is high first and then low. This pulse triggers the subsequent units to perform the actions: the pulse width capture latch reads the current count value of the counter one, the up counter two is cleared to prepare for random delay timing, and the random number generator generates a new random number and transmits it to the random number latch.

[0037] Pulse width capture latch unit: two groups of 16-bit D-latch (74HC75 chip can be used), one stores the high level time width, and one stores the low level time width. The selection of the two D-latch latch clock inputs is determined by the output level of the high and low level state latch unit. The selection of the D-latch is determined by the AND gate logic of the system clock and the input level. The pulse width capture latch unit is used to record the magnetic saturation time of the magnetic core coil in the forward or reverse charging phase. When the edge transition capture unit outputs the rising edge, the pulse width capture latch reads the value of the counter one, and judges whether it is in the forward or reverse charging phase according to the input level. When the falling edge of the edge capture pulse comes, the recorded count value is latched and kept stable for subsequent calculator to calculate the duty cycle.

[0038] Upward counter unit one and two: 16-bit counter (74HC161 counter), CP pin connected to 48MHz system clock, Q0~Q15 as output, each system clock rising edge plus 1, Q0 flip 2 times, Q1 flip 1 time, Q1 flip 2 times, Q2 flip 1 time, and so on, 16-bit from 0 to the next full 0, 2 to the power of 16. Counter one, zero at the beginning of each charging phase and start counting, used to record the time required for core saturation; counter two, start counting after the falling edge of the edge capture pulse, used to count the random delay time. The count result of counter two will be compared with the value of random number latch unit in real time, when the two are equal, output a comparison signal pulse as the end of delay time.

[0039] Random number generator unit and random number latch unit: random number generator unit is composed of linear feedback shift register (LFSR) or pseudo-random number generation circuit, internal register width is 16 bits, through polynomial feedback to achieve periodic pseudo-random number sequence; input is system clock (48MHz), output is 16-bit parallel random number. Random number latch unit is 16-way D-latch, one latch control pin LE (G), G=1 (high level): transparent mode, output Q follows input D. G from 1 to 0 (falling edge) Q latch unchanged. Its function is similar to 74HC75 chip, equivalent to 4 pieces of 74HC75 chip. Random number generator continuously generates 16-bit random number. Whenever the edge jump trigger unit outputs trigger, the random number latch unit synchronously saves the current random number value, forming a random delay target. Counter two starts counting after starting, when its count value is equal to the value in the random number latch, data comparator unit outputs control signal, realizing randomization of sampling starting phase. In this way, each sampling period has a random phase offset, so that when the interference frequency and the sampling frequency are even multiples, the sampling point is prevented from falling on the fixed phase, preventing the formation of equivalent DC signal.

[0040] Data comparator unit: it is 16-way data comparator, which can be expanded to 16-way by 74HC85 chip, when A1=B1, A2=B2... A16=B16, QA=B pin outputs high level, because high level only maintains one system clock period, so a 960 system clock delay counter is added, which restores low level after delay ends. Real-time comparison of counter two and random number latch value, when equal is detected, output a pulse from high to low, which triggers the following process: Clearing upward counter one, preparing for the next core charging test; Control high-low level state latch unit to update output state, realizing coil charging direction reversal; The control operator unit calculates the duty cycle of the last cycle and starts the DAC output.

[0041] High-low level state latch unit: the output of this unit directly drives the external coil oscillation circuit. When the data comparator output rises, the latch synchronizes the input level state to the output, thereby changing the coil charging direction: When the high level output, the coil performs forward charging; When the low level output, the coil performs reverse charging.

[0042] During the falling edge, the latch keeps the output unchanged, ensuring the stability of the charging process.

[0043] Operator unit: the operator calculates the ratio of the high level time of the latch to the cycle time, and the obtained duty cycle D value is represented by 12 bits of precision (0~4096). It represents the proportional relationship of the core saturation time in the current sampling period, and reflects the size and direction of the measured current. When the comparator pulse falls, the operation result is sent to the DAC module for digital-to-analog conversion.

[0044] Digital-to-analog conversion unit (DAC): the DAC module receives the duty cycle value output by the operator and converts it into an analog voltage signal output. The signal amplitude is proportional to the power frequency or direct current, representing the sampling result after anti-interference processing. Through the SPI interface, the positive and negative saturation time values of the core can be read at the same time, which is convenient for external digital system analysis.

[0045] As shown in Figure 5 , the fluxgate current acquisition conversion module is a back difference voltage controlled coil forward and reverse charging circuit, which includes a 1 / 2 VCC 2.5V reference driving power supply, a driving voltage amplitude conversion circuit, a comparison reference voltage amplitude conversion circuit and a magnetic saturation information acquisition unit.

[0046] 1 / 2 VCC 2.5V reference driving power supply: two 10K resistors R8 and R10 are connected in series to divide the 5V power supply to obtain a 2.5V weak driving reference voltage. The OPA2 operational amplifier drives this weak voltage to obtain a 2.5V reference power supply with a driving capacity of 20mA. This power supply is connected to the core coil 2 through a sampling resistor R13 to provide a stable midpoint driving voltage for it.

[0047] Drive voltage amplitude conversion circuit: R1, R2, and R7 are a low-current voltage conversion circuit for 5V to 4.6V and 0V to 0.4V. When 5V is input to the left side of R1, the equivalent circuit is R1 and R2 in parallel, then in series with R7. After voltage division, it is approximately 4.6V. After voltage following by the OPA1 op-amp, it achieves a high voltage drive capability of 20mA 4.6V. This is connected to pin 1 of the magnetic core coil, providing it with a forward charging voltage of 4.6V - 2.5V = 2.1V. When 0V is input to the left side of R1, the equivalent circuit is R1 and R7 in parallel, then in series with R2. After voltage division, it is approximately 0.4V. After voltage following by the OPA1 op-amp, it achieves a low voltage drive capability of 20mA 0.4V. This is connected to pin 1 of the magnetic core coil, providing it with a reverse charging voltage of 0.4V - 2.5V = -2.1V.

[0048] Magnetic saturation signal acquisition unit: The sampling resistor R13 and the magnetic core coil are connected in series to divide the charging drive voltage and form a charging hysteresis curve signal. After being filtered by the RC noise filtering circuit composed of R12 and C1, the signal is sent to the negative terminal of the comparator VC1.

[0049] The reference voltage amplitude conversion circuit consists of R4, R5, and R6, which are low-current voltage conversion circuits for 5V to 4.0V and 0V to 1.0V. When 5V is input to the upper side of R5, the equivalent circuit is R5 and R4 in parallel, then connected in series with R6. After voltage division, the voltage is approximately 4.0V, providing a 4.0V reference voltage for the positive input of comparator VC1. When 0V is input to the upper side of R5, the equivalent circuit is R5 and R6 in parallel, then connected in series with R4. After voltage division, the voltage is approximately 1.0V, providing a 1.0V reference voltage for the positive input of comparator VC1.

[0050] Forward charging phase: The process of testing the core saturation time during forward charging of the magnetic core coil, i.e. ( Figure 4 In the block diagram of the delay-phase-shift frequency converter, the (high / low level state latch unit) continuously outputs a high level when: The input voltage to the left side of R1 is 5V, which is supplied by... Figure 4, the 3-pin high-low level state latch in the delay phase shift frequency conversion function block diagram provides an output voltage, and outputs 5V when the high level is output, at which time OPA1 outputs a 4.6V charging voltage, and the forward input end of VC1 inputs a 4.0V comparison reference voltage. Since the magnetic core coil is just connected to the charging voltage, the coil current cannot be suddenly changed due to the inductive resistance, and is still small, and the voltage at both ends of the voltage dividing resistor R13 is very small, so the voltage reaching the reverse input end of VC1 through R12 is basically equal to the 2.5V voltage provided by OPA2. Since the forward input of VC1 is greater than the reverse input, the output of VC1 is 5V high level. After a period of charging of the magnetic core, the current gradually increases, and when the magnetic field strength reaches a critical point, the magnetic core reaches magnetic saturation, at which time the coil is close to a short circuit, and the voltage dividing at both ends of the coil is very small. The current at both ends of R13 reaches the saturation point current, and the voltage dividing is 2.5V provided by OPA2, which is higher than the 4.0V voltage at the forward input end of VC1, so the comparator VC1 flips to output 0V low level.

[0051] The edge jump capture unit captures the edge jump of the input signal: After the signal change of the VC1 output from high level to low level is sent to the signal input pin 1 of the delay phase shift frequency conversion function module, the edge jump of the input signal is captured by the edge jump capture unit, and then a pulse with high level first and low level second is output.

[0052] When the output is high (rising edge): ① The (pulse width capture latch unit) reads the count value of (upward counter unit 1), which represents the time value from the start of the charging of the magnetic core coil to the magnetic saturation point, and simultaneously obtains the level state before the flip through the input level of the phase shift frequency conversion function module pin, to determine whether the read time is the forward charging time or the reverse charging time. ② (Upward counter unit 2) is cleared, and is ready for timing counting of the random delay time.

[0053] ③ (Random number latch unit) synchronizes the random number value of (random number generator unit).

[0054] When the output is low (falling edge): ① The (pulse width capture latch unit) value is locked and not changed.

[0055] ② (Upward counter unit 2) starts counting.

[0056] ③ (Random number latch unit) locks the random number value and does not change.

[0057] When the low level is continuously output: The data comparator unit compares the values of the random number latch unit and the up counter unit, and generates a high-to-low pulse when the counter value and the random number latch value are equal, indicating the end of the delay time.

[0058] The data comparator unit generates a high-to-low pulse when the counter value and the random number latch value are equal.

[0059] When the output is high (rising edge): ① The up counter unit one clears the count value, preparing for measuring the reverse charging saturation time of the magnetic core.

[0060] ② The high-low level state latch unit updates the output value, i.e. updates the input level of the signal input pin 1 of the delay phase shift frequency conversion function module to the output pin 3. At this time, the input pin 1 is low, so the output pin changes from high to low, driving the external magnetic flux gate current acquisition conversion module. The voltage on the left side of the R1 resistor of the magnetic flux gate current acquisition conversion module is 0V. ③ The operator unit performs ratio calculation on the last stored high level time and the period of high level time + low level time stored in the pulse width capture latch unit according to the 12-bit mode 4096 start, and the calculation result is sent to the DAC module to convert into an analog voltage output at the falling edge.

[0061] When the output is low (falling edge): ① The up counter unit one starts counting, recording the time of the reverse charging of the magnetic core coil to the saturation point.

[0062] ② The high-low level state latch unit locks the output state, i.e. the voltage at this time is 0V.

[0063] ③ The operator unit sends the high-low level time duty cycle calculation value to the DAC module to convert into an analog voltage output.

[0064] Reverse charging phase: the process of testing the saturation time of the magnetic core by reverse charging the magnetic core coil, i.e. Figure 4 When the high-low level state latch unit in the delay phase shift frequency conversion function block continuously outputs low level: R1 left input 0V, this voltage is from Figure 4, the 3-pin high-low level state latch in the delay phase-shift frequency conversion function block diagram provides an output voltage, and outputs 0V when the output is low, at which time OPA1 outputs a charging voltage of 0.4V, and the forward input end of VC1 inputs a comparison reference voltage of 1.0V. Since the coil current cannot be abruptly changed and is very small due to the inductive resistance when the magnetic core coil is just connected to the charging voltage, the voltage across the voltage dividing resistor R13 is very small, and thus the voltage reaching the reverse input end of VC1 through R12 is substantially equal to the 2.5V voltage provided by OPA2. Since the forward input of VC1 is less than the reverse input, the output of VC1 is 0V low. After a period of reverse charging of the magnetic core, the current gradually increases, and the magnetic field strength reaches a critical point when the magnetic core reaches magnetic saturation. At this time, the coil is close to a short circuit, the voltage dividing across the coil is very small, the current across R13 reaches the saturation point, and the voltage dividing across the coil is 2.5V provided by OPA2, which is lower than the 1.0V voltage at the forward input end of VC1, so the comparator VC1 flips to output 5V high.

[0065] The edge jump capture unit captures the edge jump of the input signal: The signal change of the VC1 output from low to high is sent to Figure 4 After the signal input pin 1 of the delay phase-shift frequency conversion function block diagram is captured by the edge jump capture unit, a pulse that is high first and then low is output, When the output is high (rising edge): ① (the pulse width capture latch unit) reads the count value of (the up counter unit 1), which represents the time value from the start of the reverse charging of the magnetic core coil to the magnetic saturation point, and simultaneously determines whether the read time is the forward charging time or the reverse charging time through the flip level state of the one-pin input level before the flip. Figure 3 ② (the up counter unit 2) is cleared and is ready for the timing count of the random delay time.

[0066] ③ (the random number latch unit) synchronizes the random number value of (the random number generator unit).

[0067] When the output is low (falling edge): ① (the pulse width capture latch unit) value is locked and is not changed.

[0068] ② (the up counter unit 2) starts counting.

[0069] ③ (the random number latch unit) locks the random number value and is not changed.

[0070] When the output is continuously low: ​The data comparator unit compares the values of the random number latch unit and the up counter unit two, and generates a high-low pulse when the counter value and the random number latch value are equal, indicating the end of the delay time.

[0071] The data comparator unit generates a high-low pulse when the counter value and the random number latch value are equal.

[0072] When the output is high (rising edge): ① The up counter unit one is cleared, preparing for the measurement of the positive core charging saturation time.

[0073] ② The high-low level state latch unit updates the output value, i.e. updates the input level of the signal input pin 1 of the delay phase shift frequency conversion function module to the output pin 3. At this time, the input pin 1 is high, so the output pin changes from low to high, driving the external magnetic flux gate current acquisition conversion module, making the left side voltage of R1 resistor of the magnetic flux gate current acquisition conversion module 5V. ③ The operator unit calculates the ratio of the last stored high level time and (high level time + low level time) period in the pulse width capture latch unit according to the 12-bit mode 4096 start, and the calculation result is sent to the DAC module to convert into an analog voltage output at the falling edge.

[0074] When the output is low (falling edge): ① The up counter unit one starts counting, recording the time of the positive core coil charging to the saturation point.

[0075] ② The high-low level state latch unit locks the output state, i.e. the output voltage is 5V at this time.

[0076] ③ The operator unit sends the high-low level time duty cycle calculation value to the DAC module to convert into an analog voltage output.

[0077] Acquisition result output: Through the control process of testing the core saturation time by positive and negative core coil charging, the following is completed: after the positive core charging, saturation time test, positive saturation time reading, random time setting and delay, the high-low level duty cycle is calculated and output as an analog signal through the DAC; then the negative core charging is carried out, the saturation time test, the negative saturation time reading, the random time setting and the delay, the high-low level duty cycle is calculated and output as an analog signal through the DAC; finally, the positive core charging test is carried out again, and the cycle is repeated.

[0078] DAC output analog signal, after digital to analog, external voltage following and low frequency filtering are needed. The circuit filters out high frequency higher than 800Hz, and outputs the filtered power frequency current signal or DC signal. At the same time, the saturation time values of the positive and negative core charging can be read from the SPI interface.

[0079] Finally, when the acquisition system acquires low-frequency interference signals of 15KHZ~150KHZ, the original low-frequency interference will be disturbed due to the random delay of the acquisition process, and the phase point of the start acquisition will become discrete positive and negative almost symmetric current point data with a frequency equal to the acquisition system frequency. After RC integral filtering, these low-frequency interference signals can be basically filtered out. As for 50HZ, 60HZ and DC, the original frequency is low, and it belongs to the current caused by power supply. Since the acquisition system frequency is 2KHz~10KHz, the resolution of the power frequency acquisition is high, and the collected data still follows the waveform rule of the power frequency current, retaining the original characteristics.

[0080] In summary, the time delay phase shift frequency conversion acquisition system of the application realizes effective suppression of low-frequency high-amplitude conducted interference signals by introducing random phase and frequency conversion control in the magnetic flux gate acquisition structure.

[0081] The system structure is simple, stable and reliable, and is suitable for high-reliability leakage detection occasions such as automobile charging piles, vehicle-mounted OBCs, photovoltaic inverters and the like, can significantly reduce the misoperation rate, and improve user experience. The time delay phase shift frequency conversion function module of the application can also be replaced by only one ordinary MCU with a DAC and two counters, including the analog output application scene as shown in Figure 5 The analog output application scene as shown in

[0082] The above only describes the preferred embodiments of the application, and does not limit the application, and those skilled in the art can make usual changes and replacements within the technical scheme of the application, which should be included in the protection scope of the application.

Claims

1. A variable frequency oscillation anti-jamming system, characterized in that, The method comprises the following steps: a magnetic flux gate current acquisition module for forward and reverse charging of the magnetic core coil to obtain the magnetic core saturation time; an edge jump capture unit for detecting the high-low level flip of the analog comparator output signal and outputting a trigger pulse; an up counter unit one for starting counting at the falling edge of the trigger pulse; a pulse width capture latch unit for reading the counting value of the up counter unit one at the rising edge of the trigger pulse and locking the counting value at the falling edge; a random number generator unit for constantly generating a random data; a random number latch unit for loading the random data at the rising edge and locking the random data at the falling edge; an up counter unit two for starting counting at the falling edge of the trigger pulse and comparing with the random number latch unit; a data comparator unit for outputting a control pulse when the up counter unit two is equal to the random number latch unit; a high-low level state latch unit for updating the driving output state according to the control pulse to drive the coil oscillation circuit to realize phase shift and frequency conversion; an operator unit for calculating the duty cycle based on the forward and reverse charging time and outputting to a digital-to-analog conversion unit; a digital-to-analog conversion unit for converting the duty cycle result into an analog signal output; a low-pass filter circuit for filtering out interference signals and outputting a power frequency current signal or a direct current signal.

2. The variable frequency oscillation anti-jamming system according to claim 1, wherein, The random number generator unit outputs a 16-bit random number which is kept by the random number latch unit until the comparison is completed.

3. The variable frequency oscillation anti-jamming system of claim 1, wherein, The operator unit calculates the duty cycle with 12-bit precision based on the high-low level time and the period time.

4. The variable frequency oscillation anti-jamming system of claim 1, wherein, The magnetic flux gate current acquisition module comprises a forward driving circuit and a reverse driving circuit which respectively provide forward 4.6V and reverse 0.4V driving voltages.

5. The method for acquiring interference signals in a frequency conversion oscillation anti-interference system according to any one of claims 1-4, characterized in that, The method comprises the following steps: Step 1: forward charging of the magnetic core coil to obtain the magnetic core saturation time; Step 2: detecting the level flip of the data comparator unit output by the edge jump capture unit and outputting a trigger pulse; Step 3: reading and latching the forward charging saturation time at the rising edge of the trigger pulse and clearing the up counter unit two; Step 4: starting the up counter unit two counting at the falling edge of the trigger pulse and latching the random number generated by the random number generator unit; Step 5: comparing the values of the up counter unit two and the random number latch unit and outputting a control pulse when they are equal; Step 6: updating the high-low level state latch output according to the control pulse to drive the magnetic core coil into the reverse charging process; Step 7: repeating steps 2 to 6 to complete the reverse charging saturation time acquisition; Step 8: calculating the duty cycle from the forward and reverse charging time and outputting an analog signal through digital-to-analog conversion; Step 9: low-pass filtering the analog signal to obtain a power frequency current or a direct current signal output.

6. The method for acquiring interference signals in a frequency conversion oscillation anti-interference system according to claim 5, characterized in that, The low-pass filtering step comprises filtering out interference signals higher than 800Hz.

7. The method for acquiring interference signals in a frequency conversion oscillation anti-interference system according to claim 5, characterized in that, The method is suitable for effective acquisition of 50Hz, 60Hz power frequency current and direct current while suppressing interference in the frequency band of 15kHz-150kHz.

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