Register model construction method, system and equipment and storage medium
By constructing an initial register model of the register region to be tested in chip testing and configuring the adapter interface, the problem of high memory consumption in the prior art is solved, and efficient chip testing is achieved.
Patent Information
- Application Number
- CN202511368454.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-24
- Publication Date
- 2025-12-23
AI Technical Summary
Existing technologies increase memory consumption and reduce testing efficiency by instantiating all register regions in the chip during chip testing.
By obtaining the configuration files related to the register model, the register region to be tested is determined, an initial register model is constructed, and an adapter and direct programming interface are configured for it, avoiding the instantiation of all register regions.
It significantly reduces memory consumption, improves chip testing efficiency, and enhances the scalability, reusability, and configurability of registers.
Smart Images
Figure CN121189254A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and more specifically, to a register model construction method, system, device, and storage medium. Background Technology
[0002] During chip testing, hardware register simulations are typically copied to a verification environment using a register model. The test platform then performs read and write operations on the register model to verify the chip's functionality. However, during chip testing, the test platform may only need to test a portion of the register regions. Current technologies typically instantiate all register regions in the chip at once using scripts, leading to increased memory consumption and reduced chip testing efficiency. Summary of the Invention
[0003] In view of this, the purpose of the present invention is to provide a register model construction method, system, device and storage medium to solve the technical problems in the prior art.
[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a register model construction method, applied to a register model construction system, the method comprising: Obtain the configuration file related to the register model, and determine the register region to be tested from the configuration file; Construct an initial register model based on the aforementioned register region; The register model is obtained by configuring an adapter and a direct programming interface for the initial register model.
[0005] In an optional implementation, prior to the step of obtaining the register model-related configuration file, the method further includes: Add the register model construction system to the verification environment and determine whether there is chip verification configuration information corresponding to the verification environment; If it exists, the configuration file is generated based on the chip verification configuration information.
[0006] In an optional implementation, the step of constructing an initial register model based on the register region includes: Obtain the base address, name, and class name corresponding to the register region from the configuration file; The factory design pattern is invoked to construct the register initial model based on the base address, the name, and the class name.
[0007] In an optional implementation, after the step of constructing an initial register model based on the register region, the method further includes: Obtain the hardware interface corresponding to the register region from the configuration file; A hardware interface mapping relationship is generated according to the test requirements, and the address of the initial model of the register is mapped to the target address space according to the hardware interface mapping relationship.
[0008] In an optional implementation, the method further includes: Obtain the operation information corresponding to the initial model of the register and / or each operation record corresponding to the register model; Generate and print the corresponding operation sequence number, register status, address mapping, and register address for each operation record.
[0009] In an optional implementation, after obtaining the register model, the method further includes: Assign an address mapping to the register and obtain the root mapping information corresponding to the address mapping; If the root mapping information does not match the physical address of the register, then the register model is remapped.
[0010] In an optional implementation, the address remapping of the register model includes: Obtain the high-order bits of the physical address, generate a remapping configuration based on the high-order bits, and perform address remapping based on the remapping configuration.
[0011] Secondly, embodiments of the present invention provide a register model construction system, including: The configuration acquisition module is used to acquire configuration files related to the register model and determine the register region to be tested from the configuration files. The model building module is used to build an initial register model based on the register region; The model configuration module is used to configure the adapter and direct programming interface for the initial register model to obtain the register model.
[0012] Thirdly, embodiments of the present invention provide an electronic device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor can execute the machine-executable instructions to implement the register model construction method described in the first aspect.
[0013] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the register model construction method described in the first aspect.
[0014] This invention provides a register model construction method, system, device, and storage medium. The method determines the register region to be tested based on the register configuration file, then constructs an initial register model based on the register region to be tested, and configures a corresponding adapter and direct programming interface for the initial register model. This eliminates the need to instantiate all register regions, greatly reducing memory consumption and improving chip testing efficiency.
[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A block diagram of an electronic device provided by an embodiment of the present invention is shown; Figure 2 A flowchart illustrating a register model construction method provided by an embodiment of the present invention is shown; Figure 3 This diagram illustrates a structural schematic of a register model provided by an embodiment of the present invention. Figure 4 This diagram illustrates an address remapping principle according to an embodiment of the present invention. Figure 5 The diagram shows a functional module schematic of a register model construction system provided by an embodiment of the present invention.
[0018] Icons: 100 - Electronic device; 110 - Memory; 120 - Processor; 130 - Communication module; 500 - Register model building system; 501 - Configuration acquisition module; 502 - Model building module; 503 - Model configuration module. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0021] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0022] Please refer to Figure 1 This is a block diagram of an electronic device 100. The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, processor 120, and communication module 130 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.
[0023] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.
[0024] The processor 120 is used to read / write data or programs stored in the memory 110 and to perform corresponding functions.
[0025] The communication module 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through the network, and to send and receive data through the network.
[0026] It should be understood that, Figure 1 The structure shown is only a schematic diagram of the electronic device 100. The electronic device 100 may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.
[0027] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a register model construction method provided in this embodiment. The method is applied to a register model construction system and includes: S101. Obtain the configuration file related to the register model, and determine the register region to be tested from the configuration file.
[0028] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a register model provided in this embodiment.
[0029] The register model has three main levels: bit field, register, and block.
[0030] A reg can contain one or more fields, and a block can contain one or more regs or one or more blocks.
[0031] The configuration file for the register model can be generated according to the testing requirements. The format of the configuration file can be referred to Table 1.
[0032] Table 1
[0033] As shown in Table 1, master represents different hardware interfaces, and different hardware interfaces need to be connected to different adapters and drivers.
[0034] `address` represents the base address of the registers within the block.
[0035] block_name represents the name of the block, making it convenient to specify the block to be accessed when using functions.
[0036] `block_type` represents the type of the block, i.e., the class name. The classes used here are all generated by a script. In the example, `i3c_reg_block` is the class name of the block generated by the script, containing all registers within the i3c register.
[0037] For example, the first row of valid configurations in Table 1 indicates that the hardware interface represented by "AP" can access the i3c0 registers by accessing addresses starting at 0x200100000.
[0038] The configuration file allows you to determine the register region that needs to be tested, as well as the corresponding hardware interface.
[0039] S102. Construct an initial register model based on the register region.
[0040] The initial register model is constructed using information from the register regions and configuration files. The initial register model only contains the register regions that need to be tested.
[0041] S103. Configure the adapter and direct programming interface for the initial register model to obtain the register model.
[0042] The Direct Programming Interface (DPI) allows direct calling of C / C++ functions during testing, enabling hardware and software co-verification. The adapter, on the other hand, enables the test bus to perform test operations on the register model, allowing the register model to be tested normally.
[0043] This embodiment determines the register region to be tested based on the register configuration file, then constructs an initial register model based on the register region to be tested, and configures the corresponding adapter and direct programming interface for the initial register model. It does not require instantiation of all register regions, which greatly reduces memory consumption and improves the efficiency of chip testing.
[0044] In one implementation, prior to the step of obtaining the register model-related configuration file, the method further includes: Add the register model construction system to the verification environment and determine whether there is chip verification configuration information corresponding to the verification environment; If it exists, the configuration file is generated based on the chip verification configuration information.
[0045] When testing registers, they need to be adapted to the corresponding verification environment, which can be the actual working environment of the simulated chip.
[0046] For example, in different hardware or software environments, the chip's operating requirements may differ, and the corresponding test items may be different. Therefore, after adding the register model building system to the verification environment, it is also necessary to verify the chip configuration information corresponding to the verification environment. The chip verification configuration information can include the functions that the chip needs to be tested, and then the corresponding configuration file is generated based on the chip verification configuration information.
[0047] This embodiment obtains the chip verification configuration information corresponding to the verification environment, and then generates a configuration file based on the chip verification configuration information, providing data support for the subsequent construction of the register model.
[0048] In one implementation, the step of constructing an initial register model based on the register region includes: Obtain the base address, name, and class name corresponding to the register region from the configuration file; The factory design pattern is invoked to construct the register initial model based on the base address, the name, and the class name.
[0049] As shown in Table 1, since the chip may only need to test a portion of the items or functions, it is not necessary to instantiate all the register models corresponding to the chip. In this case, the register region can be determined according to the items or functions to be tested, and then the initial register model can be constructed according to the base address, name, and category of the register region.
[0050] When constructing the initial register model, the UVM Factory mechanism can be used. The Factory mechanism is a core mechanism based on the Factory Design Pattern, which can dynamically construct and replace object types without modifying the original code.
[0051] This embodiment generates the initial register model based on the register region, which reduces memory usage during testing and improves chip testing efficiency. Furthermore, by constructing the initial register model through factory-related patterns, the scalability, reusability, and configurability of the registers are improved.
[0052] In one implementation, after the step of constructing an initial register model based on the register region, the method further includes: Obtain the hardware interface corresponding to the register region from the configuration file; A hardware interface mapping relationship is generated according to the test requirements, and the address of the initial model of the register is mapped to the target address space according to the hardware interface mapping relationship.
[0053] Since the register model is a simulation copy of the chip, and each memory area of the chip itself is allocated a fixed physical address range, in order to test the register model, it is also necessary to map the address of the register model to the chip's physical address range, so that the test results of the register model can correspond to the chip itself.
[0054] In one embodiment, the method further includes: The target register is located from the register initial model based on the configuration information.
[0055] As shown in Table 1, when the register model to be constructed contains multiple configuration information entries, it indicates that multiple registers need to be instantiated in the register model. When it is necessary to configure or operate on register parameters, register lookup needs to be performed in the register model. At this time, register lookup can be performed using the following three lookup methods.
[0056] 1. When querying by register name reg, since register name reg does not carry blcok information, the query will directly search in all blocks or priority access blocks.
[0057] 2. To query by block name and register name block.reg, first determine which block the register to be queried is in, and then query within the block based on reg.
[0058] 3. By searching by address, you can directly find the register handle and address mapping information.
[0059] In one embodiment, the method further includes: Obtain the operation information corresponding to the initial model of the register and / or each operation record corresponding to the register model; Generate and print the corresponding operation sequence number, register status, address mapping, and register address for each operation record.
[0060] When performing test operations on the register model, each test operation usually generates a corresponding result, such as test success or test failure. In order to improve the readability of the test results, the test operation process of the register model can be printed according to the test procedure.
[0061] The printed content can include: the operation sequence number, status (start or end), address mapping (corresponding hardware interface), read / write, register hierarchical path information, register physical address, domain name, write or read value, etc. Printing the operation corresponding to the test operation as a readable log allows for quick fault location and improves debugging efficiency when the test fails or an exception occurs.
[0062] Please refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the address remapping principle provided in this embodiment.
[0063] In one implementation, after obtaining the register model, the method further includes: Assign an address mapping to the register and obtain the root mapping information corresponding to the address mapping; If the root mapping information does not match the physical address of the register, then the register model is remapped.
[0064] Root mapping information refers to the top-level, most original record in the address mapping system. It defines where an address range begins and ends, and which bus or physical memory it ultimately resides on. If the address issued by the CPU or bus recorded in the root mapping information does not match the actual physical address of the register inside the chip, then address remapping of the register model is required.
[0065] In one implementation, the address remapping of the register model includes: Obtain the high-order bits of the physical address, generate a remapping configuration based on the high-order bits, and perform address remapping based on the remapping configuration.
[0066] like Figure 4 As shown, when it is determined that the register model needs to be remapped, the physical address corresponding to the register can be obtained, and then the high-order bits of the physical address can be obtained. In a 32-bit address, the high-order bits of the physical address usually refer to the high 16 or high 18 bits, while in a 64-bit address, they generally refer to the high 32 bits.
[0067] Figure 4 This illustrates the address mapping process when the processor is a 32-bit processor and the physical address is 48 bits. In this case, we can check if the high 16 bits of the physical address are 0. If they are 0, no remapping is needed; otherwise, the high 18 bits are used to update the remapping configuration, and then address remapping is performed.
[0068] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of a register model construction system is given below. Please refer to [link / reference needed]. Figure 5 , Figure 5 This is a functional block diagram of a register model construction system provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the register model construction system provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. The register model construction system 500 includes: The configuration acquisition module 501 is used to acquire the configuration file related to the register model and determine the register region to be tested from the configuration file; Model building module 502 is used to build an initial register model based on the register region; The model configuration module 503 is used to configure the adapter and direct programming interface for the initial register model to obtain the register model.
[0069] Optionally, the above modules can be stored in the form of software or firmware. Figure 1 The memory shown is either stored in or embedded in the operating system (OS) of the electronic device, and can be used by... Figure 1 The processor executes the commands. Meanwhile, the data and program code required to execute these modules can be stored in memory.
[0070] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0071] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0072] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for constructing a register model, characterized in that, The method, applied to a register model construction system, includes: Obtain the configuration file related to the register model, and determine the register region to be tested from the configuration file; Construct an initial register model based on the aforementioned register region; The register model is obtained by configuring an adapter and a direct programming interface for the initial register model.
2. The register model construction method according to claim 1, characterized in that, Before the step of obtaining the configuration file related to the register model, the method further includes: Add the register model construction system to the verification environment and determine whether there is chip verification configuration information corresponding to the verification environment; If it exists, the configuration file is generated based on the chip verification configuration information.
3. The register model construction method according to claim 1, characterized in that, The step of constructing the initial register model based on the register region includes: Obtain the base address, name, and class name corresponding to the register region from the configuration file; The factory design pattern is invoked to construct the register initial model based on the base address, the name, and the class name.
4. The register model construction method according to claim 3, characterized in that, After the step of constructing the initial register model based on the register region, the method further includes: Obtain the hardware interface corresponding to the register region from the configuration file; A hardware interface mapping relationship is generated according to the test requirements, and the address of the initial model of the register is mapped to the target address space according to the hardware interface mapping relationship.
5. The register model construction method according to claim 1, characterized in that, The method further includes: Obtain the operation information corresponding to the initial model of the register and / or each operation record corresponding to the register model; Generate and print the corresponding operation sequence number, register status, address mapping, and register address for each operation record.
6. The register model construction method according to claim 1, characterized in that, After the step of obtaining the register model, the method further includes: Assign an address mapping to the register and obtain the root mapping information corresponding to the address mapping; If the root mapping information does not match the physical address of the register, then the register model is remapped.
7. The register model construction method according to claim 6, characterized in that, The step of remapping the address of the register model includes: Obtain the high-order bits of the physical address, generate a remapping configuration based on the high-order bits, and perform address remapping based on the remapping configuration.
8. A register model construction system, characterized in that, include: The configuration acquisition module is used to acquire configuration files related to the register model and determine the register region to be tested from the configuration files. The model building module is used to build an initial register model based on the register region; The model configuration module is used to configure the adapter and direct programming interface for the initial register model to obtain the register model.
9. An electronic device, characterized in that, It includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the register model construction method according to any one of claims 1-7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the register model construction method as described in any one of claims 1-7.