Depth information camera module and 3D sensing device

Abstract

The invention discloses a depth information camera module and a 3D sensing device, the depth information camera module comprises a packaging main body, a driving chip and a light source chip, the packaging main body is provided with a projection end, a circuit board is arranged in the projection end, the driving chip is coated with a packaging substrate, the packaging substrate and the light source chip are sequentially stacked on the side, close to an object, of the circuit board, and the light source chip is arranged in the packaging main body. The driving chip and the light source chip are connected through a plurality of first conductive circuits, the driving chip and the circuit board are connected through a second conductive circuit, and a first electronic element is arranged between the packaging substrate and the light source chip. Therefore, mutual inductance is greatly reduced, mutual inductance between parasitic inductors is reduced, inductance between capacitors and equivalent inductors is reduced, and even mutual inductance between resistors and equivalent inductors is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of light sensor, in particular to a depth information camera module and a 3D sensing device. BACKGROUND

[0002] In a 3D device of time-of-flight measurement, the principle of direct time-of-flight (D-ToF, hereinafter referred to as D-ToF) is to directly emit a light pulse, and then measure the time interval between the reflected light pulse and the emitted light pulse, that is, the time of flight of light. The 3D measurement device is an important device for space calculation, and its application on mobile terminals is becoming more and more widespread. The size requirement of the 3D measurement device is gradually developing in the direction of smaller volume and higher reliability.

[0003] Due to the fast speed of light, the receiving time in the D-ToF scheme is generally sub-nanosecond level, and D-ToF is usually used in a single-point ranging system and has fast measurement speed, so it is gradually favored by users. However, there are many interference factors in the implementation of a pixel-level sub-nanosecond electronic stopwatch, and the chip heating is a major influence.

[0004] The D-ToF chip usually adopts a SPAD chip. The SPAD chip is a device that can generate a response current within sub-nanosecond time. Its working principle is to use a reverse-biased photodiode to work in a very small voltage range beyond the breakdown voltage but not yet broken down. At this time, the diode is in a very sensitive working interval, so as long as there is a weak light signal, it can trigger an avalanche current, and the response speed is extremely fast.

[0005] However, the existing 3D measurement device has the following defects: since the 3D measurement device uses a power switch to work, when the power is turned on too much, it will cause waste of power consumption and excessive heating, increase the influence of the avalanche effect of the SPAD chip, and reduce the recognition accuracy of the receiving end. In addition, general electronic components, capacitors, resistors, and driving chips are packaged components, and the heat dissipation efficiency is generally not as high as that of molding materials. In addition, electronic components, capacitors, resistors, and driving chips are also prone to thermal drift phenomenon under heat, causing electronic signal interference. SUMMARY

[0006] An object of the present application is to provide a depth information camera module and a 3D sensing device capable of reducing the parasitic inductance of the projection end.

[0007] To achieve the above object, the technical scheme adopted by the present application is as follows: a depth information camera module, comprising a packaging main body, a driving chip and a light source chip, the packaging main body has a projection end, a circuit board is arranged in the projection end, the driving chip is coated with a packaging base, the packaging base and the light source chip are sequentially stacked and placed on the circuit board close to the object side, the driving chip and the light source chip are connected through a plurality of first conductive lines, the driving chip and the circuit board are connected through a second conductive line, and a first electronic element is arranged between the packaging base and the light source chip.

[0008] In some embodiments, at least one second electronic element is arranged on the circuit board, the conductive direction of the first electronic element is configured as a first direction, and the conductive direction of the second electronic element is configured as a second direction.

[0009] In some embodiments, the first electronic element is a power capacitor, and the second electronic element is a driving capacitor.

[0010] In some embodiments, the first electronic element is directly connected to the pins of the packaging base and the pins of the light source chip.

[0011] In some embodiments, the light source chip and the circuit board are connected through a third conductive line, the length of the first conductive line is less than the length of the second conductive line, the length of the first conductive line is less than the length of the third conductive line, the first conductive line includes a power line, and the length of the power line is less than the length of the remaining first conductive lines except the power line.

[0012] In some embodiments, at least part of each first conductive line is arranged in a vertical direction, and the length of the power line excluding the part arranged in the vertical direction is less than the length of the remaining first conductive lines excluding the part arranged in the vertical direction.

[0013] In some embodiments, a conductive layer is arranged in the packaging base, the conductive layer is provided with a conductive sphere close to one end of the circuit board, at least part of the conductive sphere is exposed outside the packaging base, a buffer medium is arranged between the packaging base and the circuit board, and the buffer medium is adapted to fill the gap formed between the packaging base and the circuit board for accommodating the conductive sphere.

[0014] In some embodiments, the packaging main body has a receiving end, the projection end and the receiving end are integrally formed, the projection end and the receiving end form a stepped structure close to the object side, and the relationship between the total length TTL-RX of the receiving end after installing the optical mechanism and the total length TTL-TX of the projection end after installing the optical mechanism satisfies the following formula:

[0015] 1.0 < TTL-RX / TTL-TX < 1.1.

[0016] In some embodiments, the total length of the optical system after the receiving end installs the optical mechanism is less than the total length of the optical system after the projection end installs the optical mechanism; a light transmission hole is formed on the receiving end, a photosensitive chip is arranged on the receiving end, the photosensitive chip is flip-chip arranged on the side of the light transmission hole away from the object, the circuit board is located on the side of the light transmission hole away from the object in the receiving end, the photosensitive chip is flip-chip arranged on the side of the circuit board away from the object, the circuit board and the photosensitive chip are connected through a solder pad, and a light blocking medium is arranged between the solder pad of the circuit board and the solder pad of the photosensitive chip.

[0017] A 3D sensing device comprising the depth information camera module.

[0018] Compared with the prior art, the beneficial effects of the present application are as follows:

[0019] 1. The depth information camera module and the 3D sensing device can increase the space for arranging electronic elements, make redundant design between electronic elements, reduce the parasitic inductance phenomenon between capacitor devices, thereby reducing the starting time, and further optimize the arrangement between the first electronic element and the second electronic element to reduce the mutual inductance phenomenon between capacitors.

[0020] 2. The depth information camera module and the 3D sensing device design the power line between the driving chip and the light source chip to be the shortest, so that the mutual inductance of the conductive circuit between the light source chip and the circuit board is small, and the light source chip is not easily affected by the conductive circuit between the circuit board. In addition, since the driving chip is a positive control circuit chip, it can control the light source chip to work according to a certain logic. After the control chip is calibrated, it is not easy to be affected by the outside world. Therefore, reducing the length of the circuit of the light source chip can greatly improve the influence of parasitic inductance at the light source chip, improve the starting time of the light source chip, and reduce the working power consumption of the chip at the projection end.

[0021] 3. The depth information camera module and the 3D sensing device can utilize the stacking structure to make the total length after the projection end installs the optical mechanism and the total length after the receiving end installs the optical mechanism close, and such basically flush optical surfaces can be more easily assembled into terminals, and make the distance between the projection end and the receiving end relative to the cover plate (such as the glass on the back of the mobile phone) of the terminal relatively compact, improving the space utilization. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1is a schematic diagram of the overall structure according to a preferred embodiment of the present application.

[0023] Figure 2 is a schematic diagram of the connection of the power line according to a preferred embodiment of the present application.

[0024] Figure 3 is a schematic diagram of the arrangement of the first electronic component according to a preferred embodiment of the present application.

[0025] Figure 4 is a schematic diagram of the arrangement of the first electronic component according to a preferred embodiment of the present application.

[0026] Figure 5 is a schematic diagram of the arrangement of the first and second electronic components according to a preferred embodiment of the present application.

[0027] Figure 6 is a schematic diagram of the arrangement of the conducting layer according to a preferred embodiment of the present application.

[0028] Figure 7 is a schematic diagram of the mold pressing during molding according to a preferred embodiment of the present application.

[0029] Figure 8 is a schematic diagram of the structure in which the package body is formed on both sides of the upper surface of the light source chip according to a preferred embodiment of the present application.

[0030] Figure 9 is a schematic diagram of the structure in which the package body is formed on both sides of the upper surface of the package substrate according to a preferred embodiment of the present application.

[0031] Figure 10 is a schematic diagram of the structure in which the light source chip and the package substrate are connected by bumps according to a preferred embodiment of the present application.

[0032] Figure 11 is a schematic diagram of the structure in which the light source chip and the package substrate are connected by silver paste according to a preferred embodiment of the present application.

[0033] Figure 12 is a schematic diagram of the structure in which the light source chip and the package substrate are connected by gold wires according to a preferred embodiment of the present application.

[0034] Figure 13 is a schematic diagram of the structure provided with a light blocking surface according to a preferred embodiment of the present application.

[0035] Figure 14 is a schematic diagram of the structure of the DOE element and the MOE element according to a preferred embodiment of the present application.

[0036] In the figure: 1, package main body; 11, projection end; 111, first electronic element; 112, second electronic element; 12, receiving end; 121, light passing hole; 13, circuit board; 14, light blocking medium; 15, light blocking surface; 2, driving chip; 3, light source chip; 31, power line; 32, first solder pad; 33, third solder pad; 34, bump ball; 35, silver glue; 36, gold wire; 37, metal base; 38, silver glue base; 4, package base; 41, conductive layer; 411, conductive sphere; 42, second solder pad; 43, fourth solder pad; 5, buffer medium; 6, mold; 61, feeding port; 62, discharging port; 7, optical mechanism; 8, photosensitive chip; 9, optical filter. DETAILED DESCRIPTION

[0037] Hereinafter, the present application will be further described in conjunction with specific embodiments, and it should be noted that the following described embodiments or technical features can be combined in any manner to form new embodiments without conflict.

[0038] In the description of the present application, it should be noted that for orientation words, such as the terms "center", "transverse", "longitudinal", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate the orientation and positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and cannot be understood as limiting the specific protection scope of the present application.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0040] The terms "include" and "have" and any variations thereof in the specification and claims of the present application are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] The present application will be further described below in conjunction with the drawings:

[0042] According to the characteristics of the SPAD chip, it can be known that the SPAD chip is prone to trigger counting by a single free electron in the avalanche region, thereby causing false counting, and the SPAD chip is greatly affected by dark noise. It is also found that the factors causing dark counting include free electrons generated inside the detector due to heat. This phenomenon occurs in SPAD chips manufactured through manufacturing processes and doping processes. Because the device has internal shockley-read-hall (SRH) defects, the ability to release and capture carriers is stronger. Therefore, under the cmos with a size of deep sub-micron (DSM), the voltage drop requires a higher doping concentration and a smaller PN junction size, which may lead to a higher defect density and a stronger accelerating electric field, making the dark counting effect more obvious. Therefore, in the D-TOF scheme, the problem of temperature sensitivity needs to be considered to reduce the influence of dark current, thereby reducing the dark current effect of the SPAD chip, i.e., the photosensitive chip.

[0043] Generally speaking, the wire can form an electrical system with other wires, the ground, and another part of itself, and sometimes it can form the structure of a flat capacitor. This parasitic in the circuit is difficult to compensate for by optimizing components, except for improving the lines of the electrical system. In addition, the current flowing through the wire will generate a magnetic field around the wire, which will affect itself and form self-induction, and also affect other wires to form mutual induction. Although the inductance of a straight wire is not as large as that of a coil, it is impossible to have no inductance, unless it is designed as an ideal straight wire without volume to avoid self-induction, and then it is placed in empty space to avoid mutual induction with any other system.

[0044] Simply put, there is parasitic inductance wherever there is wire, but the parasitic inductance carried by wires with different characteristics is different. For example, the parasitic inductance of a straight wire is definitely smaller than that of a coil-type wire. For example, when energized, the parasitic inductance of each line will affect the start time of energization. Especially when switching power works, each current change will be affected by parasitic inductance, thereby affecting the start and stop time of the circuit.

[0045] During the circuit's on and off processes, a smaller rise time (voltage rise time) results in a waveform closer to the ideal waveform. A straight up-and-down waveform represents the ideal operating mode. However, in reality, shortening the current loop between the driver chip and the light source chip directly reduces parasitic inductance. Parasitic inductance affects the rise edge of the laser waveform from the light source chip. A smaller rise edge is better for short-wavelength waveforms of a few nanoseconds, resulting in lower power consumption. To maintain the duty cycle, the current flow time needs to be set much longer than the required operating time. For example, ToF measurement requires a laser with a 1-second cycle and 0.5-second operation. In practice, to meet at least a 50% duty cycle, a laser with a 1-second cycle and 0.55-second operation may be required. Since the 3D sensing device in this application needs to operate continuously using a power switch, excessive power is applied each time, resulting in wasted power consumption and excessive heat generation.

[0046] Therefore, if the current loop between the driver chip and the light source chip can be reduced, thereby reducing parasitic inductance, the power-on time can be shortened, thus reducing power consumption and heat generation. In addition, due to the avalanche effect of the photosensitive chip, reducing heat dissipation can also increase the recognition accuracy of the receiver.

[0047] In the circuitry of a light source chip, a longer circuit design can increase parasitic inductance, thus delaying light emission. In a photosensitive chip, this can cause a delay in reception time. When calculating depth, this delayed reception time needs to be taken into account. This may require the photosensitive chip to be powered on earlier to receive the light signal. However, external signals are more likely to enter the photosensitive chip after power-on, causing signal interference and affecting depth recognition. It can also increase power consumption, thereby increasing heat generation. Heat generation can affect the dark current effect of the photosensitive chip and increase noise.

[0048] like Figures 1 to 14 As shown, this application provides a depth information camera module, including a package body 1, a driver chip 2 and a light source chip 3. The package body 1 has a projection end 11, and a circuit board 13 is disposed inside the projection end 11. The driver chip 2 is covered by a package substrate 4. The package substrate 4 and the light source chip 3 are stacked sequentially on the circuit board 13 near the object side.

[0049] Here, "object side" refers to the side closer to the object, which is generally the target of the light to be projected by the projection end 11.

[0050] When multiple chips are packaged in the same package body 1, the chips can be arranged horizontally on the circuit board or vertically stacked. Considering that the horizontal layout may result in an excessively large package size, this application chooses to arrange the driver chip 2 and the light source chip 3 in a vertical stacking manner. The vertical stacking of the driver chip 2 and the light source chip 3 can make the size smaller and the transmission path of electrical signals relatively shorter, thus making the electrical characteristics better.

[0051] In some embodiments, the upper surface area of ​​the packaging substrate 4 is larger than the area of ​​the light source chip 3, so that the stacked packaging body 1 can effectively support the light source chip 3, while also having enough space to facilitate circuit connection.

[0052] In some embodiments, the packaging body 1 encapsulates the circuit board 13, the packaging substrate 4 (including the driver chip 2), and the light source chip 3 by molding.

[0053] To reduce parasitic inductance in the circuit, the connection between driver chip 2, light source chip 3, and circuit board 13 is designed as follows:

[0054] The driver chip 2 and the light source chip 3 are connected by multiple first conductive lines. The first conductive lines include a power line 31. The length of the power line 31 is less than the length of the other first conductive lines. Since the inventors have found that the main factor affecting the rise time is the length of the power line 31 between the driver chip 2 and the light source chip 3, by reducing the length of the power line 31 between the driver chip 2 and the light source chip 3, the parasitic inductance in the circuit can be reduced, thereby improving the start-up time of the light source chip 3 and reducing the operating power consumption of the chip in the projection end 11.

[0055] The driver chip 2 and the circuit board 13 are connected by a second conductive line. The length of the first conductive line is less than the length of the second conductive line, which makes the mutual inductance between the light source chip 3 and the circuit board 13 relatively small. In other words, it makes the light source chip 3 less susceptible to the influence of the conductive line between it and the circuit board 13.

[0056] The light source chip 3 and the circuit board 13 are connected by a third conductive line. The length of the first conductive line is less than the length of the third conductive line, which makes the mutual inductance between the light source chip 3 and the circuit board 13 relatively small. In other words, the light source chip 3 is less affected by the conductive line between it and the circuit board 13. In addition, since the driver chip 2 is an active control circuit chip, it can control the light source chip 3 to work according to certain logic. That is to say, after the driver chip 2 is calibrated, it is not easily affected by external factors. Therefore, reducing the line length of the light source chip 3 can greatly improve the influence of the parasitic inductance of the light source chip 3.

[0057] In this application, the power line 31 of the light source chip 3 is connected to the driver chip 2, enabling the light source chip 3 to be controlled by the driver chip 2 and illuminated by the driver chip 2. By further designing the length of the power line 31, the power line 31 can be shorter than other first conductive lines between the driver chip 2 and the light source chip 3. Other first conductive lines include, but are not limited to, signal lines, drive lines, etc. The power line 31 can also be shorter than the second conductive line between the driver chip 2 and the circuit board 13, and the power line 31 can also be shorter than the third conductive line between the light source chip 3 and the circuit board 13. In summary, the power line 31 between the driver chip 2 and the light source chip 3 is designed to be the shortest line in the projection end 11, thereby effectively reducing parasitic inductance.

[0058] like Figures 3 to 4 In the embodiment shown, a first electronic component 111 is disposed between the packaging substrate 4 and the light source chip 3. Since capacitors are more prone to increasing parasitic inductance and the parasitic inductance of capacitors is also more difficult to eliminate, when the capacitor is as close as possible to the device and directly connected to the power supply pin, the parasitic inductance can be greatly reduced, thereby reducing the startup time. In this application, the first electronic component 111 is placed between the stacked structure of the packaging substrate 4 and the light source chip 3.

[0059] In some embodiments, the first electronic component 111 is directly connected to the pins of the package substrate 4 and the pins of the light source chip 3. This design can reduce the behavior of storing and dissipating electrical energy due to the presence of parasitic inductance along the traces. Just like a real inductor, at high frequencies, even the inductance of relatively short wires or PCB traces can be important. This solution can reduce the parasitic inductance caused by the increase in trace length and reduce the mutual inductance when the capacitor is powered on by the light source chip 3 when it is powered on by the power line 31 alone.

[0060] like Figure 5 In the illustrated embodiment, at least one second electronic component 112 is provided on the circuit board 13. The conductive direction of the first electronic component 111 is configured as a first direction, and the conductive direction of the second electronic component 112 is configured as a second direction. The capacitor can be equivalently regarded as a capacitor plate with pins connected to both sides. Since any conductor will increase inductance, pins are no exception. The longer the pin, the more inductance it brings. The parasitic impedance caused by the capacitor sometimes causes mutual inductance due to the routing method across different layers, which may increase the parasitic inductance. For example, if two PCB traces are distributed close to each other on the PCB, parasitic phenomena can easily occur, resulting in the existence of parasitic capacitance. This causes a rapid change in voltage on one trace to generate a current signal on the other trace. By setting the first electronic component 111 and the second electronic component 112 with intersecting directions, the mutual inductance phenomenon can be reduced.

[0061] In some embodiments, the first direction and the second direction are perpendicular to each other, and when the orientations of the capacitor plates in the first electronic component 111 and the second electronic component 112 are orthogonal, the induction phenomenon between charges is essentially eliminated.

[0062] It is understandable that if the packaging substrate 4 is considered as an isolation element, the packaging substrate generally has a height of 0.25-1.25mm. The height of the packaging substrate 4 is obviously thinner than the thickness (0.05-0.2mm) of a typical laminate like the circuit board 13. At least in the vertical direction, it plays a role in isolating other electronic components, and the isolation effect is much greater than the effect of placing electronic components on the front or back of the circuit board 13. In addition, from the perspective of the planar direction of the surface of the circuit board 13 in the prior art, the arrangement of electronic components is restricted to a plane, and the space is relatively compact. However, by setting the first electronic component 111 on the packaging substrate 4, this application can increase the space for arranging electronic components, and the electronic components can be redundantly designed, thereby greatly reducing the phenomenon of mutual inductance, thereby reducing the mutual inductance between parasitic inductances, reducing the inductance between equivalent capacitor inductances, and even reducing the mutual inductance between inductances due to resistance.

[0063] In some embodiments, the first electronic component is a power supply capacitor.

[0064] In some embodiments, the second electronic component is a driving capacitor.

[0065] like Figure 6 In the embodiment shown, a conductive layer 41 is provided inside the packaging substrate 4. Part of the conductive layer 41 is used to connect the light source chip 3 and the circuit board 13, and part of the conductive layer 41 is used to connect the driver chip 2 and the circuit board 13. A conductive ball 411 is provided at one end of the conductive layer 41 near the circuit board 13. At least part of the conductive ball 411 is exposed outside the packaging substrate 4. A buffer medium 5 is provided between the packaging substrate 4 and the circuit board 13. The buffer medium 5 is suitable for filling the gap formed between the packaging substrate 4 and the circuit board 13 that accommodates the conductive ball 411.

[0066] like Figure 6 In the embodiment shown, in the conductive layer 41 used to connect the driver chip 2 and the circuit board 13, since the driver chip 2 is packaged in the package substrate 4, the upper part of this conductive layer 41 can be directly connected to the driver chip 2. The lower part of the conductive layer 41 is provided with conductive spheres 411, and at least a portion of the conductive spheres 411 is exposed outside the package substrate 4.

[0067] like Figure 6In the embodiment shown, in the conductive layer 41 used to connect the light source chip 3 and the circuit board 13, since the light source chip 3 is located outside the package substrate 4, the upper part of this conductive layer 41 can be connected to the solder pads on the surface of the package substrate 4, and connected to the light source chip 3 through the solder pads. The lower part of the conductive layer 41 is provided with conductive spheres 411, and at least a portion of the conductive spheres 411 is exposed outside the package substrate 4.

[0068] When the package body 1 is formed, the driver chip 2 and the package substrate 4 need to be pressed together for forming. Therefore, the mold 6 will be pressed onto the package substrate 4. Specifically, the mold 6 will be pressed near the package substrate 4 on the non-light-emitting side of the light source chip 3. Due to the special nature of the package substrate 4, the conductive ball 411 on the bottom surface of the package substrate 4 needs to be electrically connected to the circuit board 13. Sometimes, some conductive connection medium, such as conductive silver paste, is added between the conductive ball 411 and the circuit board 13. However, since the conductive ball 411 is roughly curved, the height between the contact point with the circuit board 13 is different, which may cause the bonding strength between the package substrate 4 and the circuit board 13 to be low. This may cause the package substrate 4 to fall off the circuit board 13 during the molding process.

[0069] like Figure 7 As shown, when the encapsulation body 1 is formed, the mold 6 generally has an inlet 61 and an outlet 62. When the fluid material is injected into the mold 6, there will be a large flow rate and impact force. This transfer molding technology may cause a certain impact on the stacked structure at the encapsulation substrate 4, which may cause the encapsulation substrate 4 to fall off. In particular, the conductive ball 411 at the bottom of the encapsulation substrate 4 is prone to falling off.

[0070] Therefore, by setting a buffer medium 5 between the bottom of the packaging substrate 4 and the circuit board 13, the buffer medium 5 has a certain degree of flexibility and can resist some of the impact force of the material during molding, thereby reducing the risk of the packaging substrate 4 falling off.

[0071] In some embodiments, the buffer medium 5 is an insulating material.

[0072] In some embodiments, the buffer medium 5 is an adhesive material with a certain degree of flexibility, such as silicone. Silicone has a certain degree of flexibility and can resist the material impact force during the molding of the molding material, thereby reducing the risk of the encapsulation substrate 4 falling off.

[0073] like Figure 8 In the embodiment shown, a portion of the encapsulation body 1 is formed on both sides of the upper surface of the light source chip 3.

[0074] like Figure 9In the embodiment shown, the upper surface area of ​​the packaging substrate 4 is larger than the area of ​​the light source chip 3, so a part of the packaging body 1 can also be formed on both sides of the upper surface of the packaging substrate 4.

[0075] In some embodiments, regardless of whether a portion of the encapsulation body 1 is formed on both sides of the upper surface of the light source chip 3 or on both sides of the upper surface of the encapsulation substrate 4, this portion of the encapsulation body 1 gradually tilts away from the side closer to the light source chip 3 (or the encapsulation substrate 4) towards the side farther away from the light source chip 3 (or the encapsulation substrate 4), which can play a certain role in reducing stray light.

[0076] It is worth noting that the structure of the package body 1 formed on both sides of the upper surface of the light source chip 3 (or on both sides of the upper surface of the package substrate 4) has sufficient top surface area to support the optical mechanism 7 mounted on the projection end 11.

[0077] like Figure 10 In the illustrated embodiment, a first solder pad 32 is provided on the lower surface of the light source chip 3, and a second solder pad 42 is provided on the upper surface of the package substrate 4. The first solder pad 32 and the second solder pad 42 are connected by a bump ball 34. The light source chip 3 and the package substrate 4 are connected by a bump soldering process, which can effectively shorten the circuit length between the light source chip 3 and the driver chip 2. In the height direction, preferably between the first solder pad 32 at the bottom of the light source chip 3 and the second solder pad 42 at the top of the package substrate 4, a bump ball 34 is formed between the two solder pads as a conduction process, which can greatly shorten the line length between the light source chip 3 and the driver chip 2, thereby reducing the length of the power line 31 of the light source chip 3 and reducing the influence of parasitic inductance related to power-on.

[0078] like Figure 11 In the embodiment shown, a third solder pad 33 is provided on the lower surface of the light source chip 3, and a fourth solder pad 43 is provided on the upper surface of the packaging substrate 4. The third solder pad 33 and the fourth solder pad 43 are connected by silver paste 35. The design concept of this design is the same as that of the embodiment using bump ball 34 for connection, which can also effectively shorten the circuit length between the light source chip 3 and the driver chip 2.

[0079] like Figure 10 and 11 In the embodiment shown, at least a portion of each first conductive line is arranged in a straight line along the vertical direction. Since the gold wire 36 has a certain curvature in the conventional connection method, the length of the first conductive line will increase. By optimizing the arrangement of the first conductive lines, each first conductive line can be arranged as short as possible without affecting the structure of the light source chip 3, thereby reducing the delayed lighting phenomenon caused by parasitic inductance.

[0080] In some embodiments, based on the technical requirement of arranging the power line 31 to be as short as possible, and assuming that the lengths of all the first conductive lines in the vertical direction are substantially the same, it can be concluded that the length of the power line 31 excluding the portion arranged in a straight line in the vertical direction is less than the length of the remaining first conductive lines excluding the portion arranged in a straight line in the vertical direction, which can effectively reduce the generation of parasitic inductance.

[0081] like Figure 10 and 11 In the embodiment shown, as the most preferred arrangement, at least a portion of each first conductive line is arranged in a straight line in the vertical direction, and at least a portion of each first conductive line is arranged in a straight line in the horizontal direction. The length of the power line 31 in the horizontal direction is less than the length of the remaining first conductive lines 31 in the horizontal direction.

[0082] like Figure 10 and Figure 11 As can be seen from the image, the lateral length between the left conductive line (power line 31) and the light source chip 3 (located at the top) is smaller than the lateral length between the right conductive line and the light source chip 3.

[0083] like Figure 12 In the illustrated embodiment, the light source chip 3 and the packaging substrate 4 are connected by gold wire 36, which can maximize the light emission efficiency of the light source chip 3. The low resistance conduction method of gold wire 36 can reduce the influence of high frequency signals and further improve the light emission efficiency of the light source chip 3. In addition, since the packaging substrate 4 also affects the start-up time of the light source chip 3, it may also increase the start-up time of the light source chip 3 when it is powered on. Therefore, in this application, the packaging substrate 4 and the circuit board 13 can be connected by gold wire 36.

[0084] like Figure 1 , 6 In the embodiments shown in 12, a metal substrate 37 is provided between the packaging substrate 4 and the light source chip 3. The metal substrate 37 can reduce the temperature of the light source chip 3 on the one hand, and maintain the sealing effect between the light source chip 3 and the packaging substrate 4 on the other hand.

[0085] In some embodiments, the upper surface area of ​​the encapsulation substrate 4 is larger than the contact area between the metal substrate 37 and the encapsulation substrate 4, so that the encapsulation substrate 4 can effectively support the metal substrate 37 and also enable circuit connection.

[0086] In some embodiments, the area of ​​the upper surface of the metal substrate 37 is not less than the area of ​​the light source chip 3, so that the metal substrate 37 can effectively support the light source chip 3. It is worth noting that in this case, the light source chip 3 and the packaging substrate 4 are preferably connected by gold wires 36. The gold wires 36 can be connected from the upper surface of the light source chip 3 without interfering with the setting of the metal substrate 37.

[0087] In some embodiments, the metal substrate 37 also has a certain degree of elasticity. Since the packaging body 1 may be subjected to large external stress during the molding process, although this may not pose a significant risk when it is a single chip, in reality, after the chips are stacked, as the number of connection contact points between the chips increases and the number of structural support surfaces between the chips increases, the contact points between the chips may detach during molding, resulting in the risk of chip structure damage. Generally speaking, during the stacking process of the light source chip 3 and the packaging substrate 4, the chip may bend or warp when it is pressed. Therefore, the elasticity of the metal substrate 37 can provide a certain buffering effect during the molding process of the depth information camera module of this application.

[0088] like Figure 10 and 11 In the embodiment shown, a silver paste substrate 38 is provided between the packaging substrate 4 and the light source chip 3. Since the silver paste also contains organic materials and silver materials, it meets the packaging requirements of this application and has sealing and a certain buffering effect. The silver paste can be the conductive silver paste commonly used in the camera module industry. It is worth noting that in this case, the light source chip 3 and the packaging substrate 4 are preferably connected using a bump soldering process or a conductive silver paste process.

[0089] In some embodiments, the encapsulation body 1 has a receiving end 12, the projection end 11 and the receiving end 12 are integrally formed, and the projection end 11 and the receiving end 12 form a stepped structure on the side near the object. Specifically, the stepped structure is formed by the difference in height caused by the upper surface of the projection end 11 being higher than the upper surface of the receiving end 12.

[0090] It is worth noting that the top surface area of ​​the encapsulation body 1 at the receiver 12 (the lower side of the stepped structure) needs to be set to be sufficient to support the optical mechanism 7 mounted on the receiver 12.

[0091] like Figure 13 In the illustrated embodiment, the relationship between the total length TTL-RX of the receiver 12 after installing the optical mechanism 7 and the total length TTL-TX of the projector 11 after installing the optical mechanism 7 satisfies the following equation:

[0092] 1.0 < TTL-RX / TTL-TX < 1.1.

[0093] Since the projection end 11 has a larger structure, its volume is usually larger than that of the receiver end 12. In this application, by stacking the light source chip 3 and the driver chip 2 of the projection end 11, the length of the projection end 11 can be shortened, so that the total length of the projection end 11 after installing the optical mechanism 7 can be close to the total length of the receiver end 12 after installing the optical mechanism 7, thereby satisfying the range of 1.0 < TTL-RX / TTL-TX < 1.1. The optical surface structure of the projection end 11 and the receiver end 12 being basically flush can be more easily assembled into the terminal. At the same time, the flush optical surface structure can make the distance between the projection end 11 and the receiver end 12 relative to the cover plate on the terminal (such as the glass on the back of the mobile phone) relatively compact.

[0094] The total length of the projection end 11 after the optical mechanism 7 is installed refers to the distance between the end face of the lens (optical element in the optical mechanism 7) and the bottom of the projection end 11, and the total length of the receiving end 12 after the optical mechanism 7 is installed refers to the distance between the end face of the lens (optical element in the optical mechanism 7) and the bottom of the receiving end 12.

[0095] like Figure 13 In the illustrated embodiment, the total length of the optical system after the optical mechanism 7 is installed on the receiving end 12 is less than the total length of the optical system after the optical mechanism 7 is installed on the projection end 11. The total length of the optical system after the optical mechanism 7 is installed on the receiving end 12 is the distance between the end face of the lens (optical element) and the image plane (photosensitive chip 8). The total length of the optical system after the optical mechanism 7 is installed on the projection end 11 is the distance between the end face of the lens (optical element) and the image plane (light source chip 3). This design can meet the integrated packaging requirements of this application and improve the performance of the projection end 11 and the receiving end 12.

[0096] like Figure 13 In the illustrated embodiment, a light-transmitting hole 121 is provided on the receiving end 12, and a photosensitive chip 8 is disposed on the receiving end 12. The photosensitive chip 8 is flip-mounted on the side of the light-transmitting hole 121 away from the object side. Light reflected from the object can pass through the light-transmitting hole 121 from above and enter the photosensitive chip 8 on the side of the light-transmitting hole 121 away from the object side. The flip-mounted design of the photosensitive chip 8 can increase the distance of light reflection to the photosensitive chip 8, so that the height of the molded base of the receiving end 12 can be made smaller within the recognition accuracy range of the photosensitive chip 8, thereby increasing the length of the lens, increasing the optical design margin of the lens, increasing the design freedom of the lens, thereby improving the optical performance of the lens, and achieving effects such as higher depth recognition accuracy of the lens.

[0097] like Figure 13In the illustrated embodiment, the circuit board 13 is located in the receiver 12 on the side away from the object side of the light-transmitting hole 121. The photosensitive chip 8 is flip-chip disposed on the side of the circuit board 13 away from the object side. The circuit board 13 and the photosensitive chip 8 are connected by solder pads. Typically, the thermal conductivity of the molding material is about 2 W / mK, the thermal conductivity of the PCB is 0.3 W / mK, and the thermal conductivity of the chip is 120 W / mK. In this application, the thermal conductivity of the metal substrate 37 is approximately 100 W / mK. The photosensitive chip 8 can be thermally connected by solder pads disposed around the periphery of the photosensitive chip 8, thereby meeting the heat dissipation requirements of the package stack structure.

[0098] like Figure 13 In the embodiment shown, the filter 9 is located inside the light-transmitting hole 121 and is disposed on the side of the circuit board 13 near the object side. This allows for full utilization of the space on both sides of the circuit board 13 to accommodate, support, and fix the filter 9 and the photosensitive chip 8, thereby improving the structural compactness.

[0099] In some embodiments, the filter 9 is directly contacted and fixed to the circuit board 13, which enables the filter 9 to be positioned by the circuit board 13, thereby improving structural stability.

[0100] like Figure 13 In the embodiment shown, the circuit board 13 and the photosensitive chip 8 are connected by solder pads. A light-blocking medium 14 is provided between the solder pads of the circuit board 13 and the solder pads of the photosensitive chip 8. The light-blocking medium 14 can be a material that can absorb light, such as black or dark-colored glue, which can effectively reduce the stray light that may be caused by the soldering process between the solder pads of the photosensitive chip 8 and the solder pads of the circuit board 13.

[0101] like Figure 13 In the embodiment shown, the receiver 12 has a light-blocking surface 15 on the object side of the light-transmitting hole 121. The light-blocking surface 15 is arranged at an angle and faces the optical mechanism 7 installed on the receiver 12. The light-blocking surface 15 can effectively reduce stray light and improve the recognition accuracy of the photosensitive chip 8.

[0102] like Figure 13 In the embodiment shown, the thickness of the encapsulation body 1 formed on the side of the circuit board 13 away from the object side needs to be greater than the thickness of the structure at the photosensitive chip 8, so that the encapsulation body 1 can protect the structure at the photosensitive chip 8 and improve the structural stability.

[0103] In some embodiments, the optical mechanisms 7 mounted on both the projection end 11 and the receiving end 12 employ metalenses. In the prior art, the projection end 11 generally employs a vertically oriented DOE element (refer to...). Figure 11The element located at the top of the image modulates the wavefront by varying the optical path length of light due to the different thicknesses at different positions of the element, thereby achieving optical phase modulation. Both the projection end 11 and the receiving end 12 in this application employ MOE (meta-lens) elements (see reference). Figure 11 The component located at the bottom of the optical mechanism 7 has a lower thickness than the DOE component. By optimizing the components used in the optical mechanism 7, the overall thickness of the optical mechanism 7 is reduced, thereby reducing and controlling the thickness of the package stack structure.

[0104] Metalenses typically have unit structures on the order of half a wavelength, or hundreds of nanometers, with a constant thickness. However, the lateral nanostructure shape and size of the unit structure often vary considerably. The electromagnetic response of the unit structure nanostructure is used to design the optical path. The figure illustrates a locally magnified metalens structure, which has microstructures. These microstructures are typically shaped like cylinders, square prisms, or rhomboid prisms, with a generally consistent height but inconsistent spacing between them. In this embodiment, diffraction of light is achieved through gaps smaller than the wavelength between adjacent microstructures. Through diffraction, the light can be adjusted, including adjusting the phase and angle of the light.

[0105] A 3D sensing device includes a depth information camera module according to any of the above embodiments. The D-ToF sensor having the depth information camera module can be applied to automotive electronics and consumer electronics.

[0106] The traditional popular application of D-ToF in automotive electronics is in-vehicle LiDAR. In in-vehicle LiDAR, the main function is to achieve high 2D resolution ranging. In automotive applications, the key indicators of D-ToF include ranging distance, distance resolution, 2D resolution, and anti-interference ability.

[0107] Beyond automotive electronics, a new emerging field for D-ToF and SPAD is consumer electronics. With the rise of new applications such as AR / VR, the demand for depth sensors in the consumer electronics sector is also rapidly increasing. For consumer electronics applications, the main advantage of using D-ToF is that it can achieve both a longer ranging distance and higher ranging accuracy. Therefore, when it is necessary to extend the ranging distance to more than 10 meters, D-ToF may become a better choice. In addition, since D-ToF is less sensitive to ambient light interference, it allows the depth sensing of smart devices to work in scenarios with different lighting intensities.

[0108] The basic principles, main features, and advantages of this application have been described above. Those skilled in the art should understand that this application is not limited to the above embodiments. The embodiments and descriptions in the specification are merely the principles of this application. Various changes and modifications can be made to this application without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claims. The scope of protection claimed by this application is defined by the appended claims and their equivalents.

Claims

1. A depth information camera module, characterized in that: The device includes a package body, a driver chip, and a light source chip. The package body has a projection end, and a circuit board is disposed inside the projection end. The driver chip is covered by a package substrate. The package substrate and the light source chip are stacked sequentially on the circuit board near the object side. The driver chip and the light source chip are connected by multiple first conductive lines. The driver chip and the circuit board are connected by second conductive lines. A first electronic component is disposed between the package substrate and the light source chip.

2. The depth information camera module as described in claim 1, characterized in that: The circuit board is provided with at least one second electronic component, the first electronic component is configured to conduct electricity in a first direction, and the second electronic component is configured to conduct electricity in a second direction.

3. The depth information camera module as described in claim 2, characterized in that: The first electronic component is a power supply capacitor, and the second electronic component is a drive capacitor.

4. The depth information camera module as described in claim 1, characterized in that: The first electronic component is directly connected to the pins of the package substrate and the pins of the light source chip.

5. A depth information camera module as described in claim 1, characterized in that: The light source chip and the circuit board are connected by a third conductive line. The length of the first conductive line is less than the length of the second conductive line, and the length of the first conductive line is less than the length of the third conductive line. The first conductive line includes a power line, and the length of the power line is less than the length of the rest of the first conductive lines excluding the power line.

6. A depth information camera module as described in claim 5, characterized in that: At least a portion of each of the first conductive lines is arranged in a straight line in the vertical direction, and the length of the power line excluding the portion arranged in the straight line in the vertical direction is less than the length of the remaining first conductive lines excluding the portion arranged in the straight line in the vertical direction.

7. A depth information camera module as described in claim 1, characterized in that: A conductive layer is disposed within the encapsulation substrate, and a conductive sphere is disposed at one end of the conductive layer near the circuit board. At least a portion of the conductive sphere is exposed outside the encapsulation substrate. A buffer medium is disposed between the encapsulation substrate and the circuit board, and the buffer medium is adapted to fill the gap formed between the encapsulation substrate and the circuit board that accommodates the conductive sphere.

8. A depth information camera module as described in claim 1, characterized in that: The encapsulation body has a receiving end, and the projection end and the receiving end are integrally formed. The projection end and the receiving end form a stepped structure near the object side. The relationship between the total length TTL-RX of the receiving end after installing the optical mechanism and the total length TTL-TX of the projection end after installing the optical mechanism satisfies the following formula: 1.0 < TTL-RX / TTL-TX < 1.

1.

9. A depth information camera module as described in claim 8, characterized in that: The total length of the optical system after the optical mechanism is installed at the receiving end is less than the total length of the optical system after the optical mechanism is installed at the projection end; a light-transmitting hole is opened on the receiving end, and a photosensitive chip is disposed on the receiving end. The photosensitive chip is flip-chip disposed on the side of the light-transmitting hole away from the object side. The circuit board is located in the receiving end on the side of the light-transmitting hole away from the object side. The photosensitive chip is flip-chip disposed on the side of the circuit board away from the object side. The circuit board and the photosensitive chip are connected by solder pads. A light-blocking medium is disposed between the solder pads of the circuit board and the solder pads of the photosensitive chip.

10. A 3D sensing device, characterized in that: Includes the depth information camera module as described in any one of claims 1 to 9.

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