Digital reset circuit and chip
By using pseudo-random number generators and controllers with different voltage domains in the digital reset circuit, the problems of large reset area and insufficient stability of analog circuits are solved, thereby improving the reliability and stability of the chip.
Patent Information
- Application Number
- CN202410866194.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-12-30
AI Technical Summary
Current chip power-on reset mainly relies on analog circuits, resulting in large area, high design difficulty, and system stability that is greatly affected by process and environment.
A digital reset circuit is adopted, which utilizes two pseudo-random number generators to operate in different voltage domains. The controller generates a reset signal, monitors voltage stability in real time, enhances the sensitivity to power supply fluctuations, and dynamically generates a reliable reset signal.
It enables reliable reset under unstable power supply voltage, improving the chip's operational reliability and stability, while also having a small circuit area and simple design.
Smart Images
Figure CN121239201A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of reset circuit technology, and in particular to a digital reset circuit and chip. Background Technology
[0002] Currently, chip power-on reset primarily relies on a power-on reset (POR) signal generated by analog circuits. POR not only ensures the reset capability of digital reset circuits but is also fundamental to the normal operation of some analog modules. However, analog circuits are large in area, difficult to design, and their system stability faces significant challenges under varying process and environmental conditions. Summary of the Invention
[0003] The embodiments of this application provide a digital reset circuit and chip.
[0004] The digital reset circuit of this application includes a first pseudo-random number generator, a second pseudo-random number generator, and a controller. The first pseudo-random number generator is used to generate a first pseudo-random number; the second pseudo-random number generator is used to generate a second pseudo-random number, and the first and second pseudo-random number generators operate in different voltage domains; the controller is used to generate a reset signal based on the first and second pseudo-random numbers, and to perform a reset based on the reset signal.
[0005] The chip in this embodiment includes a reset unit and a digital reset circuit. The digital reset circuit generates a reset signal, and the reset unit performs a reset based on the reset signal.
[0006] In the digital reset circuit and chip of this application, two pseudo-random number generators operating in different voltage domains generate pseudo-random numbers respectively. Specifically, a first pseudo-random number generator generates a first pseudo-random number, and a second pseudo-random number generator generates a second pseudo-random number. This enhances the sensitivity to power supply fluctuations. When the power supply voltage is unstable, the pseudo-random number generated by the pseudo-random number generator operating in the lower voltage domain generally fluctuates first, causing the first and second pseudo-random numbers to differ. This allows for earlier detection of voltage instability, reducing the probability of system malfunction. Furthermore, dynamically generating pseudo-random numbers through the pseudo-random number generator is logically simple and allows for dynamic monitoring of voltage stability throughout the chip's operation, resulting in a more reliable reset.
[0007] The controller of the digital reset circuit monitors pseudo-random numbers in different voltage domains in real time to generate a reset signal. This provides a reliable reset signal in scenarios with unstable power supply voltage (such as during power-on) and a safe reset when the power supply voltage is unstable. This not only makes up for the instability of analog circuits, but also has a simple implementation method and a small circuit area, improving the reliability and stability of chip operation with the most limited resources.
[0008] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description
[0009] The above and / or additional aspects and advantages of the embodiments of this application will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, wherein:
[0010] Figure 1 This is a schematic diagram of the chip structure according to certain embodiments of this application.
[0011] Figure 2 This is a schematic diagram of the structure of a digital reset circuit according to certain embodiments of this application.
[0012] Figure 3 This is a signal timing diagram of a digital reset circuit according to certain embodiments of this application.
[0013] Figure 4 This is a signal timing diagram of a digital reset circuit according to certain embodiments of this application.
[0014] Figure 5 This is a signal timing diagram of a digital reset circuit according to certain embodiments of this application.
[0015] Figure 6 This is a schematic diagram of the structure of a digital reset circuit according to certain embodiments of this application.
[0016] Figure 7 This is a signal timing diagram of a digital reset circuit according to certain embodiments of this application.
[0017] Figure 8 This is a signal timing diagram of a digital reset circuit according to certain embodiments of this application.
[0018] Figure 9 This is a schematic diagram of the structure of a pseudo-random number generator according to certain embodiments of this application. Detailed Implementation
[0019] The embodiments of this application will be further described below with reference to the accompanying drawings. Throughout the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions.
[0020] Furthermore, the embodiments of this application described below in conjunction with the accompanying drawings are exemplary and are only used to explain the embodiments of this application, and should not be construed as limiting this application.
[0021] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0022] Please see Figure 1 The digital reset circuit 10 includes a first pseudo-random number generator 11, a second pseudo-random number generator 12, and a controller 13. The first pseudo-random number generator 11 is used to generate a first pseudo-random number; the second pseudo-random number generator 12 is used to generate a second pseudo-random number, and the first pseudo-random number generator 11 and the second pseudo-random number generator 12 operate in different voltage domains; the controller 13 is used to generate a reset signal based on the first pseudo-random number and the second pseudo-random number, and to perform a reset based on the reset signal.
[0023] The digital reset circuit 10 of this application generates pseudo-random numbers through two pseudo-random number generators operating in different voltage domains. Specifically, a first pseudo-random number generator 11 generates a first pseudo-random number, and a second pseudo-random number generator 12 generates a second pseudo-random number. This enhances the sensitivity to power supply fluctuations. When the power supply voltage is unstable, the pseudo-random number generated by the pseudo-random number generator operating in the lower voltage domain will generally fluctuate first, causing the first and second pseudo-random numbers to differ. This allows for earlier detection of voltage instability, reducing the probability of system malfunctions. Furthermore, the dynamic generation of pseudo-random numbers through the pseudo-random number generators is logically simple and allows for dynamic monitoring of voltage stability throughout the chip's operation, resulting in a more reliable reset.
[0024] The controller 13 of the digital reset circuit 10 monitors pseudo-random numbers in different voltage domains in real time to generate a reset signal. This provides a reliable reset signal in scenarios where the power supply voltage is unstable (such as during power-on) and also provides a safe reset when the power supply voltage is unstable. This not only makes up for the instability of analog circuits, but also has a simple implementation method and a small circuit area, improving the reliability and stability of chip operation with the most limited resources.
[0025] Please refer again to 1. Chip 100 includes a reset unit 20 and a digital reset circuit 10. The digital reset circuit 10 is used to generate a reset signal, and the reset unit 20 is used to perform a reset based on the reset signal.
[0026] The reset unit 20 is used to collect various reset sources to perform reset control on the entire system. The reset unit 20 is a critical component, especially in digital electronic systems and microcontrollers (such as single-chip microcomputers), as it is responsible for restoring the system state to a known initial state under specific conditions, ensuring reliable system startup and operation. The digital reset circuit 10 adopts a digital circuit design, capable of stably generating reset signals acting on the reset unit 20 to achieve reliable reset.
[0027] In some embodiments, the chip 100 further includes a clock source 30. The clock source 30 includes two types: a high-frequency clock source and a low-frequency clock source. The frequency of the high-frequency clock source is higher than that of the low-frequency clock source, so as to meet the different functional requirements of the chip 100 respectively.
[0028] In some embodiments, the digital reset circuit 10 includes a first pseudo-random number generator 11, a second pseudo-random number generator 12, and a controller 13.
[0029] The random number generator uses a deterministic algorithm to generate seemingly random but actually deterministic sequences of numbers based on an initial value (called a seed). Although these sequences appear random to the human eye, given the same seed, they will generate exactly the same sequence of numbers. A first pseudo-random number generator 11 is used to generate a first pseudo-random number, and a second pseudo-random number generator 12 is used to generate a second pseudo-random number.
[0030] In some embodiments, the first pseudo-random number generator 11 operates in the first voltage domain, and the second pseudo-random number generator 12 operates in the second voltage domain, wherein the voltage corresponding to the first voltage domain is less than the voltage corresponding to the second voltage domain.
[0031] Optionally, the first voltage domain and the second voltage domain can be obtained by resistor voltage division.
[0032] like Figure 1As shown, the first voltage domain is the voltage domain with operating voltage VDDL, and the second voltage domain is the voltage domain with operating voltage VDD. Since the voltage VDDL is obtained by voltage division through resistors R1 and R2, VDDL is less than VDD. That is to say, the first voltage domain is a low voltage domain, the second voltage domain is a high voltage domain, and the voltage corresponding to the first voltage domain is less than the voltage corresponding to the second voltage domain.
[0033] In order to ensure that the digital reset circuit 10 in the low voltage domain can operate normally and detect the initial voltage fluctuation first, VDDL can be set to be slightly lower than VDD. For example, the ratio of the voltage corresponding to the first voltage domain to the voltage corresponding to the second voltage domain is a preset ratio, which is less than 1.
[0034] For example, Figure 1 In the circuit, the ratio of R1 to R2 is 1:9, so the voltage value of VDDL is 90% of VDD. It is understandable that the specific ratio needs to be adjusted according to different processes, provided that the digital reset circuit 10 can function normally.
[0035] Optionally, all signals that cross two different voltage domains in this application are provided with power isolation by default. Power isolation is a known technology and will not be described in detail in this application.
[0036] In some embodiments, in order to ensure the normal operation of the digital reset circuit 10, all circuit components in the digital reset circuit 10 except for the first pseudo-random number generator 11 operate in the high voltage domain.
[0037] In some embodiments, the first pseudo-random number generator 11 and the second pseudo-random number generator 12 have the same circuit design to ensure that their values are completely consistent when they are working normally.
[0038] Specifically, when the circuit designs of the first pseudo-random number generator 11 and the second pseudo-random number generator 12 are identical, given the same initial value, the pseudo-random numbers generated by the first pseudo-random number generator 11 and the second pseudo-random number generator 12 at any given time will be the same. Thus, once the power supply voltage fluctuates, the pseudo-random numbers generated by the first pseudo-random number generator 11 in the low-voltage domain will fluctuate, resulting in a difference from the pseudo-random numbers generated by the second pseudo-random number generator 12. This achieves accurate detection of power supply fluctuations, ensuring the accuracy and timeliness of subsequent resets.
[0039] In some embodiments, the controller 13 is configured to generate a reset signal if the first pseudo-random number and the second pseudo-random number are different.
[0040] Please see Figure 1 and Figure 2 In some embodiments, the controller 13 includes a state machine 131 and a counter 132.
[0041] State machine 131 is used to determine the current state of digital reset circuit 10, such as reset state or idle state. In reset state, it is determined that the power supply voltage is unstable, and state machine 131 will generate a reset signal. In idle state, it indicates that the power supply voltage is stable, and no reset signal will be generated.
[0042] Optionally, the inputs to the state machine 131 include a first pseudo-random number, a second pseudo-random number, and the counting information of the counter 132. The current state of the digital reset circuit 10 can be determined based on at least one of the first pseudo-random number, the second pseudo-random number, and the counting information.
[0043] For example, state machine 131 can determine to enter the reset state if it detects that the first pseudo-random number and the second pseudo-random number are different. As another example, in the reset state, it can determine whether to switch from the reset state to the idle working state based on whether the first pseudo-random number and the second pseudo-random number are the same, and whether the counter 132 has reached a preset delay time.
[0044] The counter 132 is a digital circuit capable of accumulating and counting input pulses. For example, it can accumulate and count the clock signal generated by the clock source 30.
[0045] In some embodiments, state machine 131 is connected to counter 132 and is used to control the reset and clearing of counter 132, start timing, etc.
[0046] In some embodiments, state machine 131 is used to generate a first reset signal and a second reset signal in a reset state to reset the first pseudo-random number generator 11, the second pseudo-random number generator 12 and the digital system of chip 100.
[0047] The first reset signal is used to reset the first pseudo-random number generator 11 and the second pseudo-random number generator 12 (e.g., Figure 1 and Figure 2 The second reset signal is used to reset the digital system of chip 100 (e.g., RESERTN). Figure 1 and Figure 2 (POR in the text).
[0048] In some embodiments, when the state machine 131 is in a reset state, it can also generate a third reset signal, which is used to reset the counter 132 so that the counter 132 is cleared to zero; the state machine 131 is also used to generate an enable signal so that the counter 132 starts counting.
[0049] Specifically, such as Figure 2In this context, cntrst and cnten are the reset signal (i.e., the third reset signal) and enable signal of counter 132, respectively. When cntrst is valid, counter 132 is reset to zero; otherwise, counting is enabled. When cnten is valid, counter 132 increments; otherwise, it retains its current value. State machine 131 can control counter 132 to achieve timing with different delay times through cntrst and cnten.
[0050] In some embodiments, the clock source 30 of the digital reset circuit 10 can be designed independently or reuse the clock source 30 used by the chip 100. In this application, the controller 13 does not have high frequency accuracy requirements, so a low-frequency clock source can be reused. In this way, by reusing a low-frequency clock source, the cost of the digital reset circuit 10 is reduced.
[0051] Please combine Figure 3 After introducing the various components of the digital reset circuit 10, the specific working process of the digital reset circuit 10 to achieve reset will be described below.
[0052] The digital reset circuit 10 implements the reset process based on different states detected by the state machine 131. The states that the state machine 131 can detect may include the reset state and the idle working state (hereinafter referred to as S1). The reset state also includes the pseudo-random number generator reset state (hereinafter referred to as S2), the reset delay state (hereinafter referred to as S3), and the pseudo-random number generator reset release state (hereinafter referred to as S4).
[0053] 1. Idle operating state (S1) is the normal operating state of chip 100. Under normal circumstances, the power supply voltage is stable, and the digital reset circuit 10 works normally, without the need to generate a reset signal. However, since the controller 13 does not receive an external reset signal, its initial state after power-on is uncertain. Therefore, when entering this state for the first time, the reset signal (specifically the second reset signal, also known as POR reset) cannot be released immediately. Special handling is required. That is, when entering this state for the first time, a POR reset must be generated, and the POR reset must be released only after a certain delay (i.e., the POR reset fails or no longer generates a POR reset signal). This ensures sufficient reset time, guarantees the effectiveness of the reset, and avoids abnormal POR reset transitions when entering this state from other states.
[0054] In summary, in actual chip 100, the following situations may occur when entering this state:
[0055] 1) The power-on process is about to end, and the power supply voltage has reached the normal operating range of the digital reset circuit 10.
[0056] 2) The power supply voltage has just stabilized after a round of abnormal fluctuations.
[0057] 3) Unstable power supply voltage causes state machine 131 to jump arbitrarily and mistakenly enter this state from other states.
[0058] In all the above scenarios, it is necessary to maintain the POR reset (i.e., delay the release of the POR reset) upon initial entry into this state, especially in scenario 3). If the voltage continues to be unstable, it is very likely that the voltage will randomly jump to other arbitrary states from this state. Therefore, it is even more necessary to maintain a valid POR reset value to ensure that the POR reset is not released arbitrarily. A delay must be inserted (e.g., ...). Figure 3 The POR reset can only be released after DELAY1 is shown. During normal operation of chip 100, this state only needs to monitor the values of pseudo-random number 1 (i.e., the first pseudo-random number) and pseudo-random number 2 (i.e., the second pseudo-random number) in real time. Once they are not equal, it is determined that the power supply voltage is unstable and immediately jumps to the next state, i.e., the pseudo-random generator reset state.
[0059] 2. Pseudo-random number generator reset state (S2): Simultaneously reset both pseudo-random number generators and generate a POR reset, notifying the reset unit 20 of chip 100 to reset the entire chip 100. Also reset counter 132, clearing it to zero to prepare for the delay wait in the next state.
[0060] 3. Reset Delay State (S3): Keeps POR reset valid and waits for a long delay (e.g., Figure 3 The long delay (DELAY2) is achieved by starting counter 132 and waiting for it to overflow. Counter 132 is started and incremented from 0 until it reaches a preset value, which is considered to be an overflow, and then the process enters the next state, the reset and release state of the pseudo-random number generator.
[0061] 4. Reset and release state of pseudo-random number generators (S4): Releases the reset of both pseudo-random number generators and allows them to run for a period of time, thus inserting a delay (e.g., Figure 3 After DELAY2 is shown, the pseudo-random number 1 and pseudo-random number 2 are compared. If they are the same, it is determined that the power supply voltage is stable and the digital reset circuit 10 can work normally and can enter the normal working state (S1). If they are different, a new round of reset is required, and the pseudo-random number generator reset state needs to be entered (S2).
[0062] After introducing the various states of state machine 131, the process of resetting state machine 131 will be described below.
[0063] (1) When entering the reset state (specifically S2, i.e., when it is found that pseudo-random number 1 and pseudo-random number 2 are different in the idle working state or during the power-on process, i.e., entering S2), the state machine 131 generates a first reset signal and a second reset signal to reset the digital system of the first pseudo-random number generator 11, the second pseudo-random number generator 12 and the chip 100.
[0064] (2) At this time, the state machine 131 enters S3, controls the counter 132 to start timing, and releases the first reset signal (i.e., RESETN becomes high level) when the timing reaches the first delay time (i.e. DELAY2), so that the first reset signal is invalidated and the pseudo-random number generator is reset.
[0065] (3) At this time, enter S4. After releasing the first reset signal, control the counter 132 to start timing again (i.e., DELAY3);
[0066] (4) If the timing reaches the second delay time and the first pseudo-random number and the second pseudo-random number are still different, then the first reset signal is generated again (i.e., enter S2 again); if the timing reaches the second delay time and the first pseudo-random number and the second pseudo-random number are the same, then enter the idle working state (i.e., enter S1).
[0067] (5) In the idle working state, control the counter 132 to start timing again, and when the timing reaches the third delay time (i.e. DELAY1), release the second reset signal (i.e. POR becomes low level) so that the second reset signal is invalidated and POR reset is completed.
[0068] The reset process will be described below for different work scenarios.
[0069] There are several main working scenarios. One is how the digital reset circuit 10 generates a POR reset and releases it normally during the power-on period of chip 100. Another is how the POR reset is caused by power supply voltage fluctuations during the operation of chip 100, and how the POR reset is released after the voltage returns to normal. The power supply voltage fluctuations can be further divided into two types: slight fluctuations and large fluctuations.
[0070] Scenario 1: During the power-on process of chip 100, such as Figure 3As shown, the power supply voltage gradually rises to the target operating voltage (i.e., V1). VDD is the operating voltage of controller 13, which is in the same voltage domain as the normal digital logic circuit of chip 100. VDDL is the operating voltage in the low voltage domain. POR is the power-on reset signal (i.e., the second reset signal) generated by controller 13. In this example, a high level indicates that the power-on reset is valid. RESETN is the reset signal (i.e., the first reset signal) of the two pseudo-random generators generated by controller 13. In this example, a low level indicates that the reset is valid. LFSR1 (i.e., the first pseudo-random number generator 11) and LFSR2 (i.e., the second pseudo-random number generator 12) represent pseudo-random numbers generated by two pseudo-random number generators, respectively from the VDDL and VDD voltage domains. The value is represented by D. In all timing diagrams, the subscripts of D (0, 1, 2…, n, n+1, n+2…, m, m+1, m+2…, k, k+1, k+2…) represent values for several different time periods. The random value represents any possible value; two random values are unlikely to be equal at the same time. The reset value is the output value of the pseudo-random number generator in the reset state. V1 represents the critical voltage value at which the digital reset circuit 10 cannot work normally during power-on and can work normally; the actual value depends on the manufacturing process of chip 100. State machine 131 is the state machine 131 in controller 13.
[0071] To explain the power-on process in detail, Figure 3 The table marks five time points (T1 to T5), representing several key states during power-on:
[0072] Before time T1, the digital reset circuit 10 in the high-voltage domain cannot operate stably due to insufficient voltage amplitude. Therefore, LFSR2 is an unpredictable random value, and state machine 131 is also in a random state. For example, before T1, it is in state S1 (it may randomly appear in any of the states from S1 to S4). However, because the comparison between the two LFSR1 and LFSR2 is different, after T1, it will eventually enter state S2 and eventually return to state S1. Here, RESETN needs to be continuously pulled low and POR pulled high to generate a POR reset. After time T1, since the voltage in the high-voltage domain has exceeded V1, the digital reset circuit 10 in the high-voltage domain can operate normally. Therefore, LFSR2 can change from an unstable random value to a stable reset value, and state machine 131 also starts to operate normally, entering state S2, continuing to pull RESETN low, and generating a POR reset.
[0073] Before time T2, the digital reset circuit 10 in the low-voltage domain also cannot operate stably due to insufficient voltage amplitude. Therefore, the sampled value on LFSR1 is also an unpredictable random value. Only after time T2, when the voltage exceeds V1, does it enter a stable reset state. Because there is a voltage difference between the two voltage domains, T2 is usually later than T1. This results in the two pseudo-random numbers not being able to match until after T2.
[0074] Before time T3, there is a delay period DELAY2 during which RESETN remains low. This delay allows the pseudo-random number generators in both voltage domains to reset safely and stably, preventing premature reset release during periods of voltage instability. This delay is based on the operating clock, and state machine 131 primarily waits in state S3, with a sufficiently long clock cycle count. In this example, the clock uses the internal slow clock source 30 of chip 100, with a frequency of 32kHz. One cycle is approximately 31.25µs, and waiting for 64 cycles equates to a 2ms delay, which is generally sufficient for the power supply to stabilize. After time T3, the voltage amplitude is considered to have stabilized at the potential required for normal operation, and the reset can be released (i.e., the first reset signal RESETN is released). State machine 131 also enters state S4, allowing both pseudo-random number generators to start working simultaneously, ensuring that the pseudo-random value sampled in each iteration is identical.
[0075] Before time T4 and after time T3, there is a deliberately inserted delay wait DELAY3, which allows the pseudo-random number generator to work for a period of time. When the delay wait ends, state machine 131 compares the values of LFSR1 and LFSR2 one last time. If the values are the same, it enters the normal working state S1; otherwise, it continues to enter S2. Figure 3 As can be seen, the state switching time is in the middle of the stable values of LFSR1 and LFSR2. This is to ensure that a stable and accurate LFSR value can be sampled. The specific implementation method is related to the clock edge and will be described in the inverter embodiment below.
[0076] Before time T5, state machine 131 has already entered the normal working state, but it does not immediately release the POR reset. Instead, it waits for a delay of DELAY1 before pulling POR low at time T5 to release the reset. This is also for the sake of system stability, as explained in the explanation of S1 above. After time T5, POR remains in the released state, and the two pseudo-random generators work normally, so state machine 131 can remain stable in state S1.
[0077] Please see Figure 4Scenario 2: During the operation of chip 100, a power supply voltage fluctuation causes a POR reset. In this case, the power supply voltage fluctuation is small, only causing the low-voltage domain digital reset circuit 10 to malfunction. For example... Figure 4 As shown, Dk, Dk+1, Dk+1... are two pseudo-random numbers generated by the pseudo-random generator when chip 100 is working normally, and their values are exactly the same at the same time. The explanation of T2 to T5 here is the same as... Figure 3 Exactly the same, except for two additional time points:
[0078] Before time T1', the voltage begins to drop, but the circuits in both voltage domains can operate normally, so the values of LFSR1 and LFSR2 are equal. After time T1', the VDDL voltage has fallen below the threshold value that supports the normal operation of the digital reset circuit 10, causing LFSR1 to enter a random state. State machine 131 detects that the values of the two pseudo-random numbers are inconsistent and decides to exit the normal operation state S1.
[0079] At time T2', POR is pulled high to generate a reset flag and reset the two pseudo-random generators, while RESETN is pulled low.
[0080] The timing sequence of T2 to T5 is exactly the same as that of T34. In this scenario, it is demonstrated that this application can detect voltage instability as early as possible, thereby reducing the probability of system malfunction. At the same time, the use of a small voltage difference between the two voltage domains also avoids excessive sensitivity to power supply voltage, which could lead to unnecessary resets.
[0081] Please see Figure 5 In scenario three, during the operation of chip 100, a power supply voltage fluctuation causes a POR reset. At this time, the power supply voltage fluctuation is significant, causing both the high and low voltage domain digital reset circuits 10 to malfunction. For example... Figure 5 As shown, two new time points, T3' and T4', are added, representing the moments when the voltage in the high-voltage domain drops and rises to the critical values for the normal operation of the digital reset circuit 10, respectively.
[0082] After time T3', the high-voltage domain digital reset circuit 10 cannot work properly, so LFSR2 and state machine 131 will enter a random state. Even if RESETN is pulled low, LFSR2 cannot guarantee the reset value.
[0083] After time T4', the digital reset circuit 10 in the high voltage domain starts to work normally, and a normal reset value can be seen on LFSR2. However, since the voltage in the low voltage domain has not yet risen to the critical value, LFSR1 is still a random value until time T2, when it can enter the normal reset state.
[0084] It is important to note that Figure 5 The given time T4' is used to... Figure 3 The state machine 131 maintains consistency with T1, providing an example of transitioning from S1 to S2. During the actual time interval T3' to T4', state machine 131 may enter any state from S2 to S4. Therefore, the starting point of time T4' could be any state from S2 to S4. However, due to the unidirectional execution of states from S2 to S4, as long as the values of LFSR1 and LFSR2 are successfully compared, it will eventually return to S1, ensuring the safe release of the POR reset. Each case is further explained here:
[0085] When T4' is exactly S4, it will enter S2 after a delay of DELAY3. At this time, the delay of DELAY3 may be inaccurate because the initial value of counter 132 may also be a random value. When the delay is insufficient, the power supply voltage is still unstable, so the comparison in S4 will eventually fail, and it will enter S2 for a new round of POR reset.
[0086] When T4' is exactly S3, it will enter S4 after a delay of DELAY2, and then return to S1. Similarly, the delay of DELAY2 may not be accurate. When the delay is insufficient, the comparison in S4 will fail, and it will enter S2 again for a new round of POR reset.
[0087] When T4' is exactly S2, it directly enters S3 and after a series of delays, it finally returns to S1. Since counter 132 is reset in S2, the delays of DELAY3 and DELAY4 will be executed as expected.
[0088] Note that all the random cases of state machine 131 described above are also fully applicable. Figure 3 Mid-T1 time point.
[0089] Another consideration is that when state machine 131 enters a random state, specifically during the time interval between T3' and T4', POR must remain high. When randomly entering states S2 through S4, according to the design of state machine 131, POR reset remains high throughout. When randomly entering state S1, as mentioned earlier, an initial delay of DELAY1 is required to release the POR reset. However, when the voltage is unstable, it is extremely difficult for randomly entered state S1 to remain in that state for a sufficiently long time. Therefore, POR will also remain high in state S1, thus avoiding POR level fluctuations.
[0090] Please see Figure 6In some embodiments, the digital reset circuit 10 further includes an inverter 40, a first pseudo-random number generator 11 and a second pseudo-random number generator 12 are connected to the clock source 30, and the controller 13 is connected to the clock source 30 through the inverter 40. The inverter 40 is used to flip the phase of the clock signal generated by the clock source 30 so that the clock signal entering the first pseudo-random number generator 11 and the second pseudo-random number generator 12 is opposite in phase to the clock signal entering the controller 13.
[0091] Specifically, the sampling time of the pseudo-random numbers in controller 13 also needs attention. Since there is only one clock source 30 and the two random numbers come from different voltage domains, it is difficult to constrain the clock during synthesis and placement and routing. In order to ensure that the two sampled pseudo-random numbers are stable values, i.e., to avoid metastability caused by insufficient setup or hold time, the operating clock of the pseudo-random number generator is reversed with the operating clock of the state machine 131. That is, the clock signal generated by the clock source 30 and input to controller 13 is reversed through inverter 40. Figure 6 The phase of CLK is flipped by 180 degrees so that the working clock of the state machine 131 adopts the falling edge of CLK, and the working clock of the pseudo-random number generator adopts the rising and falling edges of CLK. In this way, the time from the generation of pseudo-random numbers to the sampling of them by state machine 131 is half a clock cycle. Since the frequency of CLK is relatively slow and the period is relatively long, the metastability problem is easily solved.
[0092] Clock connection diagram as follows Figure 6 As shown, clock source 30 (RCCLK) directly enters the first and second pseudo-random number generators as the working clock, but it needs to pass through an inverter 40 before entering counter 132 and state machine 131. The timing diagram for random number sampling by state machine 131 is shown below. Figure 7 As shown, both POR (the second reset signal) and RESETN (the first reset signal) are controlled by state machine 131, so their transition edges are both at the falling edge of CLK, including the switching moments of state machine 131. However, during normal operation, data changes for LFSR1 and LFSR2 occur at the rising edge of CLK.
[0093] Optionally, the inverter 40 can also toggle the clock signals entering the first pseudo-random number generator 11 and the second pseudo-random number generator 12, so that the operating clock of the state machine 131 uses the rising edge of CLK, while the operating clock of the pseudo-random number generator uses the falling edge of CLK.
[0094] In some embodiments, the number of bits counted by counter 132 is determined based on the operating clock frequency of counter 132.
[0095] Specifically, when the power supply voltage is unstable, the value of counter 132 may also be abnormal. Therefore, the bit width of counter 132 should not be too large to avoid excessive delays caused by overflow due to abnormal values. For example, if a 16-bit counter 132 is used, once a value of 64 is obtained, it may continue to increment until it reaches 0xffff before returning to 0 to restart counting, resulting in excessively long delays. The higher the operating clock frequency of counter 132, the smaller the maximum timing duration for the same number of counting bits. Therefore, to ensure that the maximum timing duration is not too large and causes excessive delays, the number of counting bits of counter 132 is determined based on its operating clock frequency.
[0096] Therefore, the counter 132 can have a bit width of 7 bits, which can reduce the risk of such a long delay. It can also be controlled by logic comparing the count value; for example, counting can be considered complete when the count value is greater than or equal to 63.
[0097] Controller 13 also needs to control counter 132 to achieve different delay times. DELAY1 to DELAY3 share the same counter 132, thus saving circuit area. Figure 6 As shown, controller 13 and counter 132 use the same clock edge, and controller 13 generates two control signals: cntrst and cnten, which are the reset signal and enable signal of counter 132, respectively. When cntrst is valid, counter 132 is reset to zero; otherwise, counting is enabled. When cnten is valid, counter 132 increments; otherwise, it retains its current value. The timing diagram for delay control implemented through counter 132 is shown below. Figure 8 As shown, cntrst is active high for reset, and cnten is active high for enable. In this example, counter 132 uses synchronous reset, so its value needs to be adjusted accordingly on the next falling clock edge. Asynchronous reset can also be used in practical applications. Note that instances where cntrst and cnten use other active levels are not excluded.
[0098] To further explain, such as Figure 8 In the example, DELAY1 is 7 clock cycles, DELAY2 is 64 clock cycles, and DELAY3 is 10 clock cycles. Based on a 32kHz clock source 30, and considering the one-cycle consumption of the S2 state, the minimum hold time for the POR valid high level is approximately 2.6ms, which is about 2ms, similar to the minimum hold time of the pseudo-random number generator. Furthermore, an additional delay is typically introduced in the digital system reset unit 20 to ensure sufficient system reset time. Figure 8This is just an example; the specific delay time control, i.e., the target maximum value of counter 132 in S3, S4, and S1, can be adjusted according to the actual system characteristics and the frequency of clock source 30.
[0099] In some embodiments, the first pseudo-random number generator 11 and the second pseudo-random number generator 12 are both linear feedback shift registers (LFSRs). The linear feedback shift register includes multiple flip-flops, the outputs of which are connected to the inputs of NOR gates, and the outputs of the NOR gates are connected to the inputs of one or more flip-flops.
[0100] Specifically, the design of the pseudo-random number generator also needs to avoid the use of zero values. The digital reset circuit 10 typically uses an LFSR to generate pseudo-random numbers, which is a known technology. Inputting a zero value will prevent the generation of pseudo-random numbers. Since both pseudo-random number generators in this application may be in an unstable state, the possibility of zero values also exists. Therefore, additional design is needed to avoid interference from zero values in the traditional LFSR. The logic is relatively simple and is also existing technology. To provide a more detailed description of this application, a supplementary explanation is provided here: a NOR logic is added to the output of all flip-flops. That is, when all flip-flops are 0, a logic 1 is generated and fed back to one of the flip-flops. In this way, even if all flip-flops randomly produce all zeros, a non-zero value can still be generated on the next clock edge.
[0101] This section briefly introduces the circuit structure used in this example, for example... Figure 9 As shown, the pseudo-random number generator uses an 8-width LFSR, which includes eight flip-flops D0 to D7. They share the reset terminal rstn and the clock terminal clk. rstn is connected to... Figure 1 and Figure 2 RESETN, clk is connected to Figure 1 In the RCCLK, the output of flip-flop D0 is connected to the input of D7. Three XOR gates are inserted into the connections between D7 and D6, D5 and D4, and D4 and D3, respectively, and XORed with the output value Q0 from D0. Other adjacent flip-flops are directly connected from the output of the previous stage to the input of the next stage. The outputs Q0 to Q7 of D0 to D7 constitute the 8 bits of the pseudo-random number, which can be represented as follows in the first pseudo-random number generator:
[0102] LFSR1[7:0]={Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0}
[0103] Since the circuit structure of the second pseudo-random number generator is exactly the same as that of the first pseudo-random number generator, the internal structure of LFSR2 is also exactly the same. This allows pseudo-random numbers to be generated with each valid clock edge after reset.
[0104] However, in an unstable circuit state, if all flip-flops simultaneously reach a value of 0, Q0 to Q7 will remain at 0, preventing the generation of pseudo-random numbers. As mentioned earlier, to avoid circuit failure caused by 0 values, a NOR gate is introduced. The outputs of all flip-flops are connected to the NOR gate, and the N value is obtained after NOR logic calculation. This N value is then sent to the XOR gate at the input of D6 for XOR calculation. Thus, when all zeros arrive, N is 1, and the input of D6 will definitely receive a value of 1, thus exiting the all-zero state. When operating normally, N is 0. Since the values of Q0 and Q7 will always have non-zero values, it will not affect the normal generation of pseudo-random numbers.
[0105] Note the basic implementation of LFSR here. The width of LFSR, the number of XOR gates, and which XOR gate(s) the output N of the NOR gate is fed into are all adjustable items. This example is only a simplified description.
[0106] Please refer to it again. Figure 6 In some embodiments, the digital reset circuit 10 further includes a filter 50, which is used to filter the reset signal and filter out the reset signal containing multiple consecutive clock cycles of low level.
[0107] Optionally, filter 50 is a digital filter, mainly used to process digital signals to achieve purposes such as noise removal, extraction of useful signal components, and modification of signal spectral characteristics.
[0108] Specifically, considering that the rising edge of POR generated when state machine 131 switches from S1 to S2 still has randomness, even though DELAY1 guarantees a very low probability, a filter 50 needs to be introduced at the output of POR to avoid this extremely low probability. For example... Figure 6 As shown, by using the same clock negative edge, several clock cycles are used to filter out accidental POR jitter (such as filtering out reset signals containing low levels for multiple consecutive clock cycles), thereby enhancing the anti-interference capability of the circuit in this application. For example, this digital filter 50 can be designed to filter out the reset signal within two consecutive clock cycles if the reset signal contains low levels, thereby filtering out some unexpected jitter in the digital reset circuit 10 and avoiding unnecessary resets.
[0109] In the description of this specification, the references to "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0110] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one feature. In the description of this application, "multiple" means at least two, such as two or three, unless otherwise explicitly specified.
[0111] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A digital reset circuit, characterized by, include: The first pseudo-random number generator is used to generate the first pseudo-random number; A second pseudo-random number generator is used to generate a second pseudo-random number. The first pseudo-random number generator and the second pseudo-random number generator operate in different voltage domains. The controller is configured to generate a reset signal based on the first pseudo-random number and the second pseudo-random number, and to perform a reset based on the reset signal.
2. The digital reset circuit of claim 1, wherein, The first pseudo-random number generator operates in the first voltage domain, and the second pseudo-random number generator operates in the second voltage domain. The voltage corresponding to the first voltage domain is less than the voltage corresponding to the second voltage domain.
3. The digital reset circuit of claim 2, wherein, The ratio of the voltage corresponding to the first voltage domain to the voltage corresponding to the second voltage domain is a preset ratio, which is less than 1.
4. The digital reset circuit of claim 2, wherein, The first voltage domain and the second voltage domain are obtained by voltage division using resistors.
5. The digital reset circuit of claim 1, wherein, The circuit designs of the first and second pseudo-random number generators are identical.
6. The digital reset circuit of claim 1, wherein, The controller is also configured to generate a reset signal if the first pseudo-random number and the second pseudo-random number are different.
7. The digital reset circuit of claim 1, wherein, The controller includes a state machine, which is used to determine that the current state is a reset state when the first pseudo-random number and the second pseudo-random number are different, and to generate the reset signal in the reset state.
8. The digital reset circuit of claim 1, 6 or 7, wherein, The reset signal includes a first reset signal and a second reset signal. The first reset signal is used to reset the first pseudo-random number generator and the second pseudo-random number generator, and the second reset signal is used to reset the digital system of the chip containing the digital reset circuit.
9. The digital reset circuit of claim 8, wherein, The controller also includes a counter, and the controller is further configured to: When the reset state is entered, the first reset signal and the second reset signal are generated to reset the first pseudo-random number generator, the second pseudo-random number generator and the digital system of the chip; The counter is controlled to keep time, and when the time reaches a first delay time, the first reset signal is released so that the first reset signal is invalidated; After the first reset signal is released, the counter is controlled to start timing again; If the second delay time is reached and the first pseudo-random number and the second pseudo-random number are still different, then the first reset signal is generated again. If the timer reaches the second delay time and the first pseudo-random number and the second pseudo-random number are the same, it is determined that the idle working state is entered. In the idle working state, the counter is controlled to start timing again, and when the timing reaches the third delay time, the second reset signal is released so that the second reset signal is invalidated.
10. The digital reset circuit of claim 1, wherein, The controller includes a state machine and a counter. The reset signal further includes a third reset signal, which is used to reset the counter to zero. The state machine is also used to generate an enable signal to enable the counter to count.
11. The digital reset circuit according to claim 9 or 10, characterized in that, The number of bits in the counter is determined based on the counter's operating clock frequency.
12. The digital reset circuit of claim 1, wherein, The first pseudo-random number generator and the second pseudo-random number generator are connected with a clock source, the controller is connected with the clock source through an inverter, the inverter is used to reverse the phase of the clock signal generated by the clock source, so that the phase of the clock signal entering the first pseudo-random number generator and the second pseudo-random number generator is opposite to that of the clock signal entering the controller.
13. The digital reset circuit of claim 1, wherein, The first pseudo-random number generator and the second pseudo-random number generator are both linear feedback shift registers, the linear feedback shift register comprises a plurality of flip-flops, the output ends of the plurality of flip-flops are connected with the input ends of NOR gate circuits, and the output end of the NOR gate circuit is connected with the input end of one or more flip-flops.
14. The digital reset circuit of claim 1, wherein, Further comprising a filter, the filter is used to filter the reset signal, and filter out the reset signal containing a plurality of continuous clock cycles of low level.
15. The digital reset circuit of claim 1, wherein, The digital reset circuit is connected with a target clock source, the clock source comprises a high-frequency clock source and a low-frequency clock source, the frequency of the high-frequency clock source is higher than that of the low-frequency clock source, and the target clock source is the low-frequency clock source.
16. A chip, characterized by The reset unit is used for resetting according to the reset signal.