Integrated circuit structure with vertical pass transistor with bottom source connection

Abstract

Structures having vertical transport field effect transistors (FETs) with bottom source connections are described. In an example, an integrated circuit structure includes a channel structure over a substrate. The gate structure laterally surrounds the channel structure. A drain structure is over the gate structure and on the channel structure. A metal source structure is under the substrate and vertically under the channel structure. A conductive via passes through the substrate, the conductive via coupling the metal source structure to the channel structure.

Description

Technical Field

[0001] The embodiments disclosed herein belong to the field of integrated circuit structure and fabrication, particularly to integrated circuit structures having vertical transmission field-effect transistors (FETs) with bottom source connections, and methods for manufacturing integrated circuit structures having vertical transmission field-effect transistors (FETs) with bottom source connections. Background Technology

[0002] Over the past few decades, feature scaling in integrated circuits has been a driving force behind the continued growth of the semiconductor industry. Scaling to increasingly smaller features allows for increased density of functional units within the limited footprint of a semiconductor chip. For example, shrinking transistor size allows for the integration of an increased number of memory or logic devices on a single chip, facilitating the manufacture of products with increased capacity. However, the pursuit of ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors (e.g., tri-gate transistors) have become increasingly prevalent as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and the ability to implement less complex tri-gate fabrication processes. On the other hand, as microelectronic device dimensions scale down to below the 10-nanometer (nm) node, maintaining improved mobility and short-channel control presents challenges in device fabrication. Nanowires used to fabricate devices offer improved short-channel control.

[0004] However, scaling up multi-gate and nanowire transistors is not without its consequences. As the size of these basic building blocks of microelectronic circuits decreases, and as the absolute number of basic building blocks fabricated in a given area increases, limitations on the photolithography processes used to pattern these building blocks become unavoidable. In particular, there may be a trade-off between the minimum size (critical size) of a feature patterned in a semiconductor stack and the spacing between such features.

[0005] Another aspect of driving innovation is the advancement of high-bandwidth (HBW) computing. Attached Figure Description

[0006] Figure 1 Cross-sectional views of an interconnect stack having a positive-side power delivery and an interconnect stack having a back-side power delivery, according to embodiments of the present disclosure, are shown.

[0007] Figure 2A A cross-sectional view of an integrated circuit structure having a nanowire layer and a back-side power delivery according to an embodiment of the present disclosure is shown.

[0008] Figure 2B An angled view of a vertical transmission field-effect transistor (FET) is shown.

[0009] Figure 2C An angled view of a lateral transmission field-effect transistor (FET) is shown.

[0010] Figure 2D A cross-sectional view of a vertical transmission field-effect transistor (FET) is shown.

[0011] Figure 2E A cross-sectional view of a vertical transmission field-effect transistor (FET) according to an embodiment of the present disclosure is shown.

[0012] Figure 2F A cross-sectional view of another vertical transmission field-effect transistor (FET) according to another embodiment of the present disclosure is shown.

[0013] Figure 2G A cross-sectional view of another vertical transmission field-effect transistor (FET) according to another embodiment of the present disclosure is shown.

[0014] Figure 3 A cross-sectional view of a non-planar integrated circuit structure taken along the gate line according to an embodiment of the present disclosure is shown.

[0015] Figures 4A-4H A plan view of a substrate fabricated using a dual-side device fabrication method according to some embodiments is shown.

[0016] Figures 5A-5H A cross-sectional view of a substrate fabricated using a dual-side device fabrication method according to some embodiments is shown.

[0017] Figure 6 A cross-sectional view along the nanowires and fins for a non-endcap architecture according to an embodiment of the present disclosure is shown.

[0018] Figure 7 A cross-sectional view along the nanowires and fins is shown for a self-aligned gate end cap (SAGE) architecture according to an embodiment of the present disclosure.

[0019] Figure 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0020] Figure 8B An embodiment according to this disclosure is shown. Figure 8A A cross-sectional view of the source or drain of a nanowire-based integrated circuit structure taken along the a-a' axis.

[0021] Figure 8C An embodiment according to this disclosure is shown. Figure 8A A cross-sectional channel view of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0022] Figure 9 A computing device according to one embodiment of the present disclosure is shown.

[0023] Figure 10 An intermediary layer including one or more embodiments of the present disclosure is shown.

[0024] Figure 11A A computing device according to one embodiment of the present disclosure is shown.

[0025] Figure 11B A processing apparatus according to one embodiment of the present disclosure is shown. Detailed Implementation

[0026] An integrated circuit structure having a vertical transfer field-effect transistor (FET) with a bottom source connection is described, as well as a method for manufacturing an integrated circuit structure having a vertical transfer field-effect transistor (FET) with a bottom source connection. In the following description, numerous specific details, such as specific integration and material systems, are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features (e.g., integrated circuit design layouts) have not been described in detail to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0027] For reference purposes only, certain terms may also be used in the following description and are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientations in the referenced figures. Terms such as “front,” “rear,” “back,” and “side” describe the orientation and / or position of portions of a component within a consistent but arbitrary frame of reference, which are readily apparent from the text describing the component under discussion and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0028] The embodiments described herein are applicable to front-end process (FEOL) semiconductor fabrication and structures. FEOL is the first part of integrated circuit (IC) manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0029] The embodiments described herein are applicable to back-end process (BEOL) semiconductor fabrication and structures. BEOL is the second part of IC manufacturing, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for chip-to-package connections. During the fabrication phase of the BEOL, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0030] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme can be illustrated using the FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using the BEOL processing scenario, such a method can also be applied to FEOL processing.

[0031] One or more embodiments described herein relate to a vertical-transmission field-effect transistor (VTFET) having a bottom-source connection. One or more embodiments described herein relate to an integrated circuit structure having a vertical-transmission field-effect transistor with a bottom-source connection for back-side power delivery. It should be understood that although a source connection is described, more generally, throughout the document, references to a source connection may refer to a reference to a source or drain connection. For example, since bottom diffusion can be the source or drain of a transistor, these terms are used interchangeably.

[0032] To provide background, a successful approach to increasing transistor density over the past few decades has been to continuously shrink key transistor parameters such as gate length, contact polysilicon pitch, and wiring pitch. For any lateral transistor architecture (e.g., FinFET transistors), any reduction in polysilicon and wiring pitch reduces the space available for placing the gate, spacers, and contacts, necessitating a trade-off between transistor density and performance.

[0033] In embodiments, the structures described herein are suitable for use as high-bandwidth (HBW) devices capable of operating at low temperatures (e.g., in the range of -77°C to 0°C). In one embodiment, a thermal regulator / cooling device is coupled to a common board having a device with a structure coupled thereto as described herein. In one embodiment, the thermal regulator device and / or cooling device are included on a processing device having a structure as described herein. In embodiments, the structures described herein enable zetta computing units (Zuocs) to operate, for example, at low temperatures, and so on.

[0034] To provide further context, in standard cell designs, diffusion placement and metal wiring layers are designed around the power delivery scheme. The power delivery scheme can be via front-side bumps to reach the M0 and diffusion contacts, or in newer architectures, it can be via wafer back-side metal that overlaps through vias that will contact the diffusion contacts located on the front side. When these operations are performed on the front-side metal or the diffusion, there is a space allocation for delivering power.

[0035] Traditionally, power is delivered from the front-side interconnect. At the standard cell level, power can be delivered directly on top of the transistor or from the top and bottom cell boundaries. Power delivered from the top and bottom cell boundaries achieves a relatively short standard cell height with slightly higher power network resistance. However, the front-side power network shares the interconnect stack with signal routing, reducing signal routing tracks. Furthermore, for high-performance designs, the power metal traces at the top and bottom cell boundaries must be wide enough to reduce power network resistance and improve performance. This typically results in an increased cell height. According to one or more embodiments of this disclosure, power can be delivered from the back side of the wafer or substrate to address area and performance issues. At the cell level, the wider metal zero power at the top and bottom cell boundaries can be eliminated, thus reducing the cell height. Additionally, the power network resistance can be significantly reduced, resulting in performance improvements. At the block and chip levels, the number of front-side signal routing tracks increases due to the removal of power routing, and the power network resistance is significantly reduced due to very wide traces, large vias, and reduced interconnect layers.

[0036] In earlier technologies, the power delivery network from bumps to transistors required significant block resources. This resource occupancy on the metal stack manifested itself as a standard cell architecture at some process nodes, where layout versioning or cell placement constraints existed at the block level. In this embodiment, eliminating the power delivery network from the front-side metal stack allows for free-sliding cell placement within the block without power delivery complexity and placement-related latency variations.

[0037] In contrast. Figure 1Cross-sectional views of an interconnect stack having a positive-side power delivery and an interconnect stack having a back-side power delivery, according to embodiments of the present disclosure, are shown.

[0038] refer to Figure 1 The interconnect stack 100 with positive-side power delivery includes transistors 102 and signal and power delivery metallization 104. Transistor 102 includes a bulk substrate 106, semiconductor fins 108, terminals 110, and device contacts 112. Signal and power delivery metallization 104 includes conductive vias 114, conductive lines 116, and metal bumps 118.

[0039] Refer again Figure 1 The interconnect stack 150 with back-side power delivery includes a transistor 152, a front-side signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes semiconductor nanowires or nanoribbons 158, terminals 160, device contacts 162, and boundary deep vias 163. The front-side signal metallization 154A includes conductive vias 164A and conductors 166A. The power delivery metallization 154B includes conductive vias 164B, conductive lines 166B, and metal bumps 168.

[0040] To provide further context, one of the ultimate goals in standard cell design is to minimize the area impact of power delivery on signal routing while maintaining a robust power delivery scheme with minimal voltage drop from the power supply. With front-side power delivery, commercial standard cell architectures must allocate routing tracks for power and ground from the top of the front-side stack to the first metal routing layer M0. This approach utilizes metal routing tracks. This means that tighter metal spacing is required to deliver power when routing signals. Tighter metal spacing results in higher capacitance and resistance, leading to higher power consumption. Furthermore, a larger voltage drop occurs from the top of the stack to the transistor source due to resistance. It should be understood that devices with front and back contacts can use bumps to couple to both the front and back substrates. For example, a package device can be arranged such that both the front and back sides are conductively coupled to the substrate.

[0041] On the other hand, direct power connection to the back side is achieved through a deep via structure or back-side contact portion, for example, where power gating is performed in the front end. As an exemplary structure, Figure 2A A cross-sectional view of an integrated circuit structure having a nanowire layer and back-side power delivery according to an embodiment of the present disclosure is shown. It should be understood that, although in Figure 2A Nanowires (or nanoribbons or nanosheets) are depicted, but fin-based architectures can also be used.

[0042] refer to Figure 2AThe integrated circuit structure 200 includes a front-side structure 204 on a back-side structure 202. The front-side structure 204 includes a device layer 206 and a plurality of metallization layers 208 on the device layer 206. The structure 200 may be supported by a carrier wafer 210 on the front-side structure 204. The back-side structure 202 includes a stack of back-side conductive structures terminating at conductive bumps 212.

[0043] In an embodiment, device layer 206 includes field-effect transistors (FETs), such as nanowire-based (shown) or fin-based transistors. In one such embodiment, the FET is used for memory. In an embodiment, device layer 206 also includes trench contacts (TCNs), gate contacts (GCNs), and contact vias (VCXs). In an embodiment, as shown, device layer 206 is on a deep via (DV) layer of the positive side structure 204. In an embodiment, the plurality of metallization layers 208 include additional metal layers (e.g., M0-M12) and associated via layers (e.g., ...). Figure 2A The winning bidders are V0-V3.

[0044] In one embodiment, the back-side structure 202 includes multiple back-side metal layers (e.g., BMO-BM3) and associated vias. In another embodiment, the back-side structure 202 includes one or more power structures, such as ground metal lines (e.g., GM0 and GM1) or power metal lines. In yet another embodiment, the back-side structure 202 includes one or more capacitor structures, such as metal-insulator-metal (MIM) capacitors.

[0045] On the other hand, a recent proposal to decouple the dimensions of the gate, isolation, and contacts from the contacted polysilicon spacing has introduced a vertical transport field-effect transistor. While this new transistor architecture allows for optimization of gate length, spacer body thickness, and contact size without conventional constraints, it also introduces new trade-offs regarding how the bottom diffusion contacts.

[0046] As a contrasting structure Figure 2B An angled view of a vertical transmission field-effect transistor (FET) is shown.

[0047] refer to Figure 2B The vertical transfer FET 220 includes a channel structure 221, a gate stack 222 laterally surrounding the channel structure 221, and a gate contact 223 connected to the gate stack 222. A source region 224 is below the channel structure 221 and contacts the source contact 225. A drain region 228 is above the channel structure 221 and contacts the drain contact 229. Dark lines 226 indicate current flow.

[0048] As another contrasting structure Figure 2CAn angled view of a lateral transmission field-effect transistor (FET) is shown.

[0049] refer to Figure 2C The lateral transfer FET 230 includes a channel structure 231, a gate stack 232 above the channel structure 231, and a gate contact 233 connected to the gate stack 232. A source region 234 is above the channel structure 231 and contacts the source contact 235. A drain region (not shown) is above the channel structure 231 and contacts the drain contact 239. Dark lines 236 indicate current flow.

[0050] and Figure 2B and Figure 2C In contrast, according to embodiments of this disclosure, the vertical transfer FET (VTFET) is contacted in a manner that reduces parasitics (i.e., improves transistor performance) and increases transistor density.

[0051] like Figure 2B As shown, by using conductive contacts from the top side of the structure (e.g., Figure 2B The contact portion 225 in the diffuser is used to make contact with the lower diffusion (e.g., the source) of a conventional vertical transmission transistor. However, since current needs to flow laterally from the contact portion to the vertical fin, parasitic resistance can degrade transistor performance. Furthermore, parasitic capacitance exists between the diffuser contact and the gate contact, and also towards the upper diffuser contact. If resistive parasitics are reduced by decreasing the spacing, capacitive parasitics will increase; conversely, if the spacing is increased, the capacitive parasitics will increase. Moreover, if the capacitance is reduced by increasing the distance between the diffuser contact and the vertical fin, the achievable transistor density will decrease.

[0052] In contrast, embodiments of this disclosure disclose different approaches for back-side connections of the device to improve device performance and density. These embodiments can be implemented to address the challenges posed by the top-side contacts to the vertical transmission FET without compromising between reduced contact resistance, reduced parasitic capacitance to the gate and to the top diffusion contacts, and / or further increased achievable transistor density.

[0053] The embodiments described herein can be embodied in the following manner: a vertical fin having a gate contact and a top diffusion contact on the same fin, wherein the bottom diffusion contact of the fin is contacted from the back side of the substrate through a micro-through silicon via.

[0054] As a contrasting structure Figure 2D A cross-sectional view of a vertical transmission field-effect transistor (FET) is shown.

[0055] refer to Figure 2DThe vertical transmission field-effect transistor (FET) 240 includes a substrate 241, a source region 242, a gate structure 243, a drain 244, a channel structure 245 (e.g., a vertical fin), a silicon-on-insulator structure 246, and a trench isolation structure 247.

[0056] refer to Figure 2D This type of transistor has a diffused contact at the top of the vertical channel (in this case, the drain, but interchangeable with the source). The bottom of the vertical channel is connected to the substrate via a second contact on top of the substrate. Transistor performance can be degraded due to this resistive path through the substrate. However, if the contacts are placed closer to the vertical fins to reduce parasitic resistance, the increased parasitic capacitance between the source-gate and source-drain junctions can also lead to performance degradation. Furthermore, the increased spacing not only increases resistance but also increases the transistor's footprint, thus reducing the achievable transistor density.

[0057] In an embodiment, to overcome this bottleneck, the embodiments described herein provide a back-side connection to reduce parasitic resistance and capacitance by increasing the spacing between the source and other device pins.

[0058] In the first example, which is particularly suitable for power amplifier transistors Figure 2E A cross-sectional view of a vertical-transmission field-effect transistor (FET) according to an embodiment of the present disclosure is shown. In this example, the back-side metal serves as the source and is connected via a through-silicon via. Because this concept can be used for larger arrays, the via size is decoupled from the device spacing, and the concept is applicable to different via sizes. It should be understood that, in applications such as bonding... Figure 2A In the described structure, the following can be used Figure 2E Multiple vertical transmission FETs are used to replace the FETs in device layer 206.

[0059] refer to Figure 2E The vertical transmission field-effect transistor (FET) 250 includes a substrate 251, a back-side metal source structure 252, a gate structure 253, a drain 254, a channel structure 255 (e.g., a vertical fin array), a silicon-on-insulator structure 257, a trench isolation structure 256, and microvias or vias 258. In an embodiment, the metal source structure 252 is a pad on the back side, such as an interconnect pad and / or a bump. It should be understood that... Figure 2E It is a simplified representation of the back metal layer, and the intermediate metal layer (e.g., BM3, BM2, etc.) is not depicted.

[0060] In the second example using embedded power rails Figure 2FA cross-sectional view of another vertical transmission field-effect transistor (FET) according to another embodiment of this disclosure is shown. In this example, the stricter design rules of the buried power rail allow for the connection of a smaller device. By moving the source to the back side of the device, additional wiring resources are available for the gate and drain, which can be used to improve the device's performance and reliability (electromigration). It should be understood that, in applications such as... Figure 2A In the described structure, the following can be used Figure 2F Multiple vertical transmission FETs are used to replace the FETs in device layer 206.

[0061] refer to Figure 2F The vertical transmission field-effect transistor (FET) 260 includes a substrate 261, a source region 262, a gate structure 263, a drain 264, a channel structure 265 (e.g., a vertical fin), a silicon-on-insulator structure 266, a trench isolation structure 267, and a buried power rail 268.

[0062] Refer again Figure 2E and Figure 2F Both structures may have increased source-to-ground capacitance, but this does not pose a problem because they are connected to the power supply line. Such embodiments can also be combined with standard connection schemes.

[0063] In the third example using the standard connection scheme, Figure 2G A cross-sectional view of another vertical transmission field-effect transistor (FET) according to another embodiment of the present disclosure is shown. In this example, stacked transistors can be implemented, and the parasitic capacitance of the intermediate node within the stack can be minimized. The source and drain of the intermediate transistor can be swapped to further reduce parasitic capacitance; or they can remain unswapped to improve the matching performance of the device. It should be understood that, in applications such as combination Figure 2A In the described structure, the following can be used Figure 2G Multiple vertical transmission FETs are used to replace the FETs in device layer 206.

[0064] refer to Figure 2G The vertical transmission field-effect transistor (FET) 270 includes a substrate 271, a source region 272, a gate structure 273, a drain structure 274, a channel structure 275 (e.g., a vertical fin structure), a silicon-on-insulator structure 276, a trench isolation structure 277, and a buried power rail 278.

[0065] According to embodiments of this disclosure, conductive deep via structures are used between the front-side and back-side structures and are fabricated prior to epitaxial source or drain formation. For background purposes, a via structure extending beneath the source or drain structure can be referred to as a deep via structure. The embodiments described herein are directed to deep via formation prior to epitaxial source or drain growth. The embodiments described herein are directed to back-side power solutions for scaled cell sizes. According to embodiments of this disclosure, vertical transistors are fabricated in locations where deep via structures or back-side contacts would otherwise be fabricated. It should be understood that, unless otherwise stated, references to nanowires herein can refer to nanowires, nanoribbons, or even nanosheets.

[0066] It should be understood that, as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein can be silicon sub-fins, silicon nanowires, silicon nanoribbons, or silicon fins. As used throughout, a silicon layer or structure can be used to describe a silicon material composed of a very large amount (if not all) of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and therefore may include very small percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Thus, embodiments described herein with respect to silicon layers or structures may include silicon layers or structures containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or substances (e.g., Ge, C, or Sn). It should be understood that the silicon layers or structures described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0067] It should be understood that, as used throughout this disclosure, the sub-fins, nanowires, nanoribbons, or fins described herein can be silicon-germanium sub-fins, silicon-germanium nanowires, silicon-germanium nanoribbons, or silicon-germanium fins. As used throughout, a silicon-germanium layer or structure can be used to describe a silicon-germanium material composed of a majority (e.g., at least 5% of both) of silicon and germanium. In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon-germanium layer or structure comprises approximately 60% germanium and approximately 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer or structure comprises approximately 30% germanium and approximately 70% silicon (Si). 70 Ge 30It should be understood that, in practice, 100% pure silicon-germanium (generally referred to as SiGe) may be difficult to form, and therefore may include a very small percentage of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may “contaminate” SiGe during diffusion during post-deposition processing. Thus, the embodiments described herein with respect to silicon-germanium layers or structures may include silicon-germanium layers or structures containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or substances (e.g., carbon or tin). It should be understood that silicon-germanium layers or structures as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0068] It should be understood that the above text, in combination with... Figures 2E-2G The described integrated circuit structure can be co-integrated with other back-side exposed integrated circuit structures. Alternatively or concurrently, a combination of... Figures 2E-2G The described process is used to fabricate other integrated circuit structures. As an example of a back-side exposed device, Figure 3 A cross-sectional view along the gate line of a non-planar integrated circuit structure according to an embodiment of the present disclosure is shown.

[0069] refer to Figure 3 The semiconductor structure or device 300 includes a non-planar active region (e.g., a solid fin structure including an extended fin portion 304 and a sub-fin region 305) located within a trench isolation region 306. In another embodiment, as shown by dashed lines, the non-planar active region is partitioned into nanowires (e.g., nanowires 304A and 304B) above the sub-fin region 305 instead of a solid fin. In either case, for ease of description of the non-planar integrated circuit structure 300, the non-planar active region 304 is hereinafter referred to as the extended fin portion. It should be understood that in one embodiment, no body substrate is coupled to the sub-fin region 305.

[0070] Gate line 308 is disposed over an extension 304 of a non-planar active region (including, if applicable, surrounding nanowires 304A and 304B) and a portion of a trench isolation region 306. As shown, gate line 308 includes a gate electrode 350 and a gate dielectric layer 352. In one embodiment, gate line 308 may further include a dielectric capping layer 354. From this viewpoint, it can also be seen that gate contact 314 and overlying gate contact via 316, together with overlying metal interconnect 360, are all disposed within an interlayer dielectric stack or layer 370. Figure 3 From another perspective, it can also be seen that in one embodiment, the gate contact 314 is disposed above the trench isolation region 306, but not above the non-planar active region.

[0071] In an embodiment, the semiconductor structure or device 300 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is constituted by or formed in a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 308 at least surrounds the top surface and a pair of sidewalls of the three-dimensional body.

[0072] For example Figure 3 As depicted, in one embodiment, interface 380 exists between the protruding fin portion 304 and the sub-fin region 305. Interface 380 may be a transition region located between the doped sub-fin region 305 and the lightly doped or undoped upper fin portion 304. In one such embodiment, each fin is approximately 10 nanometers wide or less, and the sub-fin dopant is supplied from an adjacent solid-state doped layer located at the sub-fin site. In a particular such embodiment, each fin is less than 10 nanometers wide. In another embodiment, the sub-fin region is a dielectric material, formed by recessing the fin via wet or dry etching and filling the recessed cavity with a conformal or flowable dielectric.

[0073] although Figure 3 Not depicted, but it should be understood that the source or drain region of the protruding fin portion 304, or the source or drain region adjacent to the protruding fin portion 304, is located on either side of the gate line 308, i.e., inside or outside the page. In one embodiment, the source or drain region is a doped portion of the initial material of the protruding fin portion 304. In another embodiment, the material of the protruding fin portion 304 is removed and replaced by another semiconductor material (e.g., by epitaxial deposition) to form discrete epitaxial bumps or non-discrete epitaxial structures. In either embodiment, the source or drain region may extend below the height of the dielectric layer of the trench isolation region 306, i.e., into the sub-fin region 305. According to embodiments of this disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below interface 380) suppresses source-to-drain leakage through this portion of the bulk semiconductor fin.

[0074] Refer again Figure 3In one embodiment, the fins 304 / 305 (and possibly nanowires 304A and 304B) are composed of crystalline silicon, silicon / germanium, or a germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, or combinations thereof. In one embodiment, the concentration of silicon atoms is greater than 93%. In another embodiment, the fins 304 / 305 are composed of a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. The trench isolation region 306 may be composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0075] Gate line 308 may be formed of a gate electrode stack including a gate dielectric layer 352 and a gate electrode layer 350. In an embodiment, the gate electrode of the gate electrode stack is formed of a metal gate, and the gate dielectric layer is formed of a high-k material. For example, in one embodiment, the gate dielectric layer is formed of, but is not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer may include a layer of native oxide formed from the top layers of the substrate fin 304. In an embodiment, the gate dielectric layer is formed of a top high-k portion and a lower portion formed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is formed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0076] In one embodiment, the gate electrode is formed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a particular embodiment, the gate electrode is formed of a non-work function filling material formed above a metal work function setting layer. Depending on whether the transistor is a PMOS or NMOS transistor, the gate electrode layer may be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). A P-type metal layer will enable the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to: hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may consist of a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments of this disclosure, the gate electrode may consist of a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0077] The spacer associated with the gate electrode stack can be made of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (e.g., self-aligned contacts) or contributing to the isolation of the permanent gate structure from adjacent conductive contacts. For example, in one embodiment, the spacer is made of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0078] The gate contact 314 and the overlying gate contact via 316 may be made of a conductive material. In an embodiment, one or more of the contacts or vias may be made of a metallic material. The metallic material may be a pure metal (e.g., tungsten, nickel, or cobalt) or an alloy (e.g., a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material)).

[0079] In one embodiment (though not shown), a contact pattern is formed that is substantially perfectly aligned to the existing gate pattern 308, while eliminating the use of photolithography steps with extremely tight registration budgets. In one such embodiment, the self-alignment method enables the use of inherently highly selective wet etching (e.g., compared to dry or plasma etching in conventional implementations) to generate the contact openings. In another embodiment, the contact pattern is formed by utilizing the existing gate pattern in conjunction with a contact plugging photolithography operation. In yet another embodiment, this method eliminates the need for other critical photolithography operations used in conventional methods to generate the contact pattern. In another embodiment, the trench contact mesh is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after the gate grid patterning but before the gate grid notch.

[0080] In an embodiment, providing structure 300 relates to fabricating a gate stack body structure 308 using a gate replacement process. In such an approach, a dummy gate material (e.g., polysilicon or silicon nitride pillar material) can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, in contrast to the earlier fabrication. In an embodiment, the dummy gate is removed using a dry etching or wet etching process. In one embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is made of polysilicon or amorphous silicon and is removed using a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is made of silicon nitride and is removed using a wet etching process including aqueous phosphoric acid.

[0081] Refer again Figure 3 The arrangement of the semiconductor structure or device 300 places the gate contacts over an isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure in which the contacts are formed over an active region (e.g., over a sub-fin 305) and located in the same layer as the trench contact via, on a portion of the gate electrode.

[0082] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of this disclosure. For example, in one embodiment, a dummy gate does not need to be formed before fabricating the gate contact on the active portion of the gate stack. The gate stack described herein may actually be a permanent gate stack formed initially. Furthermore, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in an embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic cells or memory, or a bipolar transistor. Furthermore, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a tri-gate device, a separately accessed dual-gate device, a gate all-around (GAA) device, a nanowire device, a nanoribbon device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0083] In embodiments, as used throughout this specification, the interlayer dielectric (ILD) material comprises, or includes, layers of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0084] In embodiments, and as used throughout this specification, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term "metal" includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed of several layers, including conductive substrates and filler layers. Any suitable deposition process (e.g., electroplating, chemical vapor deposition, or physical vapor deposition) can be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material, such as, but not limited to: Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes referred to in the art as traces, wires, lines, metals, or simply as interconnects.

[0085] In embodiments, as used throughout this specification, the hard mask material, capping layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, capping, or plug materials can be used in different regions to provide different growth or etching selectivity relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, capping layer, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride), or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, capping, or plug layers known in the art may be used. The hard mask, capping, or plug layers can be formed by CVD, PVD, or other deposition methods.

[0086] In this embodiment, as used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), EUV, and / or EBDW lithography. Positive or negative photoresists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography mask portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment, the topography mask portion is a carbon hard mask (CHM) layer, and the antireflective coating layer is a silicon ARC layer.

[0087] In another aspect, the integrated circuit structure described herein can be fabricated using a back-side exposure manufacturing method for front-side structures. In some exemplary embodiments, the back-side exposure of transistors or other device structures requires wafer-level back-side processing. Compared to conventional TSV-type techniques, the back-side exposure of transistors as described herein can be performed at device cell densities and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to substantially remove all donor substrates on which device layers are disposed during front-side device processing. Thus, micrometer-deep TSVs become unnecessary when the thickness of the semiconductor in the device cell may be only tens or hundreds of nanometers after the back-side exposure of the transistors.

[0088] The exposure techniques described in this paper enable a shift in manufacturing paradigms from "bottom-up" device fabrication to "center-out" fabrication, where "center" refers to any layer that is employed in front-side fabrication, exposed from the back side, and re-employed in back-side fabrication. While relying primarily on front-side processing, fabricating both the front and exposed back sides of the device structure can address many of the challenges associated with manufacturing 3D ICs.

[0089] For example, as described below Figures 4A-4H and Figures 5A-5HAs shown, methods for exposing the back side of the transistor can be employed, for example, to remove at least a portion of the carrier layer and intercalary layer of the donor-host substrate assembly. The process flow begins at the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP paste known to be suitable for thinning the semiconductor can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0090] In some embodiments, prior to the steps described above, the carrier layer is cleaved along a fracture plane substantially parallel to the intercalary layer. Cleavage or fracture processes can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case of a carrier layer thickness of 400-900 μm, 100-700 μm can be cleaved away by any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer at a desired uniform target depth with a fracture plane. After such a cleavage process, the remaining thickness of the carrier layer in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the absence of fracture, grinding, polishing, and / or etching operations can be used to remove a thicker carrier layer.

[0091] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point at which the back surface of the donor substrate has advanced to near the device layer. Any known endpoint detection technique suitable for detecting the transition between the materials used in the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on changes in light absorption or emission detected on the back surface of the donor substrate during polishing and / or etching. In some other embodiments, the endpoint criteria are associated with changes in light absorption or emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelengths associated with carrier layer etching byproducts can vary as a function of the different components of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of the material in the byproducts of polishing or etching the back surface of the donor substrate. For example, the processed byproducts can be sampled using a quadrupole mass analyzer, and the change in mass can be related to the different components of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the frictional force between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0092] Since inhomogeneities in the carrier removal process can be mitigated by the difference in etching rates between the carrier layer and the intercalary layer, the detection of the intercalary layer can be enhanced when the removal process is selective for the carrier layer relative to the intercalary layer. If the grinding, polishing, and / or etching operations remove the intercalary layer at a rate sufficiently lower than that of the carrier layer, the detection can even be skipped. Without an endpoint criterion, grinding, polishing, and / or etching operations of a predetermined fixed duration can be stopped on the intercalary layer material if the thickness of the intercalary layer is sufficient for the selectivity of the etching. In some examples, the carrier etching rate:intercalary layer etching rate is 3:1 to 10:1 or greater.

[0093] After exposing the intercalary layer, at least a portion of the intercalary layer can be removed. For example, one or more component layers within the intercalary layer can be removed. The thickness of the intercalary layer can be uniformly removed, for example, by polishing. Alternatively, a mask or blanket etching process can be used to remove the thickness of the intercalary layer. This process can employ the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intercalary layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that is more favorable for the removal of the intercalary layer than for the removal of the device layer. When removing an intercalary layer thickness of less than a few hundred nanometers, the removal process can be relatively slow, optimized for uniformity across the entire wafer, and can be more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, use a paste that provides very high selectivity (e.g., 100:1-300:1 or greater) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) surrounding the device layer and embedded within the intercalary layer (e.g., as electrical isolation between adjacent device regions).

[0094] For embodiments in which the device layer is exposed by completely removing the intervening layer, back-side processing can begin on the exposed back side of the device layer or on a specific device region therein. In some embodiments, back-side device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and a device region (e.g., a source or drain region) previously fabricated in the device layer.

[0095] In some embodiments where wet and / or plasma etching is used to recess the back side of the carrier layer, intermediary layer, or device layer, such etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back side surface of the device layer. As further described below, patterning can be within a device cell (i.e., "intra-cell" patterning) or can span across device cells (i.e., "inter-cell" patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediary layer is used as a hard mask for patterning the back side device layer. Therefore, the mask etching process can precede the corresponding mask device layer etching.

[0096] The fabrication scheme described above can produce a donor-body substrate assembly including an IC device, wherein the back side of the intervening layer, the back side of the device layer, and / or the back side of one or more semiconductor regions are located within the device layer, and / or the front metallization is exposed. Further backside processing can then be performed on any of these exposed regions during downstream processing.

[0097] According to one or more embodiments of this disclosure, a dual-side device fabrication scheme can be practiced at the wafer level to achieve back-side access to separated source or drain contact structures. In some exemplary embodiments, a wafer with a large formal substrate (e.g., a diameter of 300 or 450 mm) can be fabricated. In exemplary fabrication schemes, a donor substrate including a device layer is provided. In some embodiments, the device layer is a semiconductor material used in an IC device. As an example, in a transistor device (e.g., a field-effect transistor (FET)), a channel semiconductor is formed from a semiconductor device layer. As another example, for an optical device (e.g., a photodiode), a drift and / or gain semiconductor is formed from a device layer. Device layers can also be used in passive structures having IC devices. For example, an optical waveguide can be made of a semiconductor patterned from a device layer.

[0098] In some embodiments, the donor substrate comprises a stack of material layers. Such a material stack can facilitate the subsequent formation of an IC device stratum that includes a device layer but lacks the donor substrate. In an exemplary embodiment, the donor substrate includes a carrier layer separated from the device layer by one or more intermediary material layers. The carrier layer provides mechanical support during front-side processing of the device layer. The carrier can also provide a basis for crystallinity in the semiconductor device layer. The intermediary layers (multiple) can facilitate the removal of the carrier layer and / or exposure of the back side of the device layer.

[0099] Front-side fabrication operations are then performed to form a device structure comprising one or more regions in the device layer. Any known front-side fabrication technique can be used to form any known IC device, and exemplary embodiments are further described elsewhere herein. The donor substrate is then front-side connected to the host substrate to form a device-host assembly. The host substrate provides front-side mechanical support during back-side fabrication of the device layer. The host substrate may also need to fabricate IC devices and their interconnecting integrated circuits on the donor substrate. In such embodiments, the connection between the host substrate and the donor substrate may also require forming a 3D interconnect structure via hybrid (dielectric / metal) bonding. Any known host substrate and wafer-level interconnection technique can be used.

[0100] The process continues when the back side of the device layer is exposed by removing at least a portion of the carrier layer. In some other embodiments, portions of any intervening layers and / or front-side material deposited on the device layer may also be removed during the exposure operation. As described elsewhere herein in the context of some exemplary embodiments, intervening layers can facilitate very uniform exposure of the back side of the device layer, for example, acting as one or more etch markers or etch stops employed in a wafer-level back-side exposure process. The device layer surface exposed from the back side is processed to form a double-sided device layer. The native material (e.g., any of those native materials in the donor substrate) in contact with the device region interface may then be replaced with one or more non-native materials. For example, a portion of the semiconductor device layer or intervening layer may be replaced with one or more other semiconductor, metallic, or dielectric materials. In some other embodiments, portions of the front-side material removed during the exposure operation may also be replaced. For example, during back-side deprocessing / reprocessing of the front-side device, portions of dielectric spacers, gate stacks, or contact metallizations formed during front-side device fabrication may be replaced with one or more other semiconductor, metallic, or dielectric materials. In some other embodiments, the second device layer or metal interlayer is bonded to the exposed back side.

[0101] The process described above provides a device layer-body substrate assembly. The device layer-body assembly can then be further processed. For example, any known technique can be used to individualize and package the device layer-body substrate assembly. When the body substrate is entirely sacrificial, packaging the device layer-body substrate assembly may require separating the body substrate from the device layers. When the body substrate is not entirely sacrificial (e.g., where the body substrate also includes device layers), the device layer-body assembly output can be fed back as a body substrate input during subsequent iterations of the above process. Thus, for example, iterations of the above method can form wafer-level assemblies with any number of dual-side device layers, each only tens or hundreds of nanometers thick. In some embodiments, and as further described elsewhere herein, electrical testing is performed on one or more device cells located within the device layers, for example, as yield control points in the fabrication of the dual-side device layer wafer-level assembly. In some embodiments, electrical testing requires back-side device probing.

[0102] Figures 4A-4H A plan view of a substrate fabricated using a dual-side device fabrication method according to some embodiments is shown. Figures 5A-5H A cross-sectional view of a substrate fabricated using a dual-side device fabrication method according to some embodiments is shown.

[0103] like Figure 4A and Figure 5AAs shown, the donor substrate 401 includes a plurality of IC dies 411 arranged in arbitrary spatial order on the front-side wafer surface. The front-side processing of the IC dies 411 can be performed following any technique used to form any device structure. In an exemplary embodiment, the die 411 includes one or more semiconductor regions located within a device layer 415. An intermediary layer 410 separates the device layer 415 from the carrier layer 405. In an exemplary embodiment, the intermediary layer 410 is in direct contact with both the carrier layer 405 and the device layer 415. Alternatively, one or more spacer layers may be disposed between the intermediary layer 410 and the device layer 415 and / or the carrier layer 405. The donor substrate 401 may also include other layers, for example, disposed above the device layer 415 and / or below the carrier layer 405.

[0104] Device layer 415 may include one or more layers of any device material composition known to be suitable for a particular IC device (e.g., but not limited to: transistors, diodes, and resistors). In some exemplary embodiments, device layer 415 includes one or more layers of group IV (i.e., group IUPAC 14) semiconductor materials (e.g., Si, Ge, SiGe), group III-V semiconductor materials (e.g., GaAs, InGaAs, InAs, InP), or group III-N semiconductor materials (e.g., GaN, AlGaN, InGaN). Device layer 415 may also include one or more semiconductor transition metal dichalcogenide (TMD or TMDC) layers. In other embodiments, device layer 415 includes one or more graphene layers or graphene material layers having semiconductor properties. In still other embodiments, device layer 415 includes one or more oxide semiconductor layers. Exemplary oxide semiconductors include oxides of transition metals (e.g., groups IUPAC 4-10) or post-transition metals (e.g., groups IUPAC 11-14). In advantageous embodiments, the oxide semiconductor includes at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sr, Cr, Co, V, or Mo. The metal oxide can be a secondary oxide (A₂O), a primary oxide (AO), a secondary oxide (AO₂), a secondary oxide (ABO₃), or mixtures thereof. In other embodiments, device layer 415 includes one or more layers of magnetic, ferromagnetic, or ferroelectric material. For example, device layer 415 may include one or more layers of any material known to be suitable for tunnel junction devices (e.g., but not limited to, magnetic tunnel junction (MTJ) devices).

[0105] In some embodiments, device layer 415 is substantially single-crystal. Although single-crystal, it may contain a significant number of crystal defects. In other embodiments, device layer 415 is amorphous or nanocrystalline. Device layer 415 can be of any thickness (e.g., Figure 5A(z-dimensional in the original text). In some exemplary embodiments, because the functional semiconductor regions of die 411 constructed on or embedded in device layer 415 do not need to extend through the entire thickness of device layer 415, device layer 415 has a thickness greater than the z-thickness of at least some of the semiconductor regions used by die 411. In some embodiments, the semiconductor regions of die 411 are only disposed in... Figure 5A Within the top thickness of the device layer 415, defined by the dashed line 412. For example, the semiconductor region of the die 411 may have a z-thickness of 200-300 nm or less, while the device layer may have a z-thickness of 700-1000 nm or greater. Thus, a device layer thickness of approximately 600 nm can separate the semiconductor region of the die 411 from the intermediary layer 410.

[0106] The carrier layer 405 may have the same material composition as the device layer 415, or it may have a different material composition. In embodiments where the carrier layer 405 and device layer 415 have the same composition, the two layers can be identified by their position relative to the intervening layer 410. In some embodiments where device layer 415 is a crystalline Group IV, III-V, or III-N semiconductor, the carrier layer 405 is the same crystalline Group IV, III-V, or III-N semiconductor as device layer 415. In alternative embodiments, where device layer 415 is a crystalline Group IV, III-V, or III-N semiconductor, the carrier layer 405 is a crystalline Group IV, III-V, or III-N semiconductor different from device layer 415. In still other embodiments, the carrier layer 405 may include or may be the material transferred to or grown on device layer 415. For example, the carrier layer may include one or more amorphous oxide layers (e.g., glass) or crystalline oxide layers (e.g., sapphire), polymer sheets, or any (multiple) materials deposited or laminated during IC device fabrication to a structural support known to be suitable as a carrier. Carrier layer 405 may be of any thickness as a function of the carrier material properties and the substrate diameter (e.g., Figure 5A (z dimension in the original text). For example, if the carrier layer 405 is a large-size (e.g., 300-450 mm) semiconductor substrate, the carrier layer thickness can be 700-1000 μm or greater.

[0107] In some embodiments, one or more intermediary layers 410 are disposed between the carrier layer 405 and the device layer 415. In some exemplary embodiments, the intermediary layer 410 differs in composition from the carrier layer 405, such that it can act as a marker detectable during subsequent removal of the carrier layer 405. In some such embodiments, the intermediary layer 410 has a composition that will be etched at a significantly slower rate than the carrier layer 405 when exposed to the etchant used for the carrier layer 405 (i.e., the intermediary layer 410 acts as an etch stop for the carrier layer etching process). In other embodiments, the intermediary layer 410 has a composition different from that of the device layer 415. For example, the intermediary layer 410 may be a metal, semiconductor, or dielectric material.

[0108] In some exemplary embodiments where at least one of the carrier layer 405 and the device layer 415 is a crystalline semiconductor, the intermediary layer 410 is also a crystalline semiconductor layer. The intermediary layer 410 may also have the same crystallinity and crystal orientation as the carrier layer 405 and / or the device layer 415. Such embodiments, compared to alternative embodiments (where the intermediary layer 410 is a material that needs to be bonded (e.g., thermo-bonded) to the intermediary layer 410 and / or the carrier layer 405), can have the advantage of reduced donor substrate costs.

[0109] For embodiments where the intercalary layer 410 is a semiconductor, one or more of the basic semiconductor lattice elements, alloy composition, or impurity concentration may vary at least between the carrier layer 405 and the intercalary layer 410. In some embodiments where at least the carrier layer 405 is a group IV semiconductor, the intercalary layer 410 may also be a group IV semiconductor, but with a different group IV element or alloy and / or doped with impurity substances to a different impurity level than that of the carrier layer 405. For example, the intercalary layer 410 may be a silicon-germanium alloy epitaxially grown on a silicon carrier. In such embodiments, the pseudocrystalline intercalary layer may be heteroepitaxially grown to any thickness below a critical thickness. Alternatively, the intercalary layer 410 may be a relaxation buffer layer having a thickness greater than a critical thickness.

[0110] In other embodiments, where at least the carrier layer 405 is a III-V semiconductor, the intermediate layer 410 may also be a III-V semiconductor, but a different III-V alloy and / or doped with impurity substances to a different impurity level than that of the carrier layer 405. For example, the intermediate layer 410 may be an AlGaAs alloy epitaxially grown on a GaAs carrier. In some other embodiments where both the carrier layer 405 and the device layer 415 are crystalline semiconductors, the intermediate layer 410 is also a crystalline semiconductor layer, and may also have the same crystallinity and crystal orientation as the carrier layer 405 and / or the device layer 415.

[0111] In embodiments where the carrier layer 405 and the intermediate layer 410 are the same or different basic semiconductor lattice elements, impurity dopants can distinguish the carrier and the intermediate layer. For example, the intermediate layer 410 and the carrier layer 405 can both be silicon crystals, wherein the intermediate layer 410 lacks the impurities present in the carrier layer 405, or is doped with impurities not present in the carrier layer 405, or the impurities present in the carrier layer 405 are doped to different levels. Distinguishing impurities can impart etching selectivity between the carrier layer and the intermediate layer, or introduce only detectable substances.

[0112] Since impurities can provide any basis for detection of intercalary layer 410 during subsequent carrier removal, intercalary layer 410 can be doped with electrically active impurities (i.e., making it an n-type or p-type semiconductor), or it can be undoped. Exemplary electrically active impurities used for some semiconductor materials include group III elements (e.g., B) and group IV elements (e.g., P). Any other element can be used as an electrically inactive substance. The concentration of impurity dopant within intercalary layer 410 only needs to differ from the concentration of impurity dopant in carrier layer 405 by a sufficient amount to enable detection; this amount can be predetermined as a function of the detection technique and detector sensitivity.

[0113] As further described elsewhere herein, intermediary layer 410 may have a different composition than device layer 415. In some such embodiments, intermediary layer 410 may have a different bandgap than device layer 415. For example, intermediary layer 410 may have a wider bandgap than device layer 415.

[0114] In embodiments where the intermediate layer 410 includes a dielectric material, the dielectric material may be an inorganic material (e.g., SiO, SiN, SiON, SiOC, hydrosilsesquioxane, methylsilsesquioxane) or an organic material (polyimide, polynorbornene, benzocyclobutene). For some dielectric embodiments, the intermediate layer 410 may be formed as an embedding layer (e.g., by implanting oxygen into the silicon device and / or carrier layer of SiOx). Other embodiments of the dielectric intermediate layer may require bonding (e.g., thermoforming) the carrier layer 405 to the device layer 415. For example, in the case where the donor substrate 401 is a semiconductor-on-oxide (SOI) substrate, either or both of the carrier layer 405 and the device layer 415 may be oxidized and bonded together to form the SiO intermediate layer 410. Similar bonding techniques can be used for other inorganic or organic dielectric materials.

[0115] In some other embodiments, the intermediary layer 410 includes two or more materials laterally spaced within the layer. The two or more materials may include a dielectric and a semiconductor, a dielectric and a metal, a semiconductor and a metal, a dielectric and a metal, two different dielectrics, two different semiconductors, or two different metals. Within such an intermediary layer, the first material may form islands around an extension of the second material that extends through the thickness of the intermediary layer. For example, the intermediary layer may include a field-isolating dielectric that extends around an extension of the semiconductor that extends through islands within the thickness of the intermediary layer. The semiconductor may be epitaxially grown inside or outside the openings of the patterned dielectric, or the dielectric material may be deposited within the openings of the patterned semiconductor.

[0116] In some exemplary embodiments, semiconductor features, such as fins or mesas, are etched into the front surface of the semiconductor device layer. Subsequently, for example, after any known shallow trench isolation (STI) process, the trenches surrounding these features can be backfilled with an isolation dielectric. The back-side carrier removal process can be terminated with one or more semiconductor features or isolation dielectrics (e.g., as a back-side exposure etch stop). In some embodiments, the exposure of the trench isolation dielectric can be stopped, significantly delayed, or trigger a detectable signal to terminate back-side carrier polishing. For example, after exposing the (bottom) surface of the trench isolation dielectric surrounding the semiconductor features including the device layer, CMP polishing of the carrier semiconductor using a slurry (which has a higher selectivity for removing the carrier semiconductor (e.g., Si) than removing the isolation dielectric (e.g., SiO) can be significantly slowed down. Because the device layer is disposed on the front side of the intermediary layer, the device layer does not need to be directly exposed to the back-side exposure process.

[0117] Notably, in embodiments where the intermediary layer comprises both a semiconductor and a dielectric, the intermediary layer thickness can be significantly greater than the critical thickness associated with lattice mismatch between the intermediary layer and the carrier. An intermediary layer thickness below the critical thickness may be insufficient to accommodate the non-uniformity of wafer-level back-side exposure processes, but embodiments with greater thickness can advantageously increase the back-side exposure process window. Embodiments with pinhole dielectrics can further facilitate subsequent separation between the carrier layer and the device layer and improve crystal quality within the device layer.

[0118] The semiconductor material located within the intermediary layer, which includes both the semiconductor and the dielectric, can also be homoepitaxial. In some exemplary embodiments, the silicon epitaxial device layer is grown through a pinhole dielectric disposed on the silicon carrier layer.

[0119] continue Figure 4A and Figure 5AAs described, the intermediary layer 410 can also be metal. For such embodiments, the metal can be any component known to be suitable for bonding to the carrier layer 405 or the device layer 415. For example, either or both of the carrier layer 405 and the device layer 415 can be made of a metal (e.g., but not limited to, Au or Pt) and subsequently bonded together, for example, to form an Au or Pt intermediary layer 410. Such a metal can also be part of the intermediary layer, which also includes a patterned dielectric surrounding a metal feature.

[0120] Intermediate layer 410 can be of any thickness (e.g., Figure 5A (z-height in the original text). The intermediary layer should be thick enough to ensure that the carrier removal operation can be reliably terminated before exposing the device region and / or device layer 415. Exemplary thicknesses of the intermediary layer 410 range from hundreds of nanometers to several micrometers and can vary, for example, as a function of the amount of carrier material to be removed, the uniformity of the carrier removal process, and the selectivity of the carrier removal process. For embodiments where the intermediary layer has the same crystallinity and crystal orientation as the carrier layer 405, the carrier layer thickness can be reduced to the thickness of the intermediary layer 410. In other words, the intermediary layer 410 can be the top portion of a 700-1000 μm thick group IV crystalline semiconductor substrate that is also used as the carrier layer. In pseudocrystalline heteroepitaxial embodiments, the intermediary layer thickness can be limited to a critical thickness. For heteroepitaxial intermediary layer embodiments employing aspect ratio trapping (ART) or another fully relaxable buffer architecture, the intermediary layer can have any thickness.

[0121] like Figure 4B and Figure 5B As further shown, donor substrate 401 may be connected to host substrate 402 to form donor-host substrate assembly 403. In some exemplary embodiments, the front surface of donor substrate 401 is connected to the surface of host substrate 402 such that device layer 415 is located proximal to host substrate 402 and carrier layer 405 is located distal to host substrate 402. Host substrate 402 may be any substrate known to be suitable for connection to device layer 415 and / or fabrication of front stacks on device layer 415. In some embodiments, host substrate 402 includes one or more additional device layers. For example, host substrate 402 may also include one or more device layers (not depicted). Host substrate 402 may include an integrated circuit, with interconnects between IC devices fabricated in the device layers of host substrate 402, in which case connecting device layer 415 to host substrate 402 may also require forming a 3D interconnect structure via wafer-level bonding.

[0122] Although Figure 5BNot described in detail, but any number of front layers, such as interconnect metallization layers and interlayer dielectric (ILD) layers, may exist between device layer 415 and host substrate 402. Any technique can be used to connect host substrate 402 and donor substrate 401. In some exemplary embodiments further described elsewhere herein, donor substrate 401 is connected to host substrate 402 by metal-metal, oxide-oxide, or hybrid (metal / oxide-metal / oxide) thermocompression bonding.

[0123] When the main substrate 402 faces the device layer 415 located on the side opposite to the carrier layer 405, as Figure 4C and Figure 5C As further shown, at least a portion of the carrier layer 405 can be removed. With the entire carrier layer 405 removed, the donor-host substrate assembly 403 maintains a very uniform thickness and has planar back and front surfaces. Alternatively, the carrier layer 405 can be masked, and only the intermediary layer 410 located in the unmasked sub-regions can be exposed to form a non-planar back surface. Figure 4C and Figure 5C In the exemplary embodiment shown, the carrier layer 405 is removed from the entire back surface of the donor-host substrate assembly 403. The carrier layer 405 can be removed, for example, by cleaving, grinding, and / or polishing (e.g., chemical mechanical polishing) and / or wet chemical etching and / or plasma etching through the thickness of the carrier layer to expose the intermediary layer 410. One or more operations can be employed to remove the carrier layer 405. Advantageously, the removal operations(s) can be terminated based on the duration or an endpoint signal sensitive to the exposure of the intermediary layer 410.

[0124] In other embodiments, such as Figure 4D and Figure 5D As shown, at least a portion of the intermediary layer 410 is also etched to expose the back side of the device layer 415. After the intermediary layer 410 has served as a stop portion and / or a trigger for the end of the carrier layer etch, at least a portion of the intermediary layer 410 can be removed. In the case of removing the entire intermediary layer 410, the donor-host substrate assembly 403 maintains a very uniform device layer thickness, wherein the planar back and front surfaces provided by the intermediary layer 410 are much thinner than the carrier layer. Alternatively, the intermediary layer 410 can be masked, and only the device layer 415 located in the unmasked sub-region can be exposed, thereby forming a non-planar back surface. Figure 4D and Figure 5DIn the exemplary embodiment shown, the intermediate layer 410 is removed from the entire back surface of the donor-host substrate assembly 403. The intermediate layer 410 can be removed, for example, by polishing (e.g., chemical mechanical polishing) and / or blanket wet chemical etching and / or blanket plasma etching through the thickness of the intermediate layer, thereby exposing the device layer 415. One or more operations may be employed to remove the intermediate layer 410. Advantageously, the removal operations(s) may be terminated based on the duration or an endpoint signal sensitive to the exposure of the device layer 415.

[0125] In some other embodiments, such as Figure 4E and Figure 5E As shown, device layer 415 is partially etched to expose the back side of the device structure previously formed during front-side processing. At least a portion of device layer 415 may be removed after it has been used to fabricate one or more device semiconductor regions and / or after it has served as an intermediary layer etch stop or end trigger. With device layer 415 thinned over the entire substrate area, the donor-host substrate assembly 403 maintains a very uniformly reduced thickness and has planar back and front surfaces. Alternatively, device layer 415 may be masked, and device structures (e.g., device semiconductor regions) located only in unmasked sub-regions may be selectively exposed, thereby forming a non-planar back-side surface. Figure 4E and Figure 5E In the exemplary embodiment shown, the device layer 415 is thinned over the entire back surface of the donor-host substrate assembly 403. The device layer 415 can be thinned, for example, by polishing (e.g., chemical mechanical polishing) and / or wet chemical etching and / or plasma etching through the thickness of the device layer to expose one or more device semiconductor regions, and / or one or more other device structures (e.g., front-side device terminal contact metallization, spacer dielectric, etc.) previously formed during front-side processing. One or more operations can be employed to thin the device layer 415. Advantageously, the device layer thinning can be terminated based on a duration or an endpoint signal sensitive to the exposure of patterned features within the device layer 415. For example, in the case where device isolation features (e.g., shallow trench isolation) are formed during front-side processing, back-side thinning of the device layer 415 can be terminated after exposure of the isolation dielectric material.

[0126] Non-native material layers can be deposited on the back surface of the intervening layer, on the device layer and / or on specific device areas within the device layer 415, and / or on one or more other device structures (e.g., front device terminal contact metallization, spacer dielectric, etc.). One or more materials exposed from the back side can be covered by a non-native material layer or replaced by such a material. Figure 4F and Figure 5FIn some embodiments shown, a non-native material layer 420 is deposited on device layer 415. The non-native material layer 420 may have a composition and / or microstructure different from that of the material removed to expose the back side of the device layer. For example, in the case of removing intermediary layer 410 to expose device layer 415, the non-native material layer 420 may be another semiconductor with a composition or microstructure different from that of intermediary layer 410. In some such embodiments where device layer 415 is a III-N semiconductor, the non-native material layer 420 may also be a III-N semiconductor of the same or different composition regenerated on the exposed back side surface of a III-N device region. This material may be epitaxially regrown from the exposed III-N device region, for example, with a better crystal quality than the removed material, and / or to induce strain in the device layer and / or within the device region, and / or to form a vertical (e.g., z-dimensional) stack of device semiconductor regions suitable for stacked devices.

[0127] In some other embodiments where device layer 415 is a III-V semiconductor, non-native material layer 420 may also be a III-V semiconductor of the same or different composition regenerated on the exposed back-side surface of a III-V device region. This material may be epitaxially regrown from the exposed III-V device region, for example, to have a relatively better crystal quality than the removed material, and / or to induce strain in the device layer or a specific device region located within the device layer, and / or to form a vertical stack of device semiconductor regions suitable for stacking devices.

[0128] In some other embodiments where device layer 415 is a group IV semiconductor, non-native material layer 420 may also be a group IV semiconductor of the same or different composition regenerated on the exposed back-side surface of a group IV device region. This material may be epitaxially regrown from the exposed group IV device region, for example, to have a relatively better crystal quality than the removed material, and / or to induce strain within the device region, and / or to form a stack of device semiconductor regions suitable for stacking devices.

[0129] In some other embodiments, the non-native material layer 420 is a dielectric material, such as, but not limited to, SiO, SiON, SiOC, hydrogen silsesquioxane, methyl silsesquioxane, polyimide, polynorbornene, benzocyclobutene, etc. Depositing such a dielectric can be used to electrically isolate various device structures (e.g., semiconductor device regions) that may have been previously formed during processing on the front side of the donor substrate 401.

[0130] In some other embodiments, the non-native material layer 420 is a conductive material, such as any elemental metal or metal alloy known to be suitable for contacting one or more surfaces of a device region exposed from the back side. In some embodiments, the non-native material layer 420 is a metallization suitable for contacting a device region exposed from the back side (e.g., a transistor source or drain region). In embodiments, intermetallic contacts can be formed, such as NixSiy, TixSiy, Ni:Si:Pt, TiSi, CoSi, etc. Alternatively, implantation can be used to achieve robust contacts (e.g., P, Ge, B, etc.).

[0131] In some embodiments, the non-native material layer 420 is a stack of materials, such as a FET gate stack comprising both a gate dielectric layer and a gate electrode layer. As an example, the non-native material layer 420 may be a gate dielectric stack suitable for contacting semiconductor device regions (e.g., transistor channel regions) exposed from the back side. Any other materials described as options for device layer 415 may also be deposited on the back side of device layer 415 and / or on device regions formed within device layer 415. For example, the non-native material layer 420 may be any of the oxide semiconductor, TMDC, or tunneling materials described above, which may be deposited on the back side, for example, to incrementally fabricate vertically stacked device layers.

[0132] Back-side wafer-level processing can continue in any manner known to be suitable for front-side processing. For example, any known photolithography and etching techniques can be used to pattern the non-native material layer 420 into active device regions, device isolation regions, device contact metallizations, or device interconnects. Back-side wafer-level processing can also fabricate one or more interconnect metallization layers that couple terminals of different devices to one or more devices within the IC. In some embodiments further described elsewhere herein, back-side processing can be used to interconnect power buses to various device terminals within the IC.

[0133] In some embodiments, back-side processing includes bonding to a secondary host substrate. Such bonding can employ any layer transfer process to connect a back-side (e.g., non-native) material layer to another substrate. Following such bonding, the previous host substrate, acting as a sacrificial donor, can be removed to re-expose the front side of the front stack and / or device layer. Such embodiments enable iterative side-to-side lamination of the device layer with a first device layer that acts as the core of the component. Figure 4G and Figure 5G In some embodiments shown, a secondary host substrate 440 connected to the non-native material layer 420 provides at least mechanical support while the host substrate 402 is removed.

[0134] The secondary host substrate 440 can be connected to the non-native material layer 420 using any bonding method (e.g., but not limited to, thermocompression bonding). In some embodiments, both the surface layer of the secondary host substrate 440 and the non-native material layer 420 are continuous dielectric layers (e.g., SiO) that are thermocompressed together. In some other embodiments, both the surface layer of the secondary host substrate 440 and the non-native material layer 420 comprise metal layers (e.g., Au, Pt, etc.) that are thermocompressed together. In other embodiments, at least one of the surface layer of the secondary host substrate 440 and the non-native material layer 420 is patterned, including both a patterned metal surface (i.e., trace) and a surrounding dielectric (e.g., isolation), which are thermocompressed together to form a hybrid (e.g., metal / oxide) junction. In such embodiments, structural features in the secondary host substrate 440 and the patterned non-native material layer 420 are aligned (e.g., photo-aligned) during the bonding process. In some embodiments, the non-native material layer 420 includes one or more conductive back-side traces coupled to terminals fabricated in the device layer 415 of the transistor. The conductive back-side traces may, for example, be bonded to metallization located on the secondary host substrate 440.

[0135] Before or after the front-side fabrication of the device layer has been completed, bonding of the device layer can continue from the front and / or back sides of the device layer. The back-side bonding process can be performed after the front-side fabrication of the device (transistor) is substantially complete. Alternatively, the back-side bonding process can be performed before the front-side fabrication of the device (e.g., transistor) is completed, in which case the front side of the device layer can undergo additional fabrication after the back-side bonding process. Figure 4H and Figure 5H As further illustrated, for example, the front-side processing includes removing the host substrate 402 (as a second donor substrate) to re-expose the front side of the device layer 415. In this case, the donor-host substrate assembly 403 includes a secondary host substrate 440 connected to the device layer 415 via a non-native material layer 420.

[0136] On the other hand, the above text combines Figures 2E-2GThe described integrated circuit structure can be co-integrated with other back-side exposed integrated circuit structures, such as adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may be aimed at integrating multi-width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separated by SAGE walls. In embodiments, nanowires / nanoribbons are integrated with multi-Wsi within the SAGE architecture portion of a front-end process flow. Such a process flow can involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality for next-generation transistors with low power and high performance. The associated epitaxial source or drain regions can be embedded (e.g., by removing portions of the nanowires and then performing source or drain (S / D) growth).

[0137] To provide further background, the advantages of the self-aligned gate endcap (SAGE) architecture can include achieving higher layout density, and specifically, scaling diffusion to the diffusion pitch. For illustrative comparison, Figure 6 A cross-sectional view along the nanowires and fins of a non-endcap architecture according to an embodiment of the present disclosure is shown. Figure 7 A cross-sectional view along the nanowires and fins is shown for a self-aligned gate end cap (SAGE) architecture according to an embodiment of the present disclosure.

[0138] refer to Figure 6 The integrated circuit structure 600 includes a substrate 602 having fins 604, which extend by an amount 606 above an isolation structure 608 laterally surrounding a lower portion of the fins 904. As depicted, the upper portion of the fins may include a local isolation structure 622 and a growth enhancement layer 620. Corresponding nanowires 605 are located above the fins 604. A gate structure can be formed on the integrated circuit structure 600 to fabricate a device. However, breakpoints in such a gate structure can be accommodated by increasing the spacing between the fin 604 / nanowire 605 pairs.

[0139] refer to Figure 6 In an embodiment, after the gate is formed, in order to leave an exposed bottom surface including the gate structure and the epitaxial source or drain structure, the lower portion of structure 600 may be planarized and / or etched to layer 634. It should be understood that the back-side (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure. It should also be understood that it may be planarized and / or etched to other layers, such as 630 or 632.

[0140] In comparison, refer to Figure 7The integrated circuit structure 750 includes a substrate 752 having fins 754, which extend by an amount 756 above an isolation structure 758 laterally surrounding the lower portion of the fins 754. As depicted, the upper portion of the fins may include a local isolation structure 772 and a growth enhancement layer 770. Corresponding nanowires 755 are located above the fins 754. Isolation SAGE walls 760 (which may include a hard mask, as depicted) are included within the isolation structure 758 and between adjacent fin / nanowire 755 pairs. The distance between the isolation SAGE wall 760 and the nearest fin / nanowire 755 pair defines the gate cap pitch 762. Gate structures may be formed on the integrated circuit structure 750 between the isolation SAGE walls to fabricate a device. Breakpoints in such a gate structure are caused by the isolation SAGE walls. Because the isolation SAGE walls 760 are self-aligned, limitations from conventional methods can be minimized to achieve more aggressive diffusion to the diffusion pitch. Furthermore, since the gate structure includes breakpoints at all locations, individual gate structure portions can be layered via local interconnects formed on the isolation SAGE walls 760. In embodiments, as depicted, each isolation SAGE wall 760 includes a lower dielectric portion and a dielectric cap located on the lower dielectric portion.

[0141] refer to Figure 7 In an embodiment, after the gate is formed, in order to leave an exposed bottom surface including the gate structure and the epitaxial source or drain structure, the lower portion of structure 750 may be planarized and / or etched to layer 784. It should be understood that the back-side (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure. It should also be understood that it may be planarized and / or etched to other layers, such as 780 or 782.

[0142] The self-aligned gate end cap (SAGE) fabrication scheme involves forming a gate / trench contact end cap that is self-aligned to the fin without requiring additional length to accommodate mask mismatch. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of a gate end cap isolation structure, which may also be referred to as a gate wall, an isolated gate wall, or a self-aligned gate end cap (SAGE) wall.

[0143] In embodiments, as described throughout, the self-aligned gate end cap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating portions of the permanent gate structure from each other or contributing to the isolation of portions of the permanent gate structure from each other. Exemplary materials or combinations of materials include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride, and an upper portion of a material with a higher dielectric constant (e.g., hafnium oxide).

[0144] It should be understood that the above text, in combination with... Figures 2E-2G The described integrated circuit structure can be co-integrated with other back-side exposed integrated circuit structures (e.g., nanowire- or nanoribbon-based devices). Alternatively or concurrently, a combination of... Figures 2E-2G The described process is used to fabricate other integrated circuit structures. To highlight an exemplary integrated circuit structure with three vertically arranged nanowires, Figure 8A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 8B It shows Figure 8A The source or drain view of a nanowire-based integrated circuit structure, such as a cross-sectional view taken along the a-a' axis. Figure 8C It shows Figure 8A A cross-sectional channel view of a nanowire-based integrated circuit structure, taken along the b-b' axis.

[0145] refer to Figure 8A The integrated circuit structure 800 includes one or more vertically stacked nanowires (groups 804) located above a substrate 802. In the depicted embodiments, as depicted, a local isolation structure 802C, a growth enhancement layer 802B, and a lower substrate portion 802A are included within the substrate 802. For illustrative purposes, and to emphasize the nanowire portion, optional fins located below the bottommost nanowire and formed by the substrate 802 are not depicted. The embodiments herein pertain to both single-wire devices and multi-wire devices. For example, for illustrative purposes, a three-nanowire-based device having nanowires 804A, 804B, and 804C is shown. For ease of description, nanowire 804A is used as an example, wherein the description focuses on one nanowire. It should be understood that, in describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire in the nanowires.

[0146] Each nanowire in nanowire 804 includes a channel region 806. The channel region 806 has a length (L). (Reference) Figure 8CThe channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 8A and Figure 8C Both, the gate electrode stack 808 surrounds the entire perimeter (Pc) of each channel region in the channel region 806. The gate electrode stack 808 includes a gate electrode and a gate dielectric layer located between the channel region 806 and the gate electrode (not shown). In embodiments, the channel regions are discrete because they are completely surrounded by the gate electrode stack 808 without any intervening material (e.g., a lower substrate material or an overlying channel fabrication material). Therefore, in embodiments having multiple nanowires 804, the channel regions 806 of the nanowires are also relatively discrete from each other.

[0147] refer to Figure 8A and Figure 8B Both, the integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812. This pair of non-discrete source or drain regions 810 / 812 is located on either side of a channel region 806 of a plurality of vertically stacked nanowires 804. Furthermore, this pair of non-discrete source or drain regions 810 / 812 is adjacent to the channel region 806 of the plurality of vertically stacked nanowires 804. In one such embodiment (not depicted), since epitaxial growth is located on and between nanowire portions extending beyond the channel region 806, this pair of non-discrete source or drain regions 810 / 812 is directly perpendicularly adjacent to the channel region 806, wherein the nanowire ends are shown as being within the source or drain structure. In another embodiment, as... Figure 8A As depicted, because it is formed at the ends of nanowires rather than between nanowires, this pair of non-discrete source or drain regions 810 / 812 are indirectly perpendicular to the channel region 806.

[0148] In the embodiments, as depicted, the source or drain regions 810 / 812 are non-discrete because there is no single and discrete source or drain region for each channel region 806 of the nanowire 804. Therefore, in embodiments with multiple nanowires 804, the source or drain regions 810 / 812 of the nanowires are global or uniform source or drain regions, contrary to the case where they are discrete for each nanowire. That is, the non-discrete source or drain regions 810 / 812 are global in the sense that a single uniform feature is used for the source or drain regions of multiple (in this case, three) nanowires 804, and more specifically, for the source or drain regions of more than one discrete channel region 806. In one embodiment, viewed from a cross-sectional view orthogonal to the length of the discrete channel region 806, as... Figure 8BAs depicted, each of the pair of non-discrete source or drain regions 810 / 812 is approximately rectangular in shape, having a tapered bottom portion and a apex top portion. However, in other embodiments, the source or drain regions 810 / 812 of the nanowire are relatively larger and discretely non-vertically merged epitaxial structures, such as protrusions.

[0149] According to embodiments of this disclosure, and as Figure 8A and Figure 8B As depicted, the integrated circuit structure 800 also includes a pair of contacts 814, each contact 814 located on one of the source or drain regions 810 / 812 of the pair of non-discrete source or drain regions 810 / 812. In one such embodiment, each contact 814 completely surrounds the corresponding non-discrete source or drain region 810 / 812 in a vertical sense. In another aspect, as... Figure 8B As depicted, the entire perimeter of the non-discrete source or drain regions 810 / 812 may not be accessible for contact with the contact portion 814, and the contact portion 814 therefore only partially surrounds the non-discrete source or drain regions 810 / 812. In a comparative embodiment not depicted, as truncated along the a-a' axis, the entire perimeter of the non-discrete source or drain regions 810 / 812 is surrounded by the contact portion 814.

[0150] Refer again Figure 8A In one embodiment, the integrated circuit structure 800 further includes a pair of spacers 816. As depicted, the outer portions of these spacers 816 may partially overlap with non-discrete source or drain regions 810 / 812, thereby providing an "embedded" portion of the non-discrete source or drain regions 810 / 812 beneath these spacers 816. Also as depicted, the embedded portion of the non-discrete source or drain regions 810 / 812 may not extend entirely beneath the pair of spacers 816.

[0151] Substrate 802 may be made of a material suitable for manufacturing integrated circuit structures. In one embodiment, substrate 802 includes a lower body substrate made of a single-crystal material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or III-V compound semiconductor materials. An upper insulating layer is located on the lower body substrate and may be made of a material including, but not limited to, silicon dioxide, silicon nitride, or silicon oxynitride. Therefore, structure 800 can be fabricated from a semiconductor-on-insulator substrate. Alternatively, structure 800 is formed directly from the body substrate, and localized oxidation is used to form electrically insulating portions instead of the aforementioned upper insulating layer. In another alternative embodiment, structure 800 is formed directly from the body substrate, and doping is used to form electrically isolated active regions (e.g., nanowires) thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an Ω-FET type structure.

[0152] In embodiments, the nanowire 804 may be sized as a line or strip (as described below) and may have square or rounded corners. In embodiments, the nanowire 804 is made of a material such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowire 804, the single-crystal nanowire may be based on a (100) global orientation, for example, having a z-direction. <100> Planar. Other orientations may also be considered, as described below. In embodiments, the nanowires 804 are nanometer-sized when viewed from a cross-sectional perspective. For example, in a particular embodiment, the minimum size of the nanowires 804 is less than approximately 20 nanometers. In embodiments, the nanowires 804 are made of a strained material, particularly a strained material located in the channel region 806.

[0153] refer to Figure 8C In this embodiment, each channel region 806 has a width (Wc) and a height (Hc), which are approximately the same. That is, in both cases, the cross-sectional profile of the channel region 806 is square, or if it is rounded, the cross-sectional profile of the channel region 806 is circular. In another aspect, the width and height of the channel regions do not need to be the same, for example, as described throughout the text for nanoribbons.

[0154] Refer again Figure 8A , Figure 8B and Figure 8C In an embodiment, in order to leave an exposed bottom surface including the gate structure and the epitaxial source or drain structure, the lower portion of structure 800 may be planarized and / or etched to layer 899. It should be understood that the back-side (bottom) contact may be formed on the exposed bottom surface of the epitaxial source or drain structure.

[0155] In embodiments, as described throughout, the integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate structure having one or more corresponding overlying nanowire structures, and an isolation structure between the finFET or tri-gate structure and the corresponding one or more overlying nanowire structures. In some embodiments, the finFET or tri-gate structure is retained. In other embodiments, the finFET or tri-gate structure may ultimately be removed in a substrate removal process.

[0156] The embodiments disclosed herein can be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. Integrated circuits can be coupled to buses and other components in a system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0157] Figure 9 A computing device 900 according to one embodiment of the present disclosure is shown. The computing device 900 houses a board 902. The board 902 may include multiple components, including but not limited to a processor 904 and at least one communication chip 906. The processor 904 is physically and electrically coupled to the board 902. In some embodiments, at least one communication chip 906 is also physically and electrically coupled to the board 902. In other embodiments, the communication chip 906 is part of the processor 904.

[0158] Depending on the application of computing device 900, the computing device may include other components that may or may not be physically coupled and electrically coupled to board 902. These other components include, but are not limited to: volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, optical disc (CD), digital versatile optical disc (DVD), etc.).

[0159] The communication chip 906 enables wireless communication for transmitting data to and from the computing device 900. The term "wireless" and its derivatives can be used to describe circuits, apparatuses, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain wires. The communication chip 906 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. The computing device 900 may include multiple communication chips 906. For example, the first communication chip 906 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 906 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0160] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The integrated circuit die of the processor 904 may include one or more structures constructed according to embodiments of the present disclosure, such as integrated circuit structures. The term "processor" may refer to any means or part of a means for processing electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0161] The communication chip 906 also includes an integrated circuit die packaged within the communication chip 906. The integrated circuit die of the communication chip 906 may include one or more structures constructed according to embodiments of the present disclosure, such as integrated circuit structures.

[0162] In other embodiments, another component housed within the computing device 900 may contain an integrated circuit die comprising one or more structures constructed according to embodiments of the present disclosure, such as an integrated circuit structure.

[0163] In various embodiments, the computing device 900 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other embodiments, the computing device 900 may be any other electronic device that processes data.

[0164] Figure 10 An interposer 1000, comprising one or more embodiments of the present disclosure, is illustrated. The interposer 1000 is an intermediary substrate for bridging a first substrate 1002 to a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1000 is to extend connections to wider spacing or to rewire connections to different connections. For example, the interposer 1000 may couple an integrated circuit die to a ball grid array (BGA) 906, which may then be coupled to the second substrate 1004. In some embodiments, the first substrate 1002 and the second substrate 1004 are attached to opposite sides of the interposer 1000. In other embodiments, the first substrate and the second substrate 1002 / 1004 are attached to the same side of the interposer 1000. And in other embodiments, three or more substrates are interconnected through the interposer 1000.

[0165] Intermediate layer 1000 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material (e.g., polyimide). In other embodiments, intermediate layer 1000 may be formed of alternative rigid or flexible material, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

[0166] Interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. Interposer 1000 may also include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 1000. According to embodiments of this disclosure, the apparatus or processes disclosed herein can be used to manufacture interposer 1000 or to manufacture components included in interposer 1000.

[0167] It should be understood that the structures described herein can operate at low temperatures (e.g., in the range of -77 degrees Celsius to 0 degrees Celsius). In one embodiment, for example, as described below... Figure 11A The thermal regulator / cooling device is coupled to a common plate having means having a structure coupled thereto, as described herein. In one embodiment, for example, the following is combined with Figure 11B The aforementioned heat regulator device and / or refrigeration device are included on a processing apparatus having a structure as described herein.

[0168] Figure 11A A computing device 1100 according to one embodiment of the present disclosure is shown. The computing device 1100 houses a board. The board may include multiple components, including but not limited to a processing device 1102. The computing device 1100 may also include a communication chip 1112. In one embodiment, the processing device 1102 is physically and electrically coupled to the board. In some embodiments, the communication chip 1112 is also physically and electrically coupled to the board. In other embodiments, the communication chip 1112 is part of the processing device 1102.

[0169] Depending on its application, computing device 1100 may include other components that may or may not be physically coupled and electrically coupled to the board. These other components may include, but are not limited to, memory 1104 (e.g., volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory), antenna 1122, display device 1106, battery / power supply 1114, audio output device 1108, audio input device 1118, global positioning system (GPS) device 1116, another output device 1110 (e.g., video output) and other input devices 1120 (e.g., video input), security interface device 1121, and / or testing device. In one embodiment, thermal regulation / cooling device 1111 is included and coupled to the board, for example, a device including actively cooled copper channels.

[0170] Communication chip 1112 enables wireless communication for transmitting data to and from computing device 1100. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain wires. Communication chip 1112 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. Computing device 1100 may include multiple communication chips 1112. For example, the first communication chip 1112 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1112 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0171] The processing device 1102 of the computing device 1100 may include an integrated circuit die in a package. The processing device 1102 may include one or more structures constructed according to embodiments of the present disclosure, such as an all-around gate integrated circuit structure having a vertical-transfer field-effect transistor (FET) with a bottom source connection. The term "processing device" may refer to any means or part of a means of processing electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0172] Figure 11B A processing apparatus according to one embodiment of the present disclosure is shown. Reference Figure 11B The exemplary processing device 1102 includes a memory region, a logic region, a communication device region, an interconnect and redistribution layer (RDL), a metal-insulator-metal (MIM) region, a cooling device region, a thermal regulation device region, a battery / power regulation device region, and a hardware security device region. In one embodiment, the cooling device region and / or the thermal regulation device region is a region that includes actively cooled copper channels.

[0173] Therefore, embodiments of this disclosure include an integrated circuit structure having a vertical transmission field-effect transistor (FET) with a bottom source connection, and a method of manufacturing an integrated circuit structure having a vertical transmission field-effect transistor (FET) with a bottom source connection.

[0174] The above description of the embodiments shown in this disclosure (including the description in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. Although specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art.

[0175] These modifications may be made to this disclosure in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific embodiments disclosed in the specification and claims. Rather, the scope of this disclosure is determined entirely by the appended claims, which shall be interpreted in accordance with established principles of claim interpretation.

[0176] Exemplary Example 1: An integrated circuit structure includes a channel structure above a substrate. A gate structure laterally surrounds the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically below the channel structure. Conductive vias pass through the substrate, coupling the metal source structure to the channel structure.

[0177] Exemplary Example 2: An integrated circuit structure according to Exemplary Example 1, wherein the channel structure includes a vertical fin array.

[0178] Exemplary Example 3: An integrated circuit structure according to Exemplary Example 1 or 2, wherein the substrate includes a silicon-on-insulator structure.

[0179] Exemplary Example 4: The integrated circuit structure according to Exemplary Example 1, 2 or 3 further includes: one or more trench isolation structures in the substrate and laterally adjacent to the conductive vias.

[0180] Exemplary Example 5: An integrated circuit structure according to Exemplary Example 1, 2, 3 or 4, wherein the metal source structure has a lateral width greater than the lateral width of the drain structure.

[0181] Exemplary Example 6: An integrated circuit structure includes a front-side structure comprising: a device layer having a plurality of vertical transfer field-effect transistors (FETs), and a plurality of metallization layers above the vertical transfer FETs of the device layer. A back-side structure lies below the vertical transfer FETs of the device layer. The back-side structure includes a ground metal line or a power metal line.

[0182] Exemplary Example 7: An integrated circuit structure according to Exemplary Example 6, wherein each vertical transmission FET in the vertical transmission FET includes a vertical fin array.

[0183] Exemplary Example 8: An integrated circuit structure according to Exemplary Example 6 or 7, wherein each of the vertical transmission FETs includes a metal source structure vertically below the channel structure.

[0184] Exemplary Example 9: An integrated circuit structure according to Exemplary Example 8, wherein each vertical transmission FET in the vertical transmission FET includes a conductive via between a metal source structure and a channel structure.

[0185] Exemplary Example 10: An integrated circuit structure according to Exemplary Example 6 or 7, wherein each of the vertical transmission FETs includes a buried power rail.

[0186] Exemplary Example 11: A computing device includes a board and components coupled to the board. The component includes an integrated circuit structure including a channel structure above a substrate. A gate structure laterally surrounds the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically below the channel structure. A conductive via passes through the substrate, coupling the metal source structure to the channel structure.

[0187] Exemplary Example 12: The computing device according to Exemplary Example 11 further includes a memory coupled to the board.

[0188] Exemplary Example 13: The computing device according to Exemplary Example 11 or 12 further includes a communication chip coupled to the board.

[0189] Exemplary Example 14: The computing device according to Exemplary Example 11, 12 or 13 further includes a camera coupled to the plate.

[0190] Exemplary Example 15: The computing device according to Exemplary Example 11, 12, 13 or 14 further includes a battery coupled to the plate.

[0191] Exemplary Example 16: The computing device according to Exemplary Example 11, 12, 13, 14 or 15 further includes a speaker coupled to the board.

[0192] Exemplary Example 17: The computing device according to Exemplary Example 11, 12, 13, 14, 15 or 16 further includes a compass coupled to the plate.

[0193] Exemplary Example 18: The computing device according to Exemplary Example 11, 12, 13, 14, 15, 16 or 17 further includes a GPS coupled to the board.

[0194] Exemplary Example 19: The computing device according to Exemplary Example 11, 12, 13, 14, 15, 16, 17 or 18 further includes a display coupled to the board.

[0195] Exemplary Example 20: A computing device according to Exemplary Example 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: a channel structure over a substrate; a gate structure laterally surrounding the channel structure; a drain structure over the gate structure and on the channel structure; a metal source structure under the substrate and vertically under the channel structure; and a conductive via through the substrate, the conductive via coupling the metal source structure to the channel structure. The channel structure comprises an array of vertical fins.

2. The integrated circuit structure of claim 1, wherein, The substrate comprises a silicon-on-insulator structure.

3. The integrated circuit structure of claim 1 or 2, wherein, one or more trench isolation structures in the substrate and laterally adjacent to the conductive via.

4. The integrated circuit structure of claim 1, 2, or 3, further comprising: The metal source structure has a lateral width that is greater than a lateral width of the drain structure.

5. The integrated circuit structure of claim 1, 2, 3, or 4, wherein, 6. An integrated circuit structure, comprising: a front-side structure, the front-side structure comprising: a device layer having a plurality of vertical transfer field effect transistors (FETs); and a plurality of metallization layers over the vertical transfer FETs of the device layer; and a back-side structure under the vertical transfer FETs of the device layer, the back-side structure comprising a ground metal line or a power metal line. Each of the vertical transfer FETs comprises an array of vertical fins.

7. The integrated circuit structure of claim 6, wherein, Each of the vertical transfer FETs comprises a metal source structure vertically under a channel structure.

8. The integrated circuit structure of claim 6 or 7, wherein, Each of the vertical transfer FETs comprises a conductive via between the metal source structure and the channel structure.

9. The integrated circuit structure of claim 8, wherein, Each of the vertical transfer FETs comprises a buried power rail.

10. The integrated circuit structure of claim 6 or 7, wherein, 11. A computing device, comprising: a board; and a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: a channel structure over a substrate; a gate structure laterally surrounding the channel structure; a drain structure over the gate structure and on the channel structure; a metal source structure under the substrate and vertically under the channel structure; and a conductive via through the substrate, the conductive via coupling the metal source structure to the channel structure.

12. The computing device of claim 11, further comprising: a memory coupled to the board.

13. The computing device of claim 11 or 12, further comprising: a communication chip coupled to the board.

14. The computing device of claim 11, 12, or 13, further comprising: a camera coupled to the board.

15. The computing device of claim 11, 12, 13, or 14, further comprising: a battery coupled to the board.

16. The computing device of claim 11, 12, 13, 14, or 15, further comprising: a speaker coupled to the board.

17. The computing device of claim 11, 12, 13, 14, 15, or 16, further comprising: a compass coupled to the board. ​ 18. The computing device of claim 11, 12, 13, 14, 15, 16, or 17, further comprising: a GPS coupled to the board.

19. The computing device of claim 11, 12, 13, 14, 15, 16, 17, or 18, further comprising: a display coupled to the board.

20. The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein, the component is a packaged integrated circuit die.

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