Log hierarchical synchronization system based on ARM-MCU heterogeneous system

Abstract

The invention relates to a log hierarchical synchronization system based on an ARM-MCU (Advanced RISC Machine-Microprogrammed Control Unit) heterogeneous system, which belongs to the technical field of embedded systems and is characterized in that an MCU slave is connected with an FPGA (Field Programmable Gate Array) module through an LVDS (Low Voltage Differential Signaling) bus, and the FPGA module is connected with an ARM host through the Ethernet; the MCU slave is used for sending the generated log to the FPGA module and storing the log containing the key event through the annular buffer area; the FPGA module is used for packaging the log to obtain a UDP (User Datagram Protocol) message and sending the UDP message to the ARM host; and the ARM host is used for analyzing the UDP message to obtain the log, obtaining the system time, writing the log and the system time into a log file, and performing hierarchical storage on the log based on the priority of the log. According to the system provided by the invention, timestamps are uniformly recorded by the ARM, so that the problem of time asynchronization is avoided, logs are uniformly recorded and managed by the ARM end, million-level log recording is supported, and complete system operation logs can be stored.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of embedded systems, and in particular to a log hierarchical synchronization system based on an ARM-MCU heterogeneous system. BACKGROUND

[0002] The current industrial Internet of Things field generally adopts a distributed architecture of an ARM architecture host and multiple MCU slaves, and with the development of industry 5.0, new requirements are put forward for fault diagnosis of the distributed system, and 8-16 MCU nodes need to be supported for cooperative log recording, and the running state of each MCU needs to be recorded, which requires a large physical storage.

[0003] In the existing log management system, the MCU is limited by the on-chip Flash capacity (usually <256KB), and cannot store complete historical logs, and the traditional TF card expansion scheme will increase the hardware cost by more than 30%. When adopting UART serial port transmission of logs, the error rate is as high as 10⁻³ (actual measurement data), and the main processor interruption load increases by more than 40%. The local clock deviation of each device causes confusion of log timestamps, which may cause misjudgment of the order of millisecond-level critical events in power system scenarios.

[0004] The local storage space of the existing MCU device is limited, and the complete system running log cannot be saved, the serial port log transmission method occupies a large amount of MCU host resources, the cross-device log timestamp is difficult to synchronize, and the MCU performance is limited by hardware resources, and the complete system running log cannot be recorded. SUMMARY

[0005] Therefore, it is necessary to provide a log hierarchical synchronization system based on an ARM-MCU heterogeneous system to solve the problem of how to record complete logs of a distributed system and realize log synchronization.

[0006] In order to solve the above problems, the present application provides a log hierarchical synchronization system based on an ARM-MCU heterogeneous system, comprising: MCU slave, FPGA module and ARM host; The MCU slave is connected with the FPGA module through an LVDS bus, and the FPGA module is connected with the ARM host through an Ethernet; The MCU slave is used for sending generated logs to the FPGA module, and storing logs containing critical events through a ring buffer; The FPGA module is used for encapsulating the logs to obtain UDP packets, and sending the UDP packets to the ARM host; The ARM host is configured to parse the UDP packet to obtain the log, obtain system time, write the log and the system time into a log file, and store the log in a hierarchical manner based on the priority of the log.

[0007] In a possible implementation, the ARM host is specifically configured to: store logs containing emergency events in a memory queue and store regular logs in an eMMC memory.

[0008] In a possible implementation, the ARM host is further configured to: write the log and the system time into a local disk and write the log and the system time into a log server through a syslog protocol.

[0009] In a possible implementation, the ARM host is further configured to: convert the system time into a string and write the system time and the log into a log file after splicing.

[0010] In a possible implementation, the ARM host communicates with an upper computer through a TCP protocol; the upper computer is configured to send a read log instruction to the ARM host, and the read log instruction is used to obtain the log.

[0011] In a possible implementation, the ARM host comprises: a SCPI parsing module configured to parse the read log instruction and read a serious error log based on the read log instruction.

[0012] In a possible implementation, the UDP packet comprises: a synchronization header, a type, a target identifier, a source identifier, a current frame length, application layer data, and a synchronization tail.

[0013] In a possible implementation, the MCU slave is specifically configured to: collect sensor data and generate a log based on the sensor data; The MCU slave is further configured to send a fault and an abnormal configuration parameter in MCU slave operation to the ARM host through log uploading.

[0014] In a possible implementation, the ARM host adopts a Cortex-A7 processor; and the MCU slave adopts an STM32F407.

[0015] The beneficial effects of the present application are: the log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the present application, the log is generated by the MCU slave machine, and the log is sent to the FPGA module, the log is packaged by the FPGA module to obtain the UDP message, and the UDP message is sent to the ARM host, the log is obtained by the ARM host for analyzing the UDP message, the system time is obtained, the log and the system time are written into the log file, and the hierarchical storage is performed according to the priority, the log uploaded by the MCU does not record the time, the timestamp is recorded by the ARM, the problem of time asynchronization is avoided, the log is recorded and managed by the ARM, the million-level log record can be supported, and therefore the complete log of system operation can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 An embodiment structure schematic diagram of the log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the present application is shown in the figure. Figure 2 A log protocol format schematic diagram provided by the present application is shown in the figure. Figure 3 A system module structure schematic diagram provided by the present application is shown in the figure. Figure 4 A software communication structure schematic diagram provided by the present application is shown in the figure. Figure 5 One of the flowcharts of the log processing module software provided by the present application is shown in the figure. Figure 6 The second flowchart of the log processing module software provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described clearly and completely by combining the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0019] In the description of the embodiments of the application, unless otherwise specified, the meaning of "multiple" is two or more than two. The association relationship of the associated objects is described as "and / or", which means that there can be three relationships, for example: A and / or B can represent the following three cases: A exists alone, A and B exist simultaneously, and B exists alone.

[0020] The descriptions of "first", "second", and the like in the embodiments of the application are only for the purpose of description and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the technical features limited by "first" and "second" can explicitly or implicitly include at least one of the features.

[0021] In this document, the term "embodiment" means that the specific features, structures or properties described in connection with the embodiment can be included in at least one embodiment of the application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] The application provides a log hierarchical synchronization system based on an ARM-MCU heterogeneous system, which is described below.

[0023] Figure 1 An embodiment structure schematic diagram of the log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the application is shown in Figure 1 The log hierarchical synchronization system based on the ARM-MCU heterogeneous system includes: MCU slave 110, FPGA module 120 and ARM host 130; The MCU slave 110 is connected with the FPGA module 120 through an LVDS bus, and the FPGA module 120 is connected with the ARM host 130 through an Ethernet; The MCU slave 110 is configured to send the generated log to the FPGA module 120, and store the log containing a key event through a ring buffer; The FPGA module 120 is configured to encapsulate the log to obtain a UDP packet, and send the UDP packet to the ARM host 130; The ARM host 130 is configured to parse the UDP packet to obtain the log, and obtain a system time, write the log and the system time into a log file, and store the log based on a priority of the log.

[0024] As Figure 1As shown, the number of MCU slaves can be multiple, the MCU slaves are connected through a low-voltage differential signaling (LVDS) bus and an FPGA module, the FPGA module is connected with an ARM host through Ethernet, after the data of the slaves reaches the FPGA module, the FPGA module encapsulates the data into network frames and sends the network frames to the host, the ARM host parses the log frames and records the logs, and the system expandability is improved.

[0025] The MCU slave can process the data collected by the sensor to generate logs in real time, and send the generated logs to the FPGA module, and the logs uploaded by the MCU do not record time.

[0026] The ring buffer is a kind of efficient data structure, which adopts the logical design of head-to-tail connection, and can temporarily store continuously generated data (such as sensor collected logs, real-time data stream, etc.).

[0027] The MCU slave uses a ring buffer to store key events (the capacity is optimized to 2KB).

[0028] After the FPGA module receives the logs sent by the MCU slave, the logs are encapsulated according to the format of the user datagram protocol (UDP) to obtain UDP packets, and the UDP packets are sent to the ARM host.

[0029] The ARM host obtains the logs by parsing the UDP packets, and obtains the system time, converts the system time into a string, and then splices the system time and the log information together, and writes the spliced information into a log file for hierarchical storage.

[0030] That is, the logs uploaded by the MCU slave do not record time, and the timestamp is recorded by the ARM host, which can avoid the problem of time asynchronization. Moreover, the logs are recorded and managed by the ARM host, which can support million-level log recording, so that the complete logs of system running can be saved.

[0031] The ARM host stores the logs hierarchically according to the priority of the logs, and the ARM host can divide the priority according to the real-time performance and importance of the logs, which can ensure that the key logs (such as system errors and safety events) are synchronized in priority, and the secondary logs (such as debugging information) can be delayed.

[0032] In summary, the log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the embodiment of the application has the following advantages: the MCU slave generates a log, and sends the log to the FPGA module; the FPGA module encapsulates the log to obtain a UDP message, and sends the UDP message to the ARM host; the ARM host is used to parse the UDP message to obtain the log, and obtain a system time; the log and the system time are written into a log file to be stored hierarchically according to a priority; the log uploaded by the MCU does not record a time, and a time stamp is recorded by the ARM, so that the problem of time asynchronization is avoided; the ARM is used to record and manage the log uniformly, and can support million-level log recording, so that complete system running logs can be saved.

[0033] In some embodiments of the application, the ARM host is specifically configured to: store the log containing the emergency event in a memory queue, and store the regular log in an eMMC memory.

[0034] The ARM host can store the log hierarchically according to the priority of the log, realize log priority database, store the emergency event in the memory queue, ensure quick response and reliable query of the emergency event, store the regular log in the eMMC memory, and efficiently manage massive regular logs.

[0035] The log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the embodiment of the application can realize optimal configuration of the log system under resource constraints by hierarchical storage, and the ARM host can ensure quick response and reliable query of the emergency event, and efficiently manage massive regular logs.

[0036] In some embodiments of the application, the ARM host is further configured to: write the log and the system time into a local disk, and write the log and the system time into a log server through a syslog protocol.

[0037] The ARM host writes the log into the local disk, and transmits the log to the log server through the syslog protocol to write the log into the log server.

[0038] The log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the embodiment of the application can ensure that the log will not be lost when the network is interrupted or the log server fails by writing the log into the local disk, can be directly inquired locally, and can write the log into the log server through the syslog protocol to realize centralized management of logs of multiple devices.

[0039] In some embodiments of the application, the ARM host is further configured to: The system time is converted into a string, and the system time and the log are spliced and written into a log file.

[0040] The ARM host obtains the log by analyzing the UDP message, and obtains the system time.

[0041] After the system time is converted into a string, the system time and the corresponding string of the log are spliced and written into a log file for hierarchical storage.

[0042] In some embodiments of the application, the ARM host communicates with the upper computer through a TCP protocol; the upper computer is configured to send a read log instruction to the ARM host, and the read log instruction is configured to obtain the log.

[0043] In some embodiments of the application, the ARM host comprises: The SCPI analysis module is configured to analyze the read log instruction and read the serious error log based on the read log instruction.

[0044] The upper computer PC and the ARM host communicate through a TCP protocol, and the serious error log can be obtained through an instruction; the ARM host integrates an SCPI (Standard Commands for Programmable Instruments) analysis module.

[0045] The PC communicates with the ARM host through a TCP protocol, sends a read log instruction through the TCP, and can obtain one system log at a time.

[0046] All logs of the ARM host are written into a log file for storage, and the serious error log enters a serious error log queue (queue length 20000); the PC obtains the serious error log through an SCPI instruction.

[0047] In some embodiments of the application, the UDP message comprises: A synchronization header, a type, a target identifier, a source identifier, a current frame length, application layer data and a synchronization tail.

[0048] Figure 2 A log protocol format diagram provided by the application is shown in Figure 2 The data frame structure of the UDP message comprises: a synchronization header (0xAABBCC), a type, a target identifier, a source identifier, a current frame length, application layer data and a synchronization tail (0xDDEEFF).

[0049] The target identifier and the source identifier are respectively used to indicate a destination address and a source address, and the source identifier is used to distinguish a slave address; the UDP message can further comprise an extensible 32-bit CRC check.

[0050] The log of the slave is uploaded in the form of a string according to the format specified by the protocol, and the application layer data format is as follows: :PSS[n]:MCU:LOG <type> , <message> Type: ERR and INF Message: error code, "error_description; device-dependent; date" For example: -200, "execution error; torque safety limit exceeded; 1996 / 0 / 15 13:22:51.01".

[0051] The error code can refer to Table 1, which is a correspondence between log error codes, error levels and log descriptions.

[0052] Table 1

[0053] In some embodiments of the application, the MCU slave is specifically used for: collecting sensor data and generating logs based on the sensor data; The MCU slave is also used to send faults and abnormal configuration parameters in the running of the MCU slave to the ARM host through log uploading.

[0054] In some embodiments of the application, the ARM host adopts a Cortex-A7 processor; and the MCU slave adopts an STM32F407.

[0055] The MCU slave corresponds to a slave node, adopts an STM32F407 MCU (256KB SRAM), and deploys a ring buffer log collection module.

[0056] The ARM host corresponds to a master node, adopts an ARM Cortex-A7 processor (Linux 5.10 kernel), and is responsible for global log management.

[0057] The communication medium includes an Ethernet backup channel and an FPGA module LVDS communication link.

[0058] Figure 3 A system module structure diagram provided by the application is shown in Figure 3 As shown, the analog board represents a slave, which can be expanded. In the embodiment of the application, the slave address number is specified as 1-10, and the ARM host address is 0.

[0059] This address is used to be embodied in the protocol shown in Figure 2 For the slave to the host, that is, the MCU slave transmits log information to the ARM host, the destination address is filled with 0, and the source identifier is filled with the address of the analog board.

[0060] The tertiary log cache mechanism provided by the application is as follows: MCU end: manage 2KB ring buffer, dynamic adjustment of sampling rate (10-100Hz).

[0061] ARM end: realize log priority database (emergency event storage memory queue, regular log storage eMMC memory).

[0062] The ARM end writes the log into the local disk, and at the same time, transmits the log to the log server through the syslog protocol and writes it into the log server.

[0063] Figure 4 The software communication structure provided by the application is shown as follows: Figure 4 The MCU slave machine is connected through the LVDS bus and the FPGA module, the FPGA module is connected through the Ethernet and the ARM host, the data of the slave machine reaches the FPGA module, and is uniformly packaged into a network frame by the FPGA module and sent to the host, the host analyzes the log frame and records the log, and the system has strong expansibility.

[0064] The analog board data is packaged into a frame by the FPGA module and sent to the ARM host in the form of UDP.

[0065] The PC and the ARM host communicate through the TCP mode, for serious error logs, the ARM host integrates an SCPI command analysis module, the PC is connected with the ARM host through the TCP, reads the log command through the TCP, and one system log can be acquired at a time.

[0066] The communication format between the slave MCU and the host ARM host is shown as follows: Figure 2 All logs of the ARM host are written into a log file for storage, for serious error logs, the logs enter the serious error log queue (queue length 20000), and the PC acquires the logs through the instruction.

[0067] Exemplarily, the log processing flow of the log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the application includes a slave flow and a host flow.

[0068] The slave flow, the log of the slave machine is uploaded in the form of a string according to the format specified by the protocol, and the data format is as follows: :PSS[n]:MCU:LOG <type> , <message>; Type: ERR and INF; Message: error code, "error_description; device-dependent; date".

[0069] The host process, ARM host receives the network packet of the slave, judges the frame type, the frame type is defined as -200, if the received message, the frame type is -200, will enter the receiving queue, the function of entering the queue is to quickly save the log information to the local cache, Figure 5 The flowchart of the log processing module software provided by the application is shown in Figure 1, and the flowchart of the entering queue is shown in Figure Figure 5 .

[0070] The de-queue is in another thread, and the flowchart of the de-queue is shown in Figure Figure 6 . Figure 6 The flowchart of the log processing module software provided by the application is shown in Figure 2, the purpose of this thread is to parse the queue information, after the ARM host parses the error log information, the system time is acquired, the time is converted into a string form, and the log information is spliced together and written into a log file, for the serious error log, it will enter the serious error log queue cache, and the PC end can acquire the log information through an instruction.

[0071] The log hierarchical synchronization system based on the ARM-MCU heterogeneous system provided by the application has the following beneficial effects: (1) Efficient data synchronization and real-time improvement, through the hierarchical log mechanism, the system can prioritize according to the importance and real-time requirements of the log, to ensure that the key log (such as system error, security event) is synchronized first, and the secondary log (such as debugging information) can be delayed. This hierarchical strategy significantly reduces unnecessary communication overhead and improves the overall efficiency of the system.

[0072] (2) Cross-heterogeneous core clock synchronization optimization, the slave MCU does not record the time, but the host receives the log information and marks it with a time stamp.

[0073] (3) Reliability enhancement, the hierarchical log synchronization method can combine the verification mechanism (such as CRC32) and the read-back comparison to ensure the consistency of the log data in the cross-core transmission.

[0074] In addition, through the structure body storage log information (such as data address, time stamp, etc.), the system supports abnormal backtracking and auditing.

[0075] (4) Scalability and multi-protocol compatibility, the device can support multiple communication interfaces (such as GPIB bus, RS485, Ethernet, etc.), which is convenient for integration into complex environments such as industrial Internet of Things.

[0076] The advantage of the application is that the hierarchical log strategy is deeply integrated with the heterogeneous core, which solves the real-time bottleneck of traditional log synchronization, and improves the reliability and energy efficiency of the system through dynamic resource allocation and verification mechanism. It integrates innovations in multiple fields such as heterogeneous computing, timestamp synchronization, shared memory optimization, and is suitable for embedded systems, industrial control and other scenarios.

[0077] Optionally, the heterogeneous system composition of the log hierarchical synchronization system based on the ARM-MCU heterogeneous system includes: an ARM core (Cortex-A7@1.8GHz) running a Linux system, responsible for log aggregation and network transmission. MCU core (Cortex-M7@400MHz), equipped with real-time operating system (Real Time Operate System, RTOS), processing sensor data acquisition and real-time log generation. Shared resources, 512KB dual-port SRAM (address 0x80000000) and AXI bus (bandwidth 4GB / s). Safety isolation, divide the MCU log storage area into a security domain (TEE) through TrustZone, and the ARM core needs to be authenticated before accessing.

[0078] Optionally, the log hierarchical standard is as follows: MCU side: Emergency log (ERROR): hardware failure, etc. (trigger inter-core interrupt).

[0079] Regular log (WARNING / INFO): stored in a ring buffer (capacity 256, with CRC16 verification).

[0080] ARM side: Application log (DEBUG / TRACE): written to local SQLite database through syslog.

[0081] The synchronization mechanism is as follows: Emergency channel, MCU directly wakes up ARM core through IPC interrupt (RPMSG), transmits log header + key data (delay <10us).

[0082] Batch channel, ARM polls shared memory every 100ms, copies logs in batches to DDR3 through direct memory access (Direct Memory Access, DMA) (bandwidth utilization rate ≥85%).

[0083] The log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by the application can be applied to various different scenes, and is particularly suitable for distributed log recording of an ARM architecture Linux host and multiple MCU slaves in industrial control, Internet of Things and the like, as follows: Scene 1: Industrial robot joint control, the MCU detects motor overcurrent (ERROR level), interrupts the ARM core immediately, synchronizes the log to the cloud and triggers an emergency stop.

[0084] Scene 2: Smart meter data acquisition, the MCU writes current sampling logs (INFO level) every 5 seconds, and the ARM compresses in batches and then uploads through LoRaWAN.

[0085] By using the log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by the application, the real-time log synchronization delay is reduced from 50 ms in the conventional scheme to 15 us, and the static random-access memory (SRAM) occupation on the MCU side is reduced by 40% (only the 2-level log buffer is reserved).

[0086] Those skilled in the art can understand that all or part of the processes of the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware (such as a processor, a controller, etc.) to complete, and the computer program can be stored in a computer readable storage medium. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory, etc.

[0087] The log hierarchical synchronization system based on an ARM-MCU heterogeneous system provided by the application is described in detail above, and specific examples are applied in this paper to describe the principle and implementation mode of the application. The above description of the embodiments is only used to help understand the method of the application and its core idea; meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range will be changed, and the above description of the application should not be understood as a limitation of the application.< / message> < / type> < / message> < / type>

Claims

1. A log hierarchical synchronization system based on an ARM-MCU heterogeneous system, characterized in that, The application relates to a log collection system. The system comprises an MCU slave, an FPGA module and an ARM host. The MCU slave is connected with the FPGA module through an LVDS bus, and the FPGA module is connected with the ARM host through Ethernet. The MCU slave is used for sending generated logs to the FPGA module and storing logs containing key events through a ring buffer. The FPGA module is used for encapsulating the logs to obtain UDP packets and sending the UDP packets to the ARM host. The ARM host is used for parsing the UDP packets to obtain the logs, obtaining system time, writing the logs and the system time into a log file, and storing the logs based on priorities of the logs.

2. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host is specifically used for: storing logs containing emergency events in a memory queue and storing regular logs in an eMMC memory. 3.The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, wherein, The ARM host is further used for: writing the logs and the system time into a local disk and writing the logs and the system time into a log server through a syslog protocol.

4. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host is further used for: converting the system time into a string and writing the system time and the logs into a log file after splicing.

5. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, characterized in that, The ARM host communicates with an upper computer through a TCP protocol.

6. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 5, characterized in that, The upper computer is used for sending a read log instruction to the ARM host, and the read log instruction is used for obtaining the logs. The ARM host comprises an SCPI analysis module.

7. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, characterized in that, The UDP packet comprises a synchronization header, a type, a target identifier, a source identifier, a current frame length, application layer data and a synchronization tail. The MCU slave is specifically used for:

8. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, characterized in that, collecting sensor data and generating logs based on the sensor data. The MCU slave is further used for sending faults and abnormal configuration parameters in MCU slave operation to the ARM host through log uploading. The ARM host adopts a Cortex-A7 processor, and the MCU slave adopts an STM32F407.

9. The log hierarchical synchronization system based on ARM-MCU heterogeneous system according to claim 1, characterized in that, ​

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