Jitter injection circuit for comparator foreground calibration

Abstract

The invention discloses a jitter injection circuit for comparator foreground calibration. The jitter injection circuit comprises a gain amplifier circuit, a resistance feedback network circuit, a current mirror circuit, a current selection switch circuit, a shunt resistor and a resistor string circuit, wherein the gain amplifier circuit is respectively connected with the resistance feedback network circuit and the current mirror circuit; the resistance feedback network circuit, the current mirror circuit and the current selection switch circuit are respectively connected with the shunt resistor; and the resistor string circuit is respectively connected with the shunt resistor and the current selection switch circuit. According to the invention, accurate control of dither (jitter) injection amplitude is realized.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a jitter injection circuit for comparator front-end calibration. Background Technology

[0002] In the design and manufacturing of integrated circuits, process variations can cause capacitor and resistor values ​​to deviate from their design values. For applications such as high-precision ADCs, calibration circuits are required. The front-end calibration circuit typically uses dithering injection to fine-tune the comparator's discrimination threshold to improve the overall circuit's conversion accuracy. However, in actual dithering circuit design, the amplitude of the dithering injection cannot be precisely controlled, thus failing to guarantee effective misalignment calibration while also affecting the discrimination of normal signals. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a dither injection circuit for comparator front-end calibration, so as to achieve precise control of the dither injection amplitude.

[0004] The objective of this invention is achieved through the following technical solution: a jitter injection circuit for comparator front-end calibration, comprising: a gain amplifier circuit, a resistor feedback network circuit, a current mirror circuit, a current selection switch circuit, a shunt resistor, and a resistor string circuit; wherein, the gain amplifier circuit is connected to the resistor feedback network circuit and the current mirror circuit respectively; the resistor feedback network circuit, the current mirror circuit, and the current selection switch circuit are connected to the shunt resistor respectively; and the resistor string circuit is connected to the shunt resistor and the current selection switch circuit respectively.

[0005] In the jitter injection circuit for comparator front-end calibration described above, the gain amplifier circuit includes gain amplifier AMP1 and gain amplifier AMP2; wherein, gain amplifier AMP1 is connected to the resistive feedback network circuit and the current mirror circuit respectively; and gain amplifier AMP2 is connected to the resistive feedback network circuit and the current mirror circuit respectively.

[0006] In the jitter injection circuit for comparator front-end calibration described above, the resistive feedback network circuit includes resistors R1, R2, R3, R4, R5, and R6. The input reference voltage VIN1 is connected to the negative terminal of gain amplifier AMP1 via resistor R1, and the input reference voltage VIN2 is directly connected to the negative terminal of gain amplifier AMP2. One end of resistor R2 is grounded, and the other end is connected to the positive terminal of gain amplifier AMP1 and one end of resistor R4. The other end of resistor R4 is connected to the shunt resistor and one end of resistor R6, and the other end of resistor R6 is connected to the positive terminal of gain amplifier AMP2. One end of resistor R3 is connected to the negative terminal of gain amplifier AMP1, and the other end of resistor R3 is connected to one end of resistor R5. The other end of resistor R5 is connected to the positive terminal of gain amplifier AMP2.

[0007] In the jitter injection circuit for comparator front-end calibration described above, the current mirror circuit includes a P-type current mirror circuit and an N-type current mirror circuit; wherein, the P-type current mirror circuit is connected to the output terminal of gain amplifier AMP1, the shunt resistor and the resistance feedback network circuit respectively; the N-type current mirror circuit is connected to the output terminal of gain amplifier AMP2, the shunt resistor and the resistance feedback network circuit respectively.

[0008] In the jitter injection circuit for comparator front-end calibration described above, the P-type current mirror circuit includes PMOS transistors M1, M2, M3, M4, M5, and M6; wherein the output terminal of gain amplifier AMP1 is connected to the gates of PMOS transistors M1, M2, M3, M4, M5, and M6, respectively. The sources of PMOS transistors M1, M2, M3, M4, M5, and M6 are all connected to the power supply; the drain of PMOS transistor M1 is connected to the other end of the shunt resistor and resistor R4, respectively; the drains of PMOS transistors M2, M3, M4, M5, and M6 are all connected to the current selection switch circuit.

[0009] In the jitter injection circuit for comparator front-end calibration described above, the N-type current mirror circuit includes NMOS transistors M27, M28, M29, M30, M31, and M32; wherein, the output terminal of gain amplifier AMP2 is connected to the gates of NMOS transistors M27, M28, M29, M30, M31, and M32, respectively; the sources of NMOS transistors M27, M28, M29, M30, M31, and M32 are all grounded; the drain of NMOS transistor M27 is connected to the other end of the shunt resistor and resistor R3, respectively.

[0010] In the jitter injection circuit described above for comparator front-end calibration, the current selection switch circuit includes a P-type current selection switch circuit and an N-type current selection switch circuit.

[0011] In the jitter injection circuit for comparator front-end calibration described above, the P-type current selection switch circuit includes PMOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16; wherein the sources of PMOS transistors M7 and M8 are both connected to the drain of PMOS transistor M2; the sources of PMOS transistors M9 and M10 are both connected to the drain of PMOS transistor M3; and the sources of PMOS transistors M11 and M12 are both connected to the drain of PMOS transistor M16. The source of PMOS transistor M13 is connected to the drain of PMOS transistor M14; the source of PMOS transistor M13 and the source of PMOS transistor M14 are both connected to the drain of PMOS transistor M5; the source of PMOS transistor M15 and the source of PMOS transistor M16 are both connected to the drain of PMOS transistor M6; the drains of PMOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16 are each connected to a shunt resistor and a resistor series circuit, respectively.

[0012] In the jitter injection circuit for comparator front-end calibration described above, the N-type current selection switch circuit includes NMOS transistors M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26; wherein the drains of NMOS transistors M17 and M18 are both connected to the drain of NMOS transistor M28; the drains of NMOS transistors M19 and M20 are both connected to the drain of NMOS transistor M29; and the drains of NMOS transistors M21 and M22 are... All are connected to the drain of NMOS transistor M30; the drains of NMOS transistors M23 and M24 are both connected to the drain of NMOS transistor M31; the drains of NMOS transistors M25 and M26 are both connected to the drain of NMOS transistor M32; the sources of NMOS transistors M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26 are respectively connected to a shunt resistor and a resistor series circuit.

[0013] In the jitter injection circuit for comparator front-end calibration described above, the shunt resistors include resistors R7, R8, R9, and R10, and the resistor string circuit includes resistor strings Rs1 and Rs2. One end of resistor R7 and one end of resistor R8 are both connected to the drain of PMOS transistor M1; the other end of resistor R7 and the first input terminal of resistor string Rs1 are both connected to the drain of PMOS transistor M7; the other end of resistor R8 and the first input terminal of resistor string Rs2 are both connected to the drain of PMOS transistor M8; one end of resistor R9 and one end of resistor R10 are both connected to the drain of NMOS transistor M27; the other end of resistor R9 and the second input terminal of resistor string Rs1 are both connected to the drain of NMOS transistor M17; and the other end of resistor R10 and the second input terminal of resistor string Rs2 are both connected to the drain of NMOS transistor M18.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] (1) The present invention uses subtraction dithering for Dither injection. Before quantization, a pseudo-random noise is added to the signal. After quantization, the same pseudo-random noise is subtracted from the digital signal so that it has no direct impact on the final output. Compared with the traditional Dither injection method, it does not increase the overall noise energy of the system, breaks the fixed pattern of quantization error, makes it closer to white noise, and improves signal quality.

[0016] (2) The dither injection circuit for comparator front-end calibration provided by the present invention uses a gain amplifier and a current mirror circuit for amplifier multiplexing. The gain amplifier generates a fixed voltage difference while providing an initial current for the current mirror circuit.

[0017] (3) The current selection switch circuit provided by the present invention can control the current shunting through the control signal and change the voltage value across the resistor series circuit through the shunting resistor. The shunting resistor and the resistor series resistor adopt the same type of resistor to ensure that the differential output dither voltage used for comparator offset calibration is compensated for the process deviation under different temperatures and process angles. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0019] Figure 1 This is a schematic diagram of a jitter injection circuit for comparator front-end calibration provided in an embodiment of the present invention;

[0020] Figure 2 This is an embodiment of the invention for using a constant voltage V XY The resulting circuit diagram;

[0021] Figure 3 This is a simplified circuit diagram of dither injection provided in an embodiment of the present invention;

[0022] Figure 4 This is a circuit diagram of the switching control circuit of the current selection switch circuit provided in the embodiment of the present invention. Detailed Implementation

[0023] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] To ensure precise control of the dither injection amplitude and overcome the shortcomings of existing technologies, a dither injection circuit for comparator front-end calibration is provided. The dither injection circuit includes a gain amplifier circuit and a resistor feedback network circuit to generate a constant reference voltage V. XY The current mirror circuit and current selection switch circuit realize the redistribution of current, and the shunt resistor is used to change the voltage across the resistor series circuit to achieve precise control of the dither injection amplitude.

[0025] Figure 1 This is a schematic diagram of a jitter injection circuit for comparator front-end calibration provided in an embodiment of the present invention. Figure 1 As shown, the jitter injection circuit for comparator front-end calibration includes: a gain amplifier circuit, a resistor feedback network circuit, a current mirror circuit, a current selection switch circuit, a shunt resistor, and a resistor string circuit; wherein, the gain amplifier circuit is connected to the resistor feedback network circuit and the current mirror circuit respectively; the resistor feedback network circuit, the current mirror circuit, and the current selection switch circuit are connected to the shunt resistor respectively; and the resistor string circuit is connected to the shunt resistor and the current selection switch circuit respectively.

[0026] The gain amplifier circuit includes gain amplifier AMP1 and gain amplifier AMP2; wherein, gain amplifier AMP1 is connected to the resistive feedback network circuit and the current mirror circuit respectively; gain amplifier AMP2 is connected to the resistive feedback network circuit and the current mirror circuit respectively.

[0027] The resistive feedback network circuit includes resistors R1, R2, R3, R4, R5, and R6. The input reference voltage VIN1 is connected to the negative terminal of gain amplifier AMP1 through resistor R1, and the input reference voltage VIN2 is directly connected to the negative terminal of gain amplifier AMP2. One end of resistor R2 is grounded, and the other end is connected to the positive terminal of gain amplifier AMP1 and one end of resistor R4. The other end of resistor R4 is connected to the shunt resistor and one end of resistor R6, and the other end of resistor R6 is connected to the positive terminal of gain amplifier AMP2. One end of resistor R3 is connected to the negative terminal of gain amplifier AMP1, and the other end of resistor R3 is connected to one end of resistor R5. The other end of resistor R5 is connected to the positive terminal of gain amplifier AMP2.

[0028] The current mirror circuit includes a P-type current mirror circuit and an N-type current mirror circuit; the P-type current mirror circuit is connected to the output terminal of the gain amplifier AMP1, the shunt resistor, and the resistor feedback network circuit, respectively; the N-type current mirror circuit is connected to the output terminal of the gain amplifier AMP2, the shunt resistor, and the resistor feedback network circuit, respectively.

[0029] The P-type current mirror circuit includes PMOS transistors M1, M2, M3, M4, M5, and M6. The output of gain amplifier AMP1 is connected to the gates of PMOS transistors M1, M2, M3, M4, M5, and M6, respectively. The sources of PMOS transistors M1, M2, M3, M4, M5, and M6 are all connected to a power supply. The drain of PMOS transistor M1 is connected to the other end of a shunt resistor and resistor R4, respectively. The drains of PMOS transistors M2, M3, M4, M5, and M6 are all connected to a current selection switch circuit.

[0030] The N-type current mirror circuit includes NMOS transistors M27, M28, M29, M30, M31, and M32. The output of gain amplifier AMP2 is connected to the gates of NMOS transistors M27, M28, M29, M30, M31, and M32, respectively. The sources of NMOS transistors M27, M28, M29, M30, M31, and M32 are all grounded. The drain of NMOS transistor M27 is connected to the other end of a shunt resistor and resistor R3, respectively.

[0031] Current selection switch circuits include P-type current selection switch circuits and N-type current selection switch circuits.

[0032] The P-type current selection switch circuit includes PMOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16. The sources of PMOS transistors M7 and M8 are connected to the drain of PMOS transistor M2; the sources of PMOS transistors M9 and M10 are connected to the drain of PMOS transistor M3; and the sources of PMOS transistors M11 and M12 are connected to the drain of PMOS transistor M4. The sources of PMOS transistors M13 and M14 are connected to the drain of PMOS transistor M5; the sources of PMOS transistors M15 and M16 are connected to the drain of PMOS transistor M6; the drains of PMOS transistors M7, M8, M9, M10, M11, M12, M13, M14, M15, and M16 are connected to a shunt resistor and a resistor series circuit, respectively.

[0033] The N-type current selection switch circuit includes NMOS transistors M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26. The drains of NMOS transistors M17 and M18 are connected to the drain of NMOS transistor M28; the drains of NMOS transistors M19 and M20 are connected to the drain of NMOS transistor M29; and the drains of NMOS transistors M21 and M22 are connected to the drain of NMOS transistor M30. The drains of NMOS transistors M23 and M24 are connected to the drain of NMOS transistor M31; the drains of NMOS transistors M25 and M26 are connected to the drain of NMOS transistor M32; the sources of NMOS transistors M17, M18, M19, M20, M21, M22, M23, M24, M25, and M26 are connected to the shunt resistor and the resistor series circuit, respectively.

[0034] The shunt resistors include resistors R7, R8, R9, and R10, and the resistor string circuit includes resistor strings Rs1 and Rs2. One end of resistor R7 and one end of resistor R8 are connected to the drain of PMOS transistor M1; the other end of resistor R7 and the first input terminal of resistor string Rs1 are connected to the drain of PMOS transistor M7; the other end of resistor R8 and the first input terminal of resistor string Rs2 are connected to the drain of PMOS transistor M8; one end of resistor R9 and one end of resistor R10 are connected to the drain of NMOS transistor M27; the other end of resistor R9 and the second input terminal of resistor string Rs1 are connected to the drain of NMOS transistor M17; the other end of resistor R10 and the second input terminal of resistor string Rs2 are connected to the drain of NMOS transistor M18.

[0035] The gain amplifier circuit and the feedback resistor network constitute a feedback circuit, generating a constant voltage difference V at nodes X and Y. XY By selecting the current mirror path through current selection switches S1-S5 and SN1-SN5, the current and voltage drop across shunt resistors R7-R9 are changed, thereby altering the voltage V across resistor series Rs1 and Rs2. A V B V C V D At the same time, the current flowing through resistors Rs1 and Rs2 remains constant. V A V B V CV D The voltage values ​​determine the differential output voltage values ​​VO1<7:0> and VO2<7:0> used for comparator offset calibration. The gain amplifier circuit consists of AMP1 and AMP2 with a feedback resistor network R1-R6, where R1 and R2 have a resistance of 3R, and R3, R4, R5, and R6 have a resistance of 4R, where R is a unit resistance. The input reference voltage VIN1 is connected to the negative terminal of gain amplifier AMP1 through the feedback resistor R1, and the input reference voltage VIN2 is directly connected to the negative terminal of gain amplifier AMP2. Due to the virtual short principle of gain amplifiers, the voltages at the positive and negative terminals of gain amplifier AMP1 and AMP2 are the same. According to Kirchhoff's current equation, the voltage V at node X is obtained. X =VIN2 + 2 / 3VIN1, the voltage at node Y is V Y =VIN2-2 / 3VIN1, creating a constant voltage difference V between node X and node Y. XY =4 / 3VIN1.

[0036] The feedback resistor network consists of two gain amplifiers AMP1 and AMP2 and six resistors R1 to R6. The positive input of AMP1 is connected to the positive terminal of resistor R2 and the negative terminal of resistor R4, with the negative terminal of R2 grounded. The negative input of AMP1 is connected to the negative terminal of resistor R1 and the positive terminal of resistor R3, with the positive terminal of resistor R1 connected to input VIN1. The output of AMP1 is connected to the gate of a P-type current mirror M1, with the drain of M1 connected to the positive terminal of resistor R4, forming a feedback loop. The positive terminal of resistor R4 is node X. The positive input of AMP2 is connected to the positive terminal of resistor R6 and the negative terminal of resistor R5, with the negative terminal of resistor R6 connected to the positive terminal of resistor R4, and the positive terminal of resistor R5 connected to the negative terminal of resistor R3. The negative input of AMP2 is connected to input VIN2. The output of AMP2 is connected to the gate of an N-type current mirror M27, with the drain of M27 connected to the positive terminal of resistor R5, forming a feedback loop. The positive terminal of resistor R5 is node Y. The voltage difference between nodes X and Y is V. XY .

[0037] The resistance of resistors R1 and R2 is 3R, and the resistance of resistors R3, R4, R5, and R6 is 4R, where R is the unit resistance value.

[0038] constant voltage difference V XY It depends only on VIN1 and the ratio of the feedback resistor network, and its value is V XY =4 / 3VIN1.

[0039] The PMOS current mirrors are M1 to M6, with aspect ratios of 16K. p 8K p 4K p 2K p 1Kp 1K p K p The minimum aspect ratio for PMOS current mirrors is 16K. For NMOS current mirrors, the ratios are M27 to M32, with aspect ratios of 16K. n 8K n 4K n 2K n 1K n 1K n K n This represents the minimum width-to-length ratio of the NMOS current mirror. The current selection switches for the PMOS current mirror are M7 to M16, and for the NMOS current mirror, they are M17 to M26. Their control signals are S1 to S5 and SN1 to SN5, with opposite phases. The P-type and N-type current mirror circuits divide the current in a 16:8:4:2:1:1 ratio, and their input terminals are multiplexed with the gain amplifier.

[0040] The A terminal of resistor string Rs1, i.e., the first input terminal, is connected to the negative terminal of resistor R7 and the drain of P-type selector switches M7, M9, M11, M13, and M15; the B terminal of resistor string Rs1, i.e., the second input terminal, is connected to the positive terminal of resistor R9 and the drain of N-type selector switches M17, M19, M21, M23, and M25; the C terminal of resistor string Rs2, i.e., the first input terminal, is connected to the negative terminal of resistor R8 and the drain of P-type selector switches M8, M10, M12, M14, and M16; the D terminal of resistor string Rs2, i.e., the second input terminal, is connected to the positive terminal of resistor R10 and the drain of N-type selector switches M18, M20, M22, M24, and M26.

[0041] The control signals for P-type selector switches M7, M9, M11, M13, M15 and N-type selector switches M17, M19, M21, M23, M25 are S1 to S5; the control signals for P-type selector switches M8, M10, M12, M14, M16 and N-type selector switches M18, M20, M22, M24, M26 are SN1 to SN5. The control signals S1 to S5 are out of phase with SN1 to SN5. The shunt resistors R7 to R10 have a resistance of R, and the resistor strings Rs1 and Rs2 consist of seven resistors with a resistance of R connected in series. The control timing of the current selection switches ensures that the current flowing through Rs1 and Rs2 remains constant, and the voltage value V... A V B Difference V AB V remains unchanged C V D Difference V CD It remains unchanged.

[0042] The current selection switch circuit includes a P-type current selection switch circuit and an N-type current selection switch circuit. The P-type current selection switch circuit includes M7 to M16, and the N-type current selection switch circuit includes M17 to M26. The control signals of the current selection switch are S1 to S5 and SN1 to SN5, which are opposite in phase. For the P-type current selection switch, the current selection switch is turned on when the control signal is low; for the N-type current selection switch, the current selection switch is turned on when the control signal is high. R7 to R10 are shunt resistors with a resistance value of R. The resistor strings Rs1 and Rs2 are composed of seven resistors with a resistance value of R connected in series. The control timing of the current selection switch ensures that the current flowing through Rs1 and Rs2 remains constant. Changing the current and voltage drop across the shunt resistors changes the voltage value across the resistor string circuit. The resistor string circuit interpolates this voltage value, and its output is a differential output voltage used for comparator offset calibration.

[0043] like Figure 1 As shown, AMP1 and AMP2 are gain amplifiers, R1 to R6 are feedback resistors, VIN1 and VIN2 are input reference signals, and a constant voltage difference V is generated between nodes X and Y. XY M1 to M6 are P-type current mirror circuits, M7 to M16 are current selection switches for P-type current mirrors, M27 to M32 are N-type current mirror circuits, and M17 to M26 are current selection switches for N-type current mirrors. R7 to R10 are shunt resistors, and Rs1 and Rs2 are resistor strings used to generate dither signals through voltage division.

[0044] like Figure 2 As shown, the present invention provides a method for constant voltage V XY The principle behind the constant voltage in the generated circuit is as follows:

[0045] The voltage at node X is V x The voltage at node Y is V. Y Then the voltage at the input terminal of gain amplifier AMP1 is 3 / 7V. x According to the Kirchhoff current equation at the negative input of AMP1, we can obtain (VIN1-3 / 7V) x ) / 3R=(3 / 7V x -V Y ) / 4R; According to the Kirchhoff current equation at the positive input node of AMP2, we can obtain (V x -VIN2) / 4R=(VIN2-V Y ) / 4R, we get the voltage V at node X. X =VIN2 + 2 / 3VIN1, the voltage at node Y is V Y=VIN2-2 / 3VIN1, creating a constant voltage difference V between node X and node Y that depends only on VIN1. XY =4 / 3VIN1.

[0046] like Figure 3 The diagram shown is a simplified circuit diagram for implementing dither injection provided by this invention. By changing the shunt resistor R7, the voltage value V across the resistor strings Rs1 and Rs2 can be changed. A V B V C V D This ensures that the current flowing through resistors Rs1 and Rs2 remains constant, achieving differential output of the dither voltage and precise control of its value. The principle is as follows:

[0047] There is a constant voltage difference V between nodes X and Y. XY This voltage can be expressed by two expressions: based on branches R7, Rs1, and R9, V XY =I a1 R+(I a1 +I1)7R+I b2 R, based on branches V of R8, Rs2, and R10 XY =I b1 R+(I b1 +I2)7R+I a2 R can lead to I a1 =I a2 I b1 =I b2 Setting I a1 =I a2 =I a I b1 =I b2 =I b According to Kirchhoff's current law, equation I can be written. a +I b =I1+I2=16I0,I a +I1=I b +I2, we can derive I1 = I b I2 = I a Therefore, the current flowing through Rs1 and Rs2 remains constant at 16I0. The values ​​of I1 and I2 are changed by the timing control of the current selection switch. The timing generation circuit for this control is... Figure 4 Given that the control code ADJ<4:1> is provided by a random signal generator, it generates control signals S1~S5 and SN1~SN5, which change the voltage across the shunt resistor and thus change the voltage value V across the resistor series Rs1 and Rs2. A V B V C VD Voltage value V A V B Difference V AB V remains unchanged C V D Difference V CD By keeping it constant, precise control of the dither voltage value can be achieved.

[0048] This embodiment employs subtraction dithering for Dither injection. Before quantization, a pseudo-random noise is added to the signal. After quantization, the same pseudo-random noise is subtracted from the digital signal, ensuring it has no direct impact on the final output. Compared to traditional Dither injection methods, this approach does not increase the overall noise energy of the system, breaks the fixed pattern of quantization error, and makes it closer to white noise, thus improving signal quality. The Dither injection circuit for comparator front-end calibration provided in this embodiment uses a gain amplifier and a current mirror circuit for amplifier multiplexing. This gain amplifier generates a fixed voltage difference while providing initial current for the current mirror circuit. The current selection switch circuit provided in this embodiment can control the current shunting through a control signal. By changing the voltage value across the resistor string circuit through the shunting resistor, the shunting resistor and the resistor string resistor use the same resistor type, ensuring that the differential output Dither voltage used for comparator offset calibration is compensated for process deviations under different temperatures and process angles.

[0049] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A dither injection circuit for comparator foreground calibration, characterized by The application relates to a gain amplifier circuit, a resistance feedback network circuit, a current mirror circuit, a current selection switch circuit, a shunt resistance and a resistance string circuit. The gain amplifier circuit is connected with the resistance feedback network circuit and the current mirror circuit respectively. The resistance feedback network circuit, the current mirror circuit and the current selection switch circuit are connected with the shunt resistance respectively. The resistance string circuit is connected with the shunt resistance and the current selection switch circuit respectively. The gain amplifier circuit comprises gain amplifiers AMP1 and AMP2.

2. The dither injection circuit for comparator front porch calibration of claim 1, wherein: The gain amplifier AMP1 is connected with the resistance feedback network circuit and the current mirror circuit respectively. The gain amplifier AMP2 is connected with the resistance feedback network circuit and the current mirror circuit respectively. The resistance feedback network circuit comprises resistors R1, R2, R3, R4, R5 and R6.

3. The dither injection circuit for comparator front porch calibration of claim 2, wherein: An input reference voltage VIN1 is connected to the negative terminal of the gain amplifier AMP1 through the resistor R1, and an input reference voltage VIN2 is directly connected to the negative terminal of the gain amplifier AMP2. One end of the resistor R2 is grounded, and the other end of the resistor R2 is connected with the positive terminal of the gain amplifier AMP1 and one end of the resistor R4 respectively. The other end of the resistor R4 is connected with the shunt resistance and one end of the resistor R6 respectively, and the other end of the resistor R6 is connected with the positive terminal of the gain amplifier AMP2. One end of the resistor R3 is connected with the negative terminal of the gain amplifier AMP1, the other end of the resistor R3 is connected with one end of the resistor R5, and the other end of the resistor R5 is connected with the positive terminal of the gain amplifier AMP2. The current mirror circuit comprises a P-type current mirror circuit and an N-type current mirror circuit.

4. The dither injection circuit for comparator front porch calibration of claim 3, wherein: The P-type current mirror circuit is connected with the output terminal of the gain amplifier AMP1, the shunt resistance and the resistance feedback network circuit respectively. The N-type current mirror circuit is connected with the output terminal of the gain amplifier AMP2, the shunt resistance and the resistance feedback network circuit respectively. The P-type current mirror circuit comprises PMOS tubes M1, M2, M3, M4, M5 and M6.

5. The dither injection circuit for comparator front porch calibration of claim 4, wherein: The output terminal of the gain amplifier AMP1 is connected with the gate of the PMOS tube M1, the gate of the PMOS tube M2, the gate of the PMOS tube M3, the gate of the PMOS tube M4, the gate of the PMOS tube M5 and the gate of the PMOS tube M6 respectively. The source of the PMOS tube M1, the source of the PMOS tube M2, the source of the PMOS tube M3, the source of the PMOS tube M4, the source of the PMOS tube M5 and the source of the PMOS tube M6 are all connected with a power supply. The drain of the PMOS tube M1 is connected with the shunt resistance and the other end of the resistor R4 respectively. The drain of the PMOS tube M2, the drain of the PMOS tube M3, the drain of the PMOS tube M4, the drain of the PMOS tube M5 and the drain of the PMOS tube M6 are all connected with the current selection switch circuit. ​ 6. The dither injection circuit for comparator front porch calibration of claim 5, wherein: The N-type current mirror circuit comprises NMOS tubes M27, M28, M29, M30, M31 and M32. The output terminals of the gain amplifier AMP2 are connected to the gates of the NMOS tubes M27, M28, M29, M30, M31 and M32 respectively. The sources of the NMOS tubes M27, M28, M29, M30, M31 and M32 are grounded. The drain of the NMOS tube M27 is connected to the shunt resistor and the other end of the resistor R3.

7. The dither injection circuit for comparator front porch calibration of claim 6, wherein: The current selection switch circuit comprises a P-type current selection switch circuit and an N-type current selection switch circuit.

8. The dither injection circuit for comparator front porch calibration of claim 7, wherein: The P-type current selection switch circuit comprises PMOS tubes M7, M8, M9, M10, M11, M12, M13, M14, M15 and M16. The sources of the PMOS tubes M7 and M8 are connected to the drain of the PMOS tube M2. The sources of the PMOS tubes M9 and M10 are connected to the drain of the PMOS tube M3. The sources of the PMOS tubes M11 and M12 are connected to the drain of the PMOS tube M4. The sources of the PMOS tubes M13 and M14 are connected to the drain of the PMOS tube M5. The sources of the PMOS tubes M15 and M16 are connected to the drain of the PMOS tube M6. The drains of the PMOS tubes M7, M8, M9, M10, M11, M12, M13, M14, M15 and M16 are connected to the shunt resistor and the resistor string circuit respectively.

9. The dither injection circuit for comparator front porch calibration of claim 8, wherein: The N-type current selection switch circuit comprises NMOS tubes M17, M18, M19, M20, M21, M22, M23, M24, M25 and M26. The drains of the NMOS tubes M17 and M18 are connected to the drain of the NMOS tube M28. The drains of the NMOS tubes M19 and M20 are connected to the drain of the NMOS tube M29. The drains of the NMOS tubes M21 and M22 are connected to the drain of the NMOS tube M30. The drains of the NMOS tubes M23 and M24 are connected to the drain of the NMOS tube M31. The drains of the NMOS tubes M25 and M26 are connected to the drain of the NMOS tube M32. The drain of the NMOS tube M23 and the drain of the NMOS tube M24 are both connected with the drain of the NMOS tube M31; The drain of the NMOS tube M25 and the drain of the NMOS tube M26 are both connected with the drain of the NMOS tube M32; The source of the NMOS tube M17, the source of the NMOS tube M18, the source of the NMOS tube M19, the source of the NMOS tube M20, the source of the NMOS tube M21, the source of the NMOS tube M22, the source of the NMOS tube M23, the source of the NMOS tube M24, the source of the NMOS tube M25 and the source of the NMOS tube M26 are all connected with a shunt resistor and a resistor string circuit respectively.

10. The dither injection circuit for comparator front porch calibration of claim 9, wherein: The shunt resistor comprises resistors R7, R8, R9 and R10, and the resistor string circuit comprises resistor strings Rs1 and Rs2; wherein, One end of the resistor R7 and one end of the resistor R8 are both connected with the drain of the PMOS tube M1; The other end of the resistor R7 and the first input end of the resistor string Rs1 are both connected with the drain of the PMOS tube M7; The other end of the resistor R8 and the first input end of the resistor string Rs2 are both connected with the drain of the PMOS tube M8; One end of the resistor R9 and one end of the resistor R10 are both connected with the drain of the NMOS tube M27; The other end of the resistor R9 and the second input end of the resistor string Rs1 are both connected with the drain of the NMOS tube M17; The other end of the resistor R10 and the second input end of the resistor string Rs2 are both connected with the drain of the NMOS tube M18.

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