Electronic device with reduced electric field in superficial layer and method of manufacturing same

Abstract

The invention relates to an electronic device with a reduced electric field in a superficial layer and a method of manufacturing the same. A galvanic isolation device includes a metal cap layer extending over a top metal layer of a galvanic isolation module. The metal cap layer is in electrical contact with the top metal layer at a central portion of the top metal layer. The buffer layer separates the metal cap layer from the top metal layer at a peripheral portion of the top metal layer. Electric field peaks at the edges of the metal cap layer and the top metal layer are decoupled from each other by recessing side edges of the metal cap layer a distance (e.g., greater than 1 micron) from corresponding edges of the top metal layer.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of priority of Italian Patent Application No. 102024000015754, filed on July 9, 2024, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] Embodiments herein relate to an electronic device and a method of manufacturing thereof, and in particular to a current-isolation device featuring a reduced electric field strength in superficial layers. BACKGROUND

[0004] Current-isolation (GI) is known for providing isolation of different functional parts of an electrical system to prevent current flow by avoiding a direct conductive path. Current-isolation can be realized in particular by capacitive coupling or inductive coupling.

[0005] Figure 1 A portion of a current-isolation (GI) based device 1 is schematically illustrated in a lateral cross-sectional view on the xz-plane in a three-axes system with the axes x, y, z being mutually orthogonal. In particular, the GI device 1 is a capacitive-coupling GI device.

[0006] The GI device 1 comprises a solid body 10. The solid body 10 comprises a substrate 110, a first dielectric layer 112 extending on the substrate 110, a bottom metal layer 114 extending within the first dielectric layer 112 at a first height along the z-axis, and a top metal layer 116 extending within the first dielectric layer 112 at a second height along the z-axis greater than the first height. A surface 116a of the top metal layer 116 is coplanar with a surface 112a of the first dielectric layer 112, both surfaces lying on the xy-plane. Two side surfaces 116b and 116c of the top metal layer 116 extend in the yz-plane and are in direct contact with the first dielectric layer 112. The two side surfaces 116b and 116c are also referred to as “top metal edges” 116b and 116c.

[0007] The bottom metal layer 114, the first dielectric layer 112, and the top metal layer 116 form a capacitor through which different parts of an electrical system (not shown) can be coupled for transmission of electrical signals while being isolated from each other to avoid direct current flow.

[0008] The GI device 1 also includes a dielectric or insulating buffer layer 120 that extends over and in contact with the top metal layer 116 (i.e., on the top surface 116a), at two peripheral portions of the top surface 116a, and laterally to the top metal layer 116 over and in contact with the top surface 112a of the first dielectric layer 112. A metal layer 118 (also referred to as a "capping layer," and hereinafter as a "cap layer 118") is typically made of aluminum, and extends over and in contact with a central portion of the top surface 116a (including between the two peripheral portions of the top surface 116a), and over and in contact with the buffer layer 120. Two side surfaces 118b and 118c of the cap layer 118 extend in the yz plane, and are also referred to as "cap edges" 118b and 118c. The function of the cap layer 118 is to provide a suitable surface for the bonding of external wiring elements. The top metal edge 116b and the cap edge 118b extend in alignment with each other parallel to the z-axis. Similarly, the top metal edge 116c and the cap edge 118c also extend in alignment with each other parallel to the z-axis. In other words, the top metal edge 116b and the cap edge 118b lie on the same plane parallel to the yz plane, and the top metal edge 116c and the cap edge 118c lie on the same respective plane parallel to the yz plane. A second dielectric layer 122 extends over the buffer layer 120 and the cap layer 118, and contains a via 119 that is at least partially aligned with the central portion of the top surface 116a along the z-axis; a top surface 118a of the cap layer 118 is exposed through the via 119. The GI device 1 also includes an organic passivation layer 124 that extends over the second dielectric layer 122; a via 121 extends through the organic passivation layer 124 at least partially in alignment with the via 119. A bonding structure 126 extends through the vias 119, 121 to the cap layer 118 at the top surface 118a and in electrical contact therewith. For example, wire bonding can be used. A molding compound (MC) layer 125 fills the vias 119 and 121, thereby enclosing and protecting the bonding structure 126 within the vias 119, 121; the MC layer 125 can also extend over the organic passivation layer 124. The stack formed by the organic passivation layer 124 and the MC layer 125 is also referred to as a "polymer stack."

[0009] The buffer layer 120 is typically made of silicon oxide or silicon nitride, and has a thickness in the range of 400 to 800 nm. The second dielectric layer 122 is typically made of silicon oxide or silicon nitride, and has a thickness in the range of 2 to 6 pm.

[0010] In the technical field of GI devices, it is known that high electric fields (i.e. electric fields with values higher than 0.8 MV / cm) and high voltages (i.e. voltages higher than 1000 V, preferably higher than 1500 V) can be the cause of aging mechanisms that can be observed during reliability tests. These aging mechanisms mainly affect the polymer stacks 124, 125 located in the regions corresponding to the peaks of the electric field.

[0011] The peaks of the electric field are generated at the top metal edges 116b, 116c and at the cap edges 118b, 118c and extend into the polymer stacks 124, 125. The electric field strength in the polymer stacks 124, 125 depends on the thickness of the second dielectric layer 122. A higher thickness of the second dielectric layer 122 allows to withstand higher electric fields, thus prolonging the Time-To-Failure (TTF) of the aging mechanisms.

[0012] Therefore, one solution is to increase the thickness of the second dielectric layer 122. However, this solution can bring some drawbacks in the manufacturing process, including: thicker photoresist to be exposed; more time consuming and difficult etching leading to complete depletion of the photoresist; and more complex wet removal scheme for cleaning the structure to be achieved after etching. The overall consequence of these drawbacks is to reduce the manufacturing yield and to increase the production costs.

[0013] Accordingly, there is a need in the art to provide an electronic device and a method of manufacturing thereof that overcomes the above drawbacks. SUMMARY

[0014] In an embodiment, an electronic device comprises: a solid body comprising a metal structure having a top surface lying on a plane and having a thickness along a first direction orthogonal to the top surface; a metal layer on the metal structure, the metal layer comprising a central portion, a first peripheral portion and a second peripheral portion, the first and second peripheral portions being located at opposite ends of the central portion, the central portion being in direct electrical contact with said surface of the metal structure, the first and second peripheral portions being physically and electrically continuous with the central portion; and a first insulating layer between the metal structure and the first and second peripheral portions of the metal layer.

[0015] The metal structure has at least a first side surface of a corresponding portion of the metal structure laterally to said plane; and the first peripheral portion of the metal layer has a respective first side surface laterally to said plane.

[0016] The first side surface of the metal layer is recessed from the first side surface of the metal structure along a second direction orthogonal to the first direction by a first distance. This first distance can for example be equal to or greater than one micrometer.

[0017] In an embodiment, a method of manufacturing an electronic device comprises the steps of: providing a solid body comprising a metal structure having a top surface lying on a plane and having a thickness along a first direction orthogonal to the top surface; forming a first insulating layer on said surface of the metal structure; forming a first via through the first insulating layer up to a corresponding portion of said surface of the metal structure; and forming a metal layer within the first via and on the first insulating layer. The forming of the metal layer comprises: forming a central portion through the first via in direct electrical contact with said surface of the metal structure; forming a first peripheral portion at one end of the central portion and on the first insulating layer; and forming a second peripheral portion at the opposite end of the central portion and on the first insulating layer, the first and second peripheral portions being formed in physical and electrical continuity with the central portion.

[0018] The metal structure has at least a first side surface laterally to said plane externally delimiting the corresponding portion of the metal structure; and the first peripheral portion of the metal layer has a respective first side surface laterally to said plane.

[0019] The first side surface of the metal layer is formed recessed from the first side surface of the metal structure by a first distance along a second direction orthogonal to the first direction. This first distance may, for example, be equal to or greater than one micron. BRIEF DESCRIPTION OF DRAWINGS

[0020] For a better understanding of the present application, some embodiments thereof will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0021] Figure 1 A portion of a current-insulating device is schematically illustrated in a lateral cross-sectional view;

[0022] Figure 2A A portion of an electronic device, in particular a current-insulating (GI) device, is schematically illustrated in a lateral cross-sectional view;

[0023] Figure 2B A portion of a GI device of Figure 2A is illustrated in a top view, wherein Figure 2A the cross-sectional view of Figure 2B is taken along the cutting line II-II of

[0024] Figure 3 A portion of a GI device is schematically illustrated in a lateral cross-sectional view; and

[0025] Figures 4A-4G The manufacturing steps of a GI device of Figure 2A are illustrated in a lateral cross-sectional view (similarly, Figure 3 the manufacturing steps of a GI device of DETAILED DESCRIPTION

[0026] Figure 2A A portion of an electronic device 20 comprising a galvanic isolator (GI) module is schematically illustrated.

[0027] The electronic device 20 is hereinafter also referred to as GI device 20. The GI device 20 is represented in a lateral cross-sectional view parallel to the xz-plane in a three-axial system with axes x, y, z being mutually orthogonal.

[0028] Figure 2B A portion of the GI device 20 is illustrated in a top view on the xy-plane, wherein Figure 2A the cross-sectional view is taken along the cutting plane II-II of Figure 2A For a better understanding and to make the drawing clearer, Figure 2B only some features of Figure 2B are illustrated. Figure 2A

[0029] The GI device 20 comprises a solid body 200. In particular, the solid body 200 comprises a substrate 210 of e.g. a semiconductor material such as silicon (Si), silicon carbide (SiC of any polytype), sapphire (AI2O3), GaN. The substrate 210 can also comprise a plurality of layers that are epitaxially grown or deposited e.g. via chemical vapor deposition (CVD) or physical vapor deposition (PVD) and patterned via different lithography and etching steps.

[0030] The solid body 200 further comprises a bottom metal layer 214 (e.g. made of copper or aluminum) extending on a superficial portion of the substrate 210, a first intermetal dielectric layer 209 extending on the substrate 210 laterally to the bottom metal layer 214, an intermediate dielectric layer 211 extending on the first intermetal dielectric layer 209 and on the bottom metal layer 214, a top metal layer 216 (e.g. made of copper) extending on a superficial portion of the intermediate dielectric layer 211, and a second intermetal dielectric layer 213 extending on the intermediate dielectric layer 211 laterally to the top metal layer 216. The bottom and top metal layers 214, 216 at least partially overlap each other along the z-axis. The intermediate dielectric layer 211 extends between the bottom and top metal layers 214, 216 such that the bottom and top metal layers 214, 216 are capacitively coupled together, thereby forming a capacitor of the galvanic isolation module. In one embodiment, different portions of an electrical system (not shown) can be coupled by such capacitors to transmit electrical signals during use while avoiding direct galvanic flow.

[0031] ​Exemplarily, the intermediate dielectric layer 211 and the second intermetal dielectric layer 213 are a single layer (i.e., formed in a single deposition step), with the top metal layer 216 being inserted in a recess formed in the dielectric material. Exemplarily, the first intermetal dielectric layer 209 and the intermediate dielectric layer 211 are two different layers (i.e., formed in two different deposition steps). In the following disclosure, the first intermetal dielectric layer 209, the intermediate dielectric layer 211 and the second intermetal dielectric layer 213 are collectively referred to as the first dielectric layer 212. The first intermetal dielectric layer 209, the intermediate dielectric layer 211 and the second intermetal dielectric layer 213 can be the same dielectric material, or can be respective dielectric (or, in other cases, insulating) materials, including silicon oxide, silicon nitride, etc. The bottom metal layer 214 extends within the first dielectric layer 212 at a first height along the z-axis, and the top metal layer 216 extends within the first dielectric layer 212 at a second height along the z-axis that is greater than the first height.

[0032] In one embodiment, the surface 216a of the top metal layer 216 is coplanar with the surface 212a of the first dielectric layer 212, and parallel to the xy-plane; thus, the surfaces 212a and 216a as a whole form a surface of the solid body 200.

[0033] In Figure 2A In a cross-sectional view of the solid body 200, the two side surfaces 216b and 216c of the top metal layer 216 depart from the surface 216a at opposite sides of the top metal layer 216 along the x-axis, towards the bottom metal layer 214, parallel to the yz-plane. In particular, the side surfaces 216b and 216c are in direct contact with the first dielectric layer 212. These two side surfaces 216b, 216c are also referred to hereinafter as top metal edges 216b, 216c. In general, these two side surfaces 216b, 216c extend transversely to the plane on which the surface 216a of the top metal layer 216 lies, i.e., they extend transversely to the xy-plane or to a plane parallel to the xy-plane.

[0034] The GI device 20 further comprises a buffer layer 220 (made of a dielectric or insulating material, such as silicon oxide or silicon nitride) that extends over the surface 216a of the top metal layer 216, and optionally laterally to the top metal layer 216 over the surface 212a of the first dielectric layer 212.

[0035] In an embodiment, the buffer layer 220 is in direct contact with the top metal layer 216 and the first dielectric layer 212 at the respective surfaces. In another embodiment, a first adhesion layer (not shown) is interposed between the buffer layer 220 and the top metal layer 216 and / or between the buffer layer 220 and the first dielectric layer 212. Figure 2AA first adhesion layer (not shown) is extended between the surface 216a of the top metal layer 216 and the buffer layer 220, in direct contact with the top metal layer 216 and the buffer layer 220. The first adhesion layer is made of, for example, a nitride material (e.g., silicon nitride). The first adhesion layer can have a dual function of both facilitating adhesion between the buffer layer 220 and the top metal layer 216 and covering the top metal layer (i.e., avoiding migration of the metal material in the buffer layer 220).

[0036] The buffer layer 220 has a through opening 221 through which a portion of the surface 216a of the top metal layer 216 is exposed.

[0037] The conductive cap layer 218 (hereinafter referred to as "cap layer" 218) extends partially over the buffer layer 220 (portions 219b and 219c of the cap layer 218) and partially within the through opening 221 of the buffer layer 220 (portion 219a of the cap layer 218), thereby electrically contacting the top metal layer 216. In particular, the conductive cap layer 218 is made of or comprises one or more metal materials, for example, it is made of aluminum or an aluminum alloy. The portion 219b is electrically connected to the portion 219a on one side of the portion 219a; the portion 219c is electrically connected to the portion 219a on the other, opposite side of the portion 219a. The portions 219a-219c are formed as one single layer extending with electrical and physical continuity.

[0038] In one embodiment, in order to improve the manufacturing process, the portion 219b has a length along the x-axis of at least 2 μιη; similarly, the portion 219c also has a length along the x-axis of at least 2 μιη.

[0039] The cap layer 218 has a bottom surface 218a' facing directly the top metal layer 216 and a top surface 218a opposite the bottom surface 218a' along the z-axis. The cap layer 218 is terminated on one side by a first side surface 218b and on the other side by a second side surface 218c. The first side surface 218b and the second side surface 218c connect the top surface 218a to the bottom surface 218a'. In particular, the side surfaces 218b, 218c extend parallel to the yz plane. In the following, the side surfaces 218b, 218c are also referred to as "cap edges" 218b, 218c. In general, the two side surfaces 218b, 218c extend transversely to the plane on which the surface 218a of the cap layer 218 lies, i.e., they extend transversely to the xy plane or to a plane parallel to the xy plane.

[0040] The function of the cap layer 218 is to provide a suitable surface for the bonding (e.g., by means of wire bonding).

[0041] The cap edges 218b, 218c are misaligned along the z-axis from the top metal edges 216b, 216c, respectively. In particular, as shown in the top view on the xy-plane, the cap layer 218 is entirely contained within the top metal layer 216, such that the cap layer 218 covers only a central portion of the top metal layer 216, leaving an outer portion 229 of the top metal layer 216 uncovered (the cap layer 218 is not above the outer portion 229 of the top metal layer 216). In the top view, the outer portion 229 of the top metal layer 216 completely surrounds the central portion of the top metal layer 216. Figure 2B

[0042] The outer portion 229 of the top metal layer 216 has a dimension OV1 along the x-axis between the cap edge 218b and the top metal edge 216b. The outer portion of the top metal layer 216 has a dimension OV2 along the x-axis between the cap edge 218c and the top metal edge 216c.

[0043] In other words, OV1 and OV2 are distances along the x-axis and in the top view between the cap edge 218b and the top metal edge 216b, and between the cap edge 218c and the top metal edge 216c, respectively.

[0044] Preferably, the distances OV1 and OV2 are greater than or equal to 1 pm. More preferably, the distances OV1 and OV2 are greater than or equal to 2 pm.

[0045] The values of the distances OV1 and OV2 can vary in the range 1-50 pm, in particular in the range 2-31 pm, even more preferably in the range 10-15 pm. For example, these distances can be substantially equal to 2 or 31 pm, where “substantially equal to” means within + / - 3% of the target value.

[0046] In one non-limiting embodiment, the distance OV1 is equal to the distance OV2.

[0047] In general, the above-disclosed arrangement of the cap edge 218b and the top metal edge 216b allows decoupling the electric field peak located at the cap edge 218b from the electric field peak located at the top metal edge 216b. Similarly, the cap edge 218c and the top metal edge 216c are arranged inversely according to the above-disclosed arrangement of the cap edge 218b and the top metal edge 216b, thereby allowing decoupling the electric field peak located at the cap edge 218c from the electric field peak located at the top metal edge 216c.

[0048] In particular, the electric peak decoupling is obtained by recessing the top metal edges 216b, 216c from the respective cap edges 218b, 218c by the distances OV1 and OV2.

[0049] ​It is noted that Figure 2A the cross-sectional view is taken along a section line II-II parallel to the x-axis of the GI device 20. However, according to embodiments, there is also the same or a similar cross-section along a section line II'-II' parallel to the y-axis of the GI device 20. Thus, the aforementioned disclosure applies analogously to such cross-sectional view along the line II'-II', in particular with respect to the presence of a dimension along the y-axis corresponding to the distances OV1 and OV2. Figure 2B

[0050] In an embodiment, the GI device 20 additionally comprises a second dielectric layer 222 extending above the buffer layer 220 and the cap layer 218 and comprising a via 230 at least partially aligned with a portion 219a of the cap layer 218 along the z-axis, i.e. with a portion of the cap layer 218 directly contacting the top metal layer 216. Thus, a surface 218a of the portion 219a is exposed by the via 230.

[0051] In an embodiment, the GI device 20 further comprises an organic passivation layer 224 extending above the second dielectric layer 222 and a via 232 extending through the organic passivation layer 224 at least partially aligned with the via 230.

[0052] Exemplarily, a bonding structure 226 extends through the vias 230, 232 to and electrically contacts the cap layer 218 at the portion 219a. For example, wire bonding can be used. A molding compound (MC) layer 225 at least partially fills the vias 230, 232, thereby enclosing and protecting the bonding structure 226 within the vias 230, 232. The MC layer 225 can also extend above the organic passivation layer 224. The stack formed by the organic passivation layer 224 and the MC layer 225 is also referred to as "polymer stack" 224, 225.

[0053] The buffer layer 220 is for example made of silicon oxide or silicon nitride. In Figures 2A-2B an embodiment, the thickness "t bo " of the buffer layer 220 along the z-axis is for example in the range of 400 to 800 nm. The second dielectric layer 222 is for example made of silicon oxide or silicon nitride. The thickness "t so " of the second dielectric layer 222 is for example in the range of 2 to 6 pm.

[0054] In an embodiment, a second adhesive layer (not shown) physically couples the organic passivation layer 224 and the second dielectric layer 222 together. The second adhesive layer, which can also have a sealing function, is for example made of a nitride material, e.g. silicon nitride.

[0055] ​In one exemplary embodiment: the bottom metal layer 214 is made of copper and has a thickness in the range of 0.5 to 1.5 pm; the first dielectric layer 212 is made of silicon oxide and has a total thickness in the range of 4 to 20 pm, for example 10 pm; the top metal layer 216 is made of copper and has a thickness in the range of 2 to 4 pm; the cap layer 218 is made of aluminum and has a thickness in the range of 0.5 to 1.5 pm, preferably 1 pm; the distances OV1, OV2 are in the range of 10 to 15 pm, in particular 14 pm; the buffer layer 220 is made of silicon oxide and has a thickness "t bo " in the range of 400 to 800 nm, in particular 600 nm; and the second dielectric layer 222 is made of silicon oxide and has a thickness "t so " in the range of 2 to 6 pm, in particular 4.5 pm.

[0056] The buffer layer 220 and the second oxide layer 222 form together an "inorganic passivation". The inorganic passivation has a thickness "t ip " along the z-axis, given by the sum of t bo and t so . The inorganic passivation thickness t ip is in the range of 2.4 to 6.8 pm, in particular 5.1 pm.

[0057] The organic passivation layer 224 is for example made of polyimide and has a thickness in the range of 5 to 20 pm, in particular 9 pm. The MC layer 225 is made of a polymeric material, for example a composite polymeric material with oxide filler, and has a thickness in the range of 7 to 26 pm.

[0058] By introducing the OV1, OV2 distances, a decoupling of the electric field located at the two metal edges on each side of the device, i.e. the cap edge 218b and the top metal edge 216b on one side, and the cap edge 218c and the top metal edge 216c on the other side, is obtained. Thus, the main electric field peaks are confined at the top metal edges 216b, 216c. Due to the presence of the outer region 229 which is not covered by the cap layer 218, the inorganic passivation thickness t so is greater than the second dielectric layer 222 thickness t ip The top metal edges 216b, 216c, i.e. the zones where the electric field intensity is the highest, are separated from the polymeric stack 224, 225, thus reducing the electric field intensity in the polymeric stack 224, 225.

[0059] In this way, a reduction of the electric field intensity in the polymeric stack 224, 225 is obtained. The electric field intensity in the polymeric stack 224, 225 is reduced and the TTF in reliability tests is improved.

[0060] Reference is made to Figure 3 , describing another embodiment. In Figure 3 , the upper portion of the GI device 30 is illustrated in the same tri-axial system of axes x, y, z and in the same lateral cross-sectional view as Figure 2A . In Figure 2A , the GI device 30 is illustrated in the same tri-axial system of axes x, y, z and in the same lateral cross-sectional view as Figure 3 . In Figure 2A , the GI device 30 is illustrated in the same tri-axial system of axes x, y, z and in the same lateral cross-sectional view as

[0061] In the GI device 30, the thickness t bo of the buffer layer 220 is increased, thereby forming a corresponding buffer layer 320 having an increased thickness t bo ' in the range of 2 to 6 pm, in particular 4 pm. The thickness t bo ' of the buffer layer 320 allows to reach a total inorganic passivation thickness t ip ' in the range of 4 to 12 pm, in particular 8.5 pm, which separates the top metal edge 216b from the polymer stack. In this way, since the inorganic passivation thickness t ip ' is increased with respect to the embodiment of Figures 2A-2B , it is possible to further reduce the impact of the electric field acting on the polymer stack 224, 225, thereby improving the operational lifetime of the device and / or increasing the electrical performance.

[0062] Reference is made to Figures 4A-4G , now describing the manufacturing steps of the portion of the GI device 20 (analogously, of the GI device 30), which are limited to the formation of the relevant elements of the GI device 20. Figures 4A-4G is a lateral cross-sectional view on the xz plane.

[0063] Reference is made to Figure 4A , after the formation of the solid body 200 in a per se known manner (for example, by means of one or more epitaxial growths or depositions on the substrate 210 using PVD or CVD, and one or more mask etching steps), the buffer layer 220 is deposited by means of known deposition processes (for example, by CVD or by atomic layer deposition (ALD)).

[0064] As discussed, in one embodiment (GI device 20, Figure 2A ), the buffer layer 220 has a thickness t bo in the range of 400 to 800 nm, in particular 600 nm.

[0065] In another embodiment (GI device 30, Figure 3) the buffer layer 320 has a thickness t in the range of 2 to 6 pm, in particular 4 pm bo .

[0066] With reference to Figure 4B a mask etching step is performed to remove a selective portion of the buffer layer 220. As a result, a through opening 221 is formed in the buffer layer 220, thereby exposing a portion of the top surface 216a of the top metal layer 216.

[0067] With reference to Figure 4C a deposition step is performed to form a metal layer 618. In particular, an aluminum deposition step is performed (the portion of the metal layer 618 filling the through opening 221 forms a central portion 219a of the cap layer 218).

[0068] With reference to Figure 4D a mask etching step of the metal layer 618 is performed in a per se known manner (e.g. by means of photolithography followed by dry etching) to remove a selective portion of the peripheral region of the metal layer 618, thereby forming the cap layer 218 having peripheral portions 219b and 219c, with the respective cap edges 218b, 218c being recessed with respect to the top metal edges 216b, 216c. Figure 4D The mask etching step of the metal layer 618 comprises forming an etch mask that protects the central portion of the metal layer 618 from the etchant, leaving the peripheral region of the metal layer 618 unprotected. The protected central portion of the metal layer 618 corresponds to the aforesaid regions 219a-219c; the unprotected peripheral region of the metal layer 618 covers the aforesaid outer regions 229.

[0069] Alternatively, other processes can be used for the mask etching, such as a lift-off process or other patterning methods.

[0070] With reference to Figure 4E a deposition step of a second dielectric layer 222 is performed (e.g. by means of CVD). The second dielectric layer 222 is made of, for example, silicon oxide and has a thickness t between 2 and 6 pm, in particular 4.5 pm so .

[0071] With reference to Figure 4F a mask etching step of the second dielectric layer 222 is performed (e.g. by means of photolithography followed by dry etching). As a result, a through opening 230 is formed through the entire thickness of the second dielectric layer 222, thereby exposing the portion 219a of the cap layer 218.

[0072] With reference to Figure 4G the bonding structure 226 and the polymer stack (i.e. the organic passivation layer 224 and the MC layer 225) are formed in a per se known manner.

[0073] As a result, a structure 600 is obtainedFigure 2A Devices.

[0074] Finally, it is evident that modifications and variations may be made to the content described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

[0075] In particular, it should be noted that the scope indicated in this disclosure should be understood to include the boundary values ​​of the corresponding scope.

[0076] The top and bottom metal layers can have any shape selected from quadrilaterals, circles, or approximately polygons, or other shapes in the top view on the xy plane. The shapes of the top and bottom metal layers can be different from each other.

[0077] While previous disclosures have described the top and bottom metal layers as part of a current insulator in the form of a capacitor, the embodiments are equally applicable to current insulators employing inductive coupling; in this case, the top and bottom metal layers are the windings (helices) of a planar inductor, and thus include metal turns.

[0078] Moreover, the disclosed embodiments can also be applied to other technical fields besides current isolation, such as electronic devices for power applications.

[0079] Based on the foregoing explanation, the advantages provided by the embodiments are obvious.

[0080] In particular, improvements in TTF were observed due to the reduction in electric field strength in the polymer stack.

[0081] As has been observed, the recessed cap edges 218b, 218c relative to the top metal edges 216b, 216c allow the electric fields located at the top metal edges 216b, 216c and the cap edges 218b, 218c to decouple from each other, thereby reducing or attenuating the electric field strength in the polymer stack corresponding to these edges.

[0082] Figure 3 In the embodiment, the increased thickness of the buffer layer 320 leads to an increase in the total thickness of the inorganic passivation portion, which further reduces the electric field strength in the polymer stack.

[0083] Therefore, the above results allow for mitigation of the effects of aging mechanisms recorded during reliability testing, thereby extending product lifespan without introducing additional complexity into the manufacturing process.

[0084] It should be noted that when a range is specified in this article, the range explicitly includes the minimum and maximum values ​​of the specified range.

Claims

1. An electronic device comprising: a solid body comprising a metal structure having a top surface lying on a plane and having a thickness along a first direction normal to the top surface; a metal layer on the metal structure, the metal layer comprising a central portion, a first peripheral portion, and a second peripheral portion, the first and second peripheral portions being at opposite ends of the central portion, the central portion being in direct electrical contact with the surface of the metal structure, the first and second peripheral portions being physically and electrically continuous with the central portion; a first insulating layer between the metal structure and the first and second peripheral portions of the metal layer; wherein the metal structure has at least a first side surface of a corresponding portion of the metal structure laterally to the plane externally bounding the corresponding portion of the metal structure; and the first peripheral portion of the metal layer has a respective first side surface laterally to the plane; and wherein the first side surface of the metal layer is recessed from the first side surface of the metal structure along a second direction normal to the first direction by a first distance equal to or greater than one micron.

2. The electronic device of claim 1, wherein the first distance is in a range of 2 to 31 microns.

3. The electronic device of claim 1, wherein the first distance is substantially equal to 2 microns.

4. The electronic device of claim 1, wherein the first distance is substantially equal to 31 microns.

5. The electronic device of claim 1, wherein the first insulating layer has a thickness along the first direction equal to or greater than 400 nanometers.

6. The electronic device of claim 1, wherein the first insulating layer has a thickness along the first direction equal to or greater than 2 microns.

7. The electronic device of claim 1, further comprising: a second insulating layer on the first insulating layer and on a portion of the metal layer; wherein the second insulating layer comprises a second via at least partially aligned with the central portion of the metal layer along the first direction and extending through the second insulating layer to the metal layer.

8. The electronic device of claim 7, further comprising: a passivation layer extending over the second insulating layer and comprising a third via at least partially aligned with the second via along the first direction.

9. The electronic device of claim 7, further comprising a molding compound filling the second via and the third via.

10. The electronic device of claim 1, further comprising a wire connection electrically coupled to the central portion of the metal layer.

11. The electronic device of claim 1, further comprising a current isolation module, wherein the metal structure is a plate of a capacitor of the current isolation module.

12. The electronic device of claim 1, further comprising a current isolation module, wherein the metal structure is a spiral conductor of an inductor of the current isolation module.

13. The electronic device of claim 1, wherein: the metal structure has at least a second side surface of a corresponding portion of the metal structure laterally to the plane and externally bounding the corresponding portion of the metal structure along the second direction opposite the first side surface; and the first peripheral portion of the metal layer has a respective second side surface laterally to the plane. The second peripheral portion of the metal layer further comprises a respective second side surface opposite the first side surface along a second direction and extending transverse to the plane; and wherein the second side surface of the metal layer is recessed from the second side surface of the metal structure along a second direction orthogonal to the first direction by a second distance in the range of 2 to 31 micrometers.

14. The electronic device of claim 13, wherein the first distance and the second distance have the same value.

15. An electronic device, comprising: a solid body comprising a metal structure having a top surface lying on a plane and having a thickness along a first direction orthogonal to the top surface; a metal layer on the metal structure, the metal layer comprising a central portion, a first peripheral portion, and a second peripheral portion, the first and second peripheral portions being at opposite ends of the central portion, the central portion being in direct electrical contact with the surface of the metal structure, the first and second peripheral portions being physically and electrically continuous with the central portion; and a first insulating layer between the metal structure and the first and second peripheral portions of the metal layer; wherein the first insulating layer has a thickness along the first direction greater than or equal to 2 micrometers.

16. The electronic device of claim 15, wherein the thickness of the first insulating layer is less than or equal to 6 micrometers.

17. The electronic device of claim 16, further comprising a second insulating layer on the first insulating layer and on a portion of the metal layer, wherein the second insulating layer has a respective thickness greater than or equal to 2 micrometers and less than or equal to 6 micrometers.

18. The electronic device of claim 17, further comprising a polymer layer on the second insulating layer.

19. The electronic device of claim 18, wherein a distance between the polymer layer and the metal structure is in the range of 4 to 12 µm.

20. The electronic device of claim 15, wherein the metal structure has at least a first side surface laterally to the plane externally bounding a respective portion of the metal structure; and the first peripheral portion of the metal layer has a respective first side surface laterally to the plane, wherein the first side surface of the metal layer is recessed from the first side surface of the metal structure along a second direction orthogonal to the first direction by a first distance in the range of 2 to 31 micrometers.

21. A method of manufacturing an electronic device, comprising the steps of: providing a solid body comprising a metal structure having a top surface lying on a plane and having a thickness along a first direction orthogonal to the top surface; forming a first insulating layer on the surface of the metal structure; forming a first via through the first insulating layer up to a respective portion of the surface of the metal structure; and forming a metal layer within the first via and on the first insulating layer, wherein forming the metal layer comprises forming a central portion in direct electrical contact with the surface of the metal structure through the first via, forming a first peripheral portion at one end of the central portion and on the first insulating layer, and forming a second peripheral portion at an opposite end of the central portion and on the first insulating layer, the first and second peripheral portions being formed to be physically and electrically continuous with the central portion; wherein the metal structure has at least a first side surface laterally to the plane externally delimiting a corresponding portion of the metal structure; wherein the first peripheral portion of the metal layer has a respective first side surface laterally to the plane; and wherein the first side surface of the metal layer is formed to be recessed from the first side surface of the metal structure along a second direction orthogonal to the first direction by a first distance equal to or higher than one micrometer.

22. The method of claim 21, wherein the first distance is in the range of 2 to 31 micrometers.

23. The method of claim 21, wherein the first distance is substantially equal to 2 micrometers.

24. The method of claim 21, wherein the first distance is substantially equal to 31 micrometers.

25. The method of claim 21, wherein the metal structure has at least a first side surface laterally to the plane externally delimiting a corresponding portion of the metal structure, the first peripheral portion of the metal layer has a respective first side surface laterally to the plane, the first side surface of the metal layer is recessed from the first side surface of the metal structure along a second direction orthogonal to the first direction by a first distance equal to or higher than one micrometer; and the first insulating layer has a thickness along the first direction higher than or equal to 2 micrometers.

26. The method of claim 25, wherein the first distance is in the range of 2 to 31 micrometers, and the thickness of the first insulating layer is less than or equal to 6 micrometers.

Images