Two-dimensional Van der Waals heterostructure-based sensing, storage and calculation integrated device of floating gate type ferroelectric field effect transistor, design and preparation method of sensing, storage and calculation integrated device, and bionic optic neuromorphic chip
By using a floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure, combined with a biomimetic visual neuromorphic chip design, material compatibility and process integration of traditional visual sensors are achieved, improving signal response range and reaction speed, and reducing system power consumption.
Patent Information
- Application Number
- CN202511305032.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2026-01-13
AI Technical Summary
Existing traditional vision sensors face challenges in data processing and energy efficiency, and have poor material and process compatibility.
A floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure is adopted. By sequentially stacking the gate electrode, blocking layer, ferroelectric layer, tunneling layer and two-dimensional semiconductor layer, the photoelectric response characteristics and polarization direction control are realized. Combined with the biomimetic visual neuromorphic chip design, the storage and computing functions of optical signals are realized.
High sensitivity, low power consumption, and real-time processing capabilities are achieved in a single device, solving the material compatibility and process integration problems of traditional solutions, improving signal response range and response speed, and reducing system power consumption.
Smart Images
Figure CN121335153A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and in particular to a sensor-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor, its design and fabrication method, and a biomimetic visual neuromorphic chip. Background Technology
[0002] Amid the rapid development of IoT and AI technologies, global sensor networks are undergoing unprecedented structural changes. In today's rapidly evolving field of intelligent sensing, traditional visual sensing technologies are facing numerous fundamental challenges.
[0003] In existing technologies, firstly, at the data processing level, the amount of raw data generated by mainstream image sensors is extremely large, and the data stream formed during high-speed continuous shooting puts enormous pressure on the transmission bandwidth. Secondly, in terms of energy efficiency, the power consumption of conventional sensor and processor combinations remains high. More critically, there is the issue of material process compatibility; traditional ferroelectric memory materials require high-temperature processing and have low compatibility with standard semiconductor processes.
[0004] Therefore, existing technologies still need improvement and development. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to provide a sensor-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating gate ferroelectric field-effect transistor, its design and fabrication method, and a biomimetic visual neuromorphic chip, in order to address the above-mentioned defects of the prior art.
[0006] The technical solution adopted by this invention to solve the technical problem is as follows: A sensor-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor, comprising: The gate electrode, barrier layer, ferroelectric layer, tunneling layer, two-dimensional semiconductor layer, and source / drain electrodes are stacked sequentially. The two-dimensional semiconductor layer has photoelectric response characteristics, and the tunneling layer is configured to allow photogenerated carriers in the two-dimensional semiconductor layer to tunnel to the ferroelectric layer. When the polarization direction of the ferroelectric layer is toward the two-dimensional semiconductor layer, the ferroelectric layer has a negative photoconductivity effect; when the polarization direction of the ferroelectric layer is away from the two-dimensional semiconductor layer, the ferroelectric layer has a positive photoconductivity effect.
[0007] The aforementioned integrated sensing, storage, and computing device based on a floating-gate ferroelectric field-effect transistor with a two-dimensional van der Waals heterostructure, wherein the integrated sensing, storage, and computing device based on a floating-gate ferroelectric field-effect transistor with a two-dimensional van der Waals heterostructure has a storage time of more than 10 seconds for optical signals.4 s; The two-dimensional semiconductor layer has visible light response characteristics and / or ultraviolet light response characteristics.
[0008] The aforementioned floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure is described in which the two-dimensional semiconductor layer is a two-dimensional transition metal chalcogenide layer, and the two-dimensional transition metal chalcogenide is selected from at least one of MoS2, MoSe2, and WSe2, and the thickness of the two-dimensional semiconductor layer is 5~10nm.
[0009] The aforementioned inductive-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor, wherein the thickness of the barrier layer is greater than the thickness of the tunneling layer.
[0010] The aforementioned floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure is described in a sensor-memory-computing integrated device, wherein the thickness of the barrier layer is 15~35nm and the thickness of the tunneling layer is 5~10nm. The barrier layer includes at least one of an h-BN layer or a SiO2 layer, and the tunneling layer is an h-BN layer. The source and drain electrodes include a source electrode and a drain electrode, both of which are Au / Cr electrodes; the gate electrode is an Au / Cr electrode or a Si electrode.
[0011] The aforementioned floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure is described in the form of an integrated inductor-memory-computer device, wherein the ferroelectric layer is a two-dimensional ferroelectric material layer.
[0012] The aforementioned floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure is described in the following: the two-dimensional ferroelectric material layer is an α-In2Se3 layer or a two-dimensional CuInP2S6 layer, and the thickness of the two-dimensional ferroelectric material layer is 10~50nm.
[0013] A biomimetic visual neuromorphic chip, comprising: at least one device array, the device array including a central device and a plurality of peripheral devices, the plurality of peripheral devices surrounding the central device; Both the central device and the surrounding devices adopt the inductive-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating gate ferroelectric field-effect transistor as described above. The polarization direction of the ferroelectric layer of the central device is opposite to that of the ferroelectric layer of the surrounding device; The drain electrode in the source-drain electrode of the central device and the drain electrode in the source-drain electrode of each of the surrounding devices are connected in parallel.
[0014] A method for designing and fabricating an integrated inductor-memory-computer device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor as described in any of the above claims, comprising the steps of: Fabrication of the gate electrode; After the barrier layer is prepared, it is peeled off and transferred to the gate electrode; After the ferroelectric layer is prepared, it is peeled off and transferred to the barrier layer; After the tunneling layer is prepared, it is peeled off and transferred to the ferroelectric layer; A two-dimensional semiconductor layer is prepared, stripped off, and transferred to the tunneling layer; Source and drain electrodes are fabricated on the two-dimensional semiconductor layer.
[0015] The design and fabrication method of the inductive-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating gate ferroelectric field-effect transistor, wherein the gate electrode and the source / drain electrode are both fabricated using electron beam lithography and vapor deposition techniques.
[0016] Beneficial Effects: This invention, through a van der Waals heterostructure floating-gate ferroelectric field-effect transistor, achieves synergistic modulation of ferroelectric, dielectric, and semiconductor properties at the atomic scale, providing a novel technical path for constructing a biomimetic vision system with high sensitivity, low power consumption, and real-time processing capabilities. This innovation not only solves the material compatibility and process integration challenges faced by traditional solutions, but more importantly, through an optoelectronic-ferroelectric multi-field coupling mechanism, it organically integrates bidirectional optical signal sensing, storage, and computation functions in a single device. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the integrated inductor-memory-computer device based on a two-dimensional van der Waals heterostructure floating gate ferroelectric field-effect transistor in an embodiment of the present invention.
[0018] Figure 2 This is a schematic diagram of the device array structure in an embodiment of the present invention.
[0019] Explanation of reference numerals in the attached figures: 1. Source / drain electrodes; 2. Two-dimensional semiconductor layer; 3. Tunneling layer; 4. Ferroelectric layer; 5. Barrier layer; 6. Gate electrode; 10. Central components; 20. Surrounding components. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0021] This invention provides some embodiments of an integrated inductor-memory-computer device based on a floating-gate ferroelectric field-effect transistor with a two-dimensional van der Waals heterostructure.
[0022] Traditional visual sensors face challenges such as insufficient transmission bandwidth, high power consumption, and low process compatibility, while novel two-dimensional materials exhibit better process adaptability and milder processing conditions. Breakthrough developments in two-dimensional material systems offer new insights into solving these long-standing technical challenges. Significant progress has been made in charge transport performance of novel semiconductor materials, with carrier mobility reaching remarkably high levels. Regarding ferroelectric property modulation, the subthreshold swing due to the negative capacitance effect is less than 60 mV / dec, significantly reducing polarization switching energy consumption and demonstrating extremely high energy efficiency. Of particular note is the superior photoelectric conversion capability exhibited by optoelectronic devices based on van der Waals heterostructures, providing an ideal platform for novel sensor-memory-computing integration. Although laboratory studies have confirmed the enormous potential of these materials, a significant gap remains between research results and industrial applications. Compared to mainstream commercially available products, novel sensor-memory-computing integrated devices have outstanding advantages in several core performance indicators, including a wider signal response range, faster response speed, and higher energy utilization efficiency. What is particularly valuable is that these performance improvements do not depend on manufacturing processes and can be achieved at relatively mature process nodes, which greatly enhances the practical value and industrialization prospects of the technology.
[0023] A thorough analysis of the fundamental limitations faced by existing technological approaches reveals that differences in material dimensions are one of the root causes. The interface defect density of three-dimensional ferroelectric materials generally exceeds 10-1. 12 / cm 2 Two-dimensional materials can be controlled within 10 10 / cm 2 In terms of physical limits, traditional FETs are constrained by the Boltzmann limit, making it difficult to break through the subthreshold swing of 60mV / dec, while ferroelectric modulation mechanisms offer the possibility of overcoming this limit. At the system architecture level, the inherent memory separation characteristics of the von Neumann architecture result in an energy efficiency ratio typically below 10 TOPS / W, while the integrated inductive-computing architecture promises to achieve ultra-high energy efficiency of 100+ TOPS / W. Overcoming these technological bottlenecks requires not only innovation in material systems but also fundamental changes at the levels of device physics and system architecture.
[0024] like Figure 1 As shown, the inductive-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor of the present invention includes: The gate electrode 6, the barrier layer 5, the ferroelectric layer 4, the tunneling layer 3, the two-dimensional semiconductor layer 2, and the source / drain electrode 1 are stacked sequentially. The two-dimensional semiconductor layer 2 has photoelectric response characteristics, and the tunneling layer 3 is configured to allow photogenerated carriers in the two-dimensional semiconductor layer 2 to tunnel to the ferroelectric layer 4. When the polarization direction of the ferroelectric layer 4 is towards the two-dimensional semiconductor layer 2, the ferroelectric layer 4 has a negative photoconductivity effect; when the polarization direction of the ferroelectric layer 4 is away from the two-dimensional semiconductor layer 2, the ferroelectric layer 4 has a positive photoconductivity effect.
[0025] Specifically, the device has a gate electrode 6 and source / drain electrodes 1, located on opposite sides of the device. The source / drain electrodes 1 include a source electrode and a drain electrode, both located on the same side of the device. A barrier layer 5 is configured to block charge carriers from entering the gate electrode 6. The barrier layer 5 serves as a gate dielectric layer, suppressing leakage current from the gate electrode 6. A ferroelectric layer 4 is configured to change its conductivity under illumination. The ferroelectric layer 4 has a polarization direction, which can be directed towards the two-dimensional semiconductor layer 2 or the tunneling layer 3, or towards the barrier layer 5. When the polarization direction of the ferroelectric layer 4 is directed towards the two-dimensional semiconductor layer 2 or the tunneling layer 3, the ferroelectric layer 4 exhibits a negative photoconductivity effect; under illumination, its conductivity decreases, and the conductivity is non-volatile. When the polarization direction of the ferroelectric layer 4 is directed towards the barrier layer 5, the ferroelectric layer 4 exhibits a positive photoconductivity effect; under illumination, its conductivity increases, and the conductivity is non-volatile. The tunneling layer 3 is configured to allow photogenerated carriers in the two-dimensional semiconductor layer 2 to tunnel to the ferroelectric layer 4. The two-dimensional semiconductor exhibits photoelectric response characteristics, enabling the sensing of optical signals. Under illumination, the two-dimensional semiconductor layer 2 generates carriers, which pass through the tunneling layer 3 to reach the ferroelectric layer 4, thus achieving the sensing and storage of optical signals. The two-dimensional semiconductor layer 2 / tunneling layer 3 / ferroelectric layer 4 / barrier layer 5 form a two-dimensional van der Waals heterostructure. Through atomically precise material stacking, photoelectric-ferroelectric multi-field synergistic control is achieved, enabling the fabrication of a biomimetic neuromorphic visual chip.
[0026] When the polarization direction of the ferroelectric layer 4 faces the two-dimensional semiconductor layer 2, the ferroelectric layer 4 exhibits a negative photoconductivity effect. Under illumination, the two-dimensional semiconductor layer 2 generates photogenerated carriers, which tunnel into the ferroelectric layer 4. Because the conductivity of the ferroelectric layer 4 decreases under illumination, the current between the source and drain electrodes decreases. When the polarization direction of the ferroelectric layer 4 faces away from the two-dimensional semiconductor layer 2, the ferroelectric layer 4 exhibits a positive photoconductivity effect. Under illumination, the two-dimensional semiconductor layer 2 generates photogenerated carriers, which tunnel into the ferroelectric layer 4. Because the conductivity of the ferroelectric layer 4 increases under illumination, the current between the source and drain electrodes increases.
[0027] Adjusting the voltage at gate electrode 6 can also change the resistance between the source and drain electrodes. Under a positive gate voltage, the device resistance changes from 10... 10 Ω decreased to 10 5 The resistance is Ω, and the change in resistance is non-volatile. Under negative gate voltage, the device resistance is 10 Ω.10 If Ω, then the switching ratio is 10. 5 Furthermore, the device's subthreshold swing can be as low as 60 mV / dec. The illumination input and the electrical input of the gate electrode 6 can be synergistically controlled.
[0028] In a preferred embodiment of the present invention, the integrated sensing, storage, and computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor has a storage time of more than 10 seconds for optical signals. 4 s.
[0029] Specifically, the device stores optical signals for more than 10 seconds. 4 s, thus possessing better sensing and storage performance.
[0030] In a preferred embodiment of the present invention, the two-dimensional semiconductor layer 2 has visible light response characteristics and / or ultraviolet light response characteristics.
[0031] Specifically, the two-dimensional semiconductor layer 2 can be responsive to visible light or to ultraviolet light. The wavelength of visible light is typically 400 nm to 700 nm, while the wavelength of ultraviolet light is typically less than 400 nm.
[0032] In a preferred embodiment of the present invention, the two-dimensional semiconductor layer is a two-dimensional transition metal chalcogenide layer, wherein the two-dimensional transition metal chalcogenide is selected from at least one of MoS2, MoSe2, and WSe2.
[0033] Specifically, the two-dimensional semiconductor material of the two-dimensional semiconductor layer 2 can be a two-dimensional transition metal chalcogenide layer, such as MoS2, MoSe2, or WSe2. Other two-dimensional semiconductor materials can also be used for the two-dimensional semiconductor layer 2.
[0034] In a preferred implementation of this invention, such as Figure 1 As shown, the thickness of the two-dimensional semiconductor layer 2 is 5~10nm.
[0035] Specifically, the thickness of the two-dimensional semiconductor layer 2 is 5~10nm, and the thickness of the two-dimensional semiconductor layer 2 can be configured as needed.
[0036] In a preferred implementation of this invention, such as Figure 1 As shown, the thickness of the barrier layer 5 is greater than the thickness of the tunneling layer 3.
[0037] Specifically, the thickness of the barrier layer 5 is greater than the thickness of the tunneling layer 3, so that charge carriers can easily tunnel through the tunneling layer 3, but not easily through the barrier layer 5.
[0038] In a preferred implementation of this invention, such as Figure 1 As shown, the thickness of the barrier layer 5 is 15~35nm, and the thickness of the tunneling layer 3 is 5~10nm.
[0039] Specifically, the thickness of the barrier layer 5 can be 15~35nm, and the thickness of the tunneling layer 3 can be 5~10nm. The thicknesses of the barrier layer 5 and the tunneling layer 3 can be configured as needed.
[0040] In a preferred embodiment of the present invention, the barrier layer 5 includes at least one of an h-BN layer or a SiO2 layer.
[0041] Specifically, the barrier material of the barrier layer 5 can be h-BN or SiO2. Utilizing its atomically flat surface and ultra-high insulation, it effectively suppresses leakage current in the gate electrode 6. Other barrier materials can also be used for the barrier layer 5. The h-BN layer possesses high insulation and atomically flat characteristics, ensuring efficient electric field transmission while suppressing leakage current in the gate electrode 6.
[0042] In a preferred embodiment of the present invention, the tunneling layer 3 is an h-BN layer.
[0043] Specifically, the tunneling material of tunnel layer 3 can be h-BN. Other tunneling materials can also be used for tunnel layer 3.
[0044] In a preferred implementation of this invention, such as Figure 1 As shown, the source / drain electrode 1 includes a source electrode and a drain electrode, both of which are Au / Cr electrodes.
[0045] Specifically, the source and drain electrodes can be made of the same material, for example, an Au / Cr electrode. The Au / Cr electrode consists of sequentially stacked Cr and Au layers, where the Cr layer thickness can be 5–15 nm and the Au layer thickness can be 30–70 nm. The thicknesses of the Cr and Au layers can be configured as needed.
[0046] In a preferred embodiment of the present invention, the gate electrode 6 is an Au / Cr electrode or a Si electrode.
[0047] Specifically, the gate electrode 6 can be an Au / Cr electrode or a Si electrode.
[0048] In a preferred embodiment of the present invention, the ferroelectric layer 4 is a two-dimensional ferroelectric material layer.
[0049] Specifically, the ferroelectric layer 4 is a two-dimensional ferroelectric material layer. The two-dimensional ferroelectric material layer and the two-dimensional semiconductor layer 2 form a coupling effect to achieve non-volatile storage and photoelectric synergistic control. Moreover, it can be excited by light of various wavelengths.
[0050] In a preferred embodiment of the present invention, the two-dimensional ferroelectric material layer is an α-In2Se3 layer or a two-dimensional CuInP2S6 layer.
[0051] Specifically, the two-dimensional ferroelectric material of the two-dimensional ferroelectric material layer can be α-In₂Se₃ or CuInP₂S₆. Other two-dimensional ferroelectric materials can also be used for the two-dimensional ferroelectric material layer.
[0052] In a preferred implementation of this invention, such as Figure 1 As shown, the thickness of the two-dimensional ferroelectric material layer is 10~50nm.
[0053] Specifically, the thickness of the two-dimensional ferroelectric material layer is 10~50nm. The thickness of the two-dimensional ferroelectric material layer can be configured as needed.
[0054] This invention utilizes a van der Waals heterostructure floating-gate ferroelectric field-effect transistor to achieve synergistic modulation of ferroelectric, dielectric, and semiconductor properties at the atomic scale, providing a novel technological path for constructing biomimetic vision systems with high sensitivity, low power consumption, and real-time processing capabilities. This innovation not only solves the material compatibility and process integration challenges faced by traditional solutions, but more importantly, through a photoelectric-ferroelectric multi-field coupling mechanism, it organically integrates bidirectional optical signal sensing, storage, and computation functions in a single device, opening up new possibilities for the development of future intelligent sensing systems. The innovative mechanism of controlling the polarization direction of the photoresponse polarity provides a new path for constructing intelligent vision systems with biological retinal characteristics. Its integrated sensing, storage, and computation characteristics will significantly reduce data transmission requirements and system power consumption, laying the foundation for the development of next-generation edge intelligent devices.
[0055] Based on the inductive-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor described in any of the above embodiments, the present invention also provides a preferred embodiment of a biomimetic visual neuromorphic chip.
[0056] like Figure 2 As shown, the biomimetic visual neuromorphic chip of this invention includes: at least one device array, the device array including a central device 10 and a plurality of peripheral devices 20, the plurality of peripheral devices 20 surrounding the central device 10; both the central device 10 and the peripheral devices 20 are inductive-memory-computing integrated devices based on a two-dimensional van der Waals heterostructure floating gate ferroelectric field-effect transistor as described in any of the above embodiments; the polarization direction of the ferroelectric layer of the central device 10 is opposite to the polarization direction of the ferroelectric layer of the peripheral devices 20; the drain electrode in the source-drain electrode of the central device 10 and the drain electrode in the source-drain electrode of each of the peripheral devices 20 are connected in parallel.
[0057] Specifically, multiple devices form a device array, and at least one device array exists within the chip. The devices in the device array are divided into a central device 10 and surrounding devices 20. There are multiple surrounding devices 20, which surround the central device 10. The drain electrodes of each device in the device array are connected in parallel. The source electrodes of each device in the device array are independent of each other, enabling independent control.
[0058] Using light stimulation as input, the driving circuit forms a sample-and-hold branch and a direct-through branch. The output terminals of the sample-and-hold branch and the direct-through branch are connected to the inverting and non-inverting input ports of a differential amplifier, respectively, resulting in an output voltage spike. The sample-and-hold branch is connected to a device array, which can simulate the ON / OFF receptive field mechanism of biological vision. The sample-and-hold branch utilizes the ultra-low subthreshold characteristic of this device to achieve high-speed switching, driven by high-frequency pulses ranging from -1 V to 0.5 V.
[0059] In a preferred embodiment of the present invention, the polarization direction of the ferroelectric layer of the central device 10 is toward the two-dimensional semiconductor layer, and the polarization direction of the ferroelectric layer of the surrounding device 20 is away from the two-dimensional semiconductor layer.
[0060] Specifically, the ferroelectric layer of the central device 10 exhibits a negative photoconductivity effect, resulting in a decrease in the current between the source and drain electrodes of the central device 10 under illumination. The ferroelectric layer of the surrounding device 20 exhibits a positive photoconductivity effect, resulting in an increase in the current between the source and drain electrodes of the surrounding device 20 under illumination.
[0061] Based on the floating-gate ferroelectric field-effect transistor with a two-dimensional van der Waals heterostructure described in any of the above embodiments, the present invention also provides a preferred embodiment of the design and fabrication method of the floating-gate ferroelectric field-effect transistor with a two-dimensional van der Waals heterostructure.
[0062] The design and preparation method of this invention includes the following steps: Step S100: Prepare the gate electrode; Step S200: After preparing the barrier layer, peel it off and transfer it to the gate electrode; Step S300: After preparing the ferroelectric layer, peel it off and transfer it to the barrier layer; Step S400: After preparing the tunneling layer, peel it off and transfer it to the ferroelectric layer; Step S500: Prepare a two-dimensional semiconductor layer, peel it off and transfer it to the tunneling layer; Step S600: Prepare source and drain electrodes on the two-dimensional semiconductor layer.
[0063] Specifically, the gate electrode is first fabricated, followed by the sequential transfer and stacking of the barrier layer, ferroelectric layer, tunneling layer, and two-dimensional semiconductor layer onto the gate electrode. Finally, the source and drain electrodes are fabricated on the two-dimensional semiconductor layer. The two-dimensional semiconductor layer, tunneling layer, ferroelectric layer, and barrier layer are all fabricated using chemical vapor deposition (CVD) or mechanical lift-off methods.
[0064] Both the gate electrode and the source / drain electrode are fabricated using electron beam lithography and evaporation techniques. Specifically, in fabricating the gate electrode, photoresist is spin-coated onto a substrate, and an electrode pattern is formed using electron beam exposure and development. Then, Cr and Au metals are deposited using electron beam evaporation to obtain the gate electrode. In fabricating the source / drain electrode, photoresist is spin-coated onto a two-dimensional semiconductor layer, and an electrode pattern is formed using electron beam exposure and development. Then, Cr and Au metals are deposited using electron beam evaporation to obtain the source / drain electrode.
[0065] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.
Claims
1. A sensor-memory-computing integrated device based on a floating-gate ferroelectric field-effect transistor with a two-dimensional van der Waals heterostructure, characterized in that, include: The gate electrode, barrier layer, ferroelectric layer, tunneling layer, two-dimensional semiconductor layer, and source / drain electrodes are stacked sequentially. The two-dimensional semiconductor layer has photoelectric response characteristics, and the tunneling layer is configured to allow photogenerated carriers in the two-dimensional semiconductor layer to tunnel to the ferroelectric layer. When the polarization direction of the ferroelectric layer is toward the two-dimensional semiconductor layer, the ferroelectric layer has a negative photoconductivity effect; when the polarization direction of the ferroelectric layer is away from the two-dimensional semiconductor layer, the ferroelectric layer has a positive photoconductivity effect.
2. The integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 1, characterized in that, The aforementioned floating-gate ferroelectric field-effect transistor based on a two-dimensional van der Waals heterostructure has a storage time of more than 10 seconds for optical signals. 4 s; The two-dimensional semiconductor layer has visible light response characteristics and / or ultraviolet light response characteristics.
3. The integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 2, characterized in that, The two-dimensional semiconductor layer is a two-dimensional transition metal chalcogenide layer, and the two-dimensional transition metal chalcogenide is selected from at least one of MoS2, MoSe2, and WSe2. The thickness of the two-dimensional semiconductor layer is 5~10nm.
4. The integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 1, characterized in that, The thickness of the barrier layer is greater than the thickness of the tunneling layer.
5. The integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 4, characterized in that, The thickness of the barrier layer is 15~35nm, and the thickness of the tunneling layer is 5~10nm; The barrier layer includes at least one of an h-BN layer or a SiO2 layer, and the tunneling layer is an h-BN layer. The source and drain electrodes include a source electrode and a drain electrode, both of which are Au / Cr electrodes; the gate electrode is an Au / Cr electrode or a Si electrode.
6. The integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 1, characterized in that, The ferroelectric layer is a two-dimensional ferroelectric material layer.
7. The integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 6, characterized in that, The two-dimensional ferroelectric material layer is an α-In2Se3 layer or a two-dimensional CuInP2S6 layer, and the thickness of the two-dimensional ferroelectric material layer is 10~50nm.
8. A biomimetic visual neuromorphic chip, characterized in that, include: At least one device array, the device array comprising a central device and a plurality of surrounding devices, the plurality of surrounding devices surrounding the central device; Both the central device and the surrounding devices adopt the inductive-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating gate ferroelectric field-effect transistor as described in any one of claims 1 to 7. The polarization direction of the ferroelectric layer of the central device is opposite to that of the ferroelectric layer of the surrounding device; The drain electrode in the source-drain electrode of the central device and the drain electrode in the source-drain electrode of each of the surrounding devices are connected in parallel.
9. A method for designing and fabricating an integrated inductor-memory-computing device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor as described in any one of claims 1 to 7, characterized in that, Including the following steps: Fabrication of the gate electrode; After the barrier layer is prepared, it is peeled off and transferred to the gate electrode; After the ferroelectric layer is prepared, it is peeled off and transferred to the barrier layer; After the tunneling layer is prepared, it is peeled off and transferred to the ferroelectric layer; A two-dimensional semiconductor layer is prepared, stripped off, and transferred to the tunneling layer; Source and drain electrodes are fabricated on the two-dimensional semiconductor layer.
10. The design and fabrication method of the inductor-memory-computing integrated device based on a two-dimensional van der Waals heterostructure floating-gate ferroelectric field-effect transistor according to claim 9, characterized in that, Both the gate electrode and the source / drain electrode are fabricated using electron beam lithography and vapor deposition techniques.