3D structure core particle test layout design method supporting cross-level cascade test and single core particle self-test

Abstract

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuit testing, and more particularly relates to a 3D structure chiplet test layout design method supporting cross-level connection testing and single chiplet self-testing. BACKGROUND

[0002] With the rapid development of ultra-large scale integrated circuits towards high density, high bandwidth and low delay, 3D structure chiplets (3D Chiplet) have become a core technical solution to break through the physical limit of 2D planar integration due to the architectural advantages of "multi-layer chiplet vertical stacking + through silicon via interconnection". By stacking chiplets with different functions (such as computing chiplets, storage chiplets, interface chiplets) in the vertical direction, the chip integration can be significantly improved, the signal transmission path can be shortened, and the system power consumption can be reduced. 3D structure chiplets have been widely used in high-end server CPUs, artificial intelligence chips, high-performance storage and other fields.

[0003] However, the stacking characteristics of 3D structure chiplets also make their testing much more difficult than 2D structures, and the testing technology has become a key bottleneck restricting the mass production and application of 3D chiplets. The current core requirements for testing 3D structure chiplets include verifying the signal connectivity of chiplets within a layer, verifying the transmission integrity of vertical interconnections between layers, accurately locating faults, and controlling the occupation of testing resources (to avoid excessive use of TSVs leading to a sharp increase in packaging costs). However, existing technologies have the following significant defects when addressing these requirements: 1. High occupation of interlayer testing resources, leading to a sharp increase in packaging costs: Existing 3D chiplet testing solutions mostly follow the idea of "direct stacking of 2D test layout": a separate test PIN and vertical test channel (TSV) are designed for each layer of chiplets, and the intra-layer test layout mostly adopts a rectangular arrangement (1 test PIN covering 4 signal PINs). This design leads to: A sharp increase in the number of vertical test channels (TSVs): each layer needs to be configured with TSVs matching the number of test PINs, and when there are 3 or more layers of stacking, the total number of TSVs can be 2-3 times that of 2D structures, not only occupying a large amount of packaging space (TSV aperture is usually 5-10 μm, and dense arrangement can easily lead to chiplet cracking risk), but also increasing 3D packaging costs by more than 30%; Low intra-layer test efficiency: the coverage efficiency of the rectangular intra-layer test PIN is low, and the number of test PINs needs to be increased to achieve full signal coverage, further exacerbating the redundancy of interlayer test resources.

[0004] 2. Lack of independent control by layers, leading to poor test accuracy due to interlayer signal crosstalk: Current 3D chiplet test circuits mostly use "overall enable" logic: all layers of test PINs and vertical channels are activated simultaneously during testing, and no independent control mechanism is designed for different levels. This design has a serious problem of interlayer signal crosstalk: When testing the signal of a certain layer, the test pins of adjacent layers will receive and feed back interference signals, causing the output signal to be distorted, making it impossible to accurately determine whether the fault is located in the target layer. During cross-layer testing, vertical channels of non-target layers can form "parasitic paths," causing test signals to be diverted and making it difficult to verify the true transmission performance of inter-layer interconnects (such as TSVs), with a false positive rate of over 15%.

[0005] 3. Inability to perform self-testing on a single core chip, resulting in difficulty in fault location and low testing efficiency: Existing 3D core testing solutions rely on a "multi-core stacking followed by overall testing" process: multiple cores must be vertically stacked and bonded before signals can be input through the top / bottom layer test interfaces to verify overall connectivity. This process has two major problems: Single-core faults cannot be detected in advance: If a single core itself has an intralayer signal fault (such as an open circuit at the factory), when the overall test fails after stacking, it is impossible to distinguish whether the fault originates from "inside the single core" or "interlayer damage during the stacking process". It is necessary to disassemble and re-test, which extends the test cycle by more than 50%. Redundancy in multi-layer testing steps: When testing chip paths spanning 3 or more layers, each complete path must be tested individually. There is no efficient segmented testing logic, and the testing time increases linearly with the number of stacked layers.

[0006] 4. Insufficient test coverage, with signal blind spots existing: Some solutions aim to reduce resource consumption by simplifying the intra-layer test layout (e.g., reducing the number of test pins) or omitting some inter-layer test channels. Incomplete signal coverage within the layer: The simplified test layout cannot cover the edge signal pins, causing some signals to remain in an "untested state" for a long time, which can easily lead to "hidden faults" (such as excessive signal delay) during mass production. Interlayer interconnect test blind zone: After omitting some TSV test channels, it is impossible to verify the integrity of all vertical interconnects. After 3D stacking, "local interlayer transmission interruption" may occur, affecting the overall function of the chip.

[0007] In summary, existing 3D chip testing technologies suffer from multiple bottlenecks in terms of resource consumption, test accuracy, efficiency, and coverage, making it difficult to meet the mass production testing requirements of high-density 3D stacked integrated circuits. Therefore, developing a test layout design method that adapts to the characteristics of 3D stacking, balances test efficiency and resource optimization, and supports single-chip self-testing and cross-layer cascade testing has become a key issue that urgently needs to be addressed in the current 3D chip technology field. Summary of the Invention

[0008] The application aims to solve the problems in the prior art and provides a 3D structure die test layout design method supporting cross-level chain testing and single-die self testing.

[0009] To achieve the above-mentioned purpose, the application is implemented by adopting the following technical scheme: a 3D structure die test layout design method supporting cross-level chain testing and single-die self testing, the method comprising the following steps: a. designing a test point layout of a 3D stacked die, adopting a hexagonal arrangement mode for each layer of the die, connecting 1 layer-in test PIN with 6 signal PINs in the same layer, and setting a vertical test channel to connect the layer-in test PIN of each layer with the corresponding test PIN of the adjacent layer through a vertical interconnection structure; b. configuring an independent layer-in test circuit for each layer of the die, and connecting the layer-in test circuit with the vertical test channel through a level selection switch; c. designing a test process, based on the test circuit, first performing single-die self testing, then performing cross-level chain testing, and judging the layer-in and interlayer signal connectivity through the test results.

[0010] Preferably, the vertical interconnection structure in the step a is a through silicon via, each layer-in test PIN is connected with the layer-in test PIN at the corresponding position of the upper layer and the lower layer through one TSV, and the connection point of the TSV with the layer-in test PIN is located at the center position of the hexagonal layout.

[0011] Preferably, the layer-in test PIN of each layer of the die in the step a is arranged equidistantly with the 6 signal PINs in the same layer, and the layer-in test PINs of the adjacent layers are projected to coincide in the vertical direction.

[0012] Preferably, the layer-in test circuit in the step b comprises: a layer-in control module: configuring an independent control signal for each layer-in test PIN, for controlling the opening or closing of the test PIN during the layer-in testing; a level selection module: configuring a level selection signal for the vertical test channel, for controlling the conduction or disconnection between the test PINs of the adjacent layers, to selectively activate the cross-layer test path.

[0013] Preferably, the single-die self testing comprises: single-layer-in self testing: opening one layer-in test PIN of a certain layer of the target die through the layer-in control module, closing the other test PINs in the same layer and all the vertical test channels, inputting a test signal and detecting the output, and judging the layer-in signal connectivity; single-die cross-layer self testing: conducting the vertical test channels of the adjacent two layers in the target die through the level selection module, closing the test PINs of the other layers at the same time, inputting a test signal and detecting the cross-layer output, and judging the interlayer connectivity inside the die.

[0014] Preferably, the cross-layer test includes: Adjacent layer test: after completing the single-chip self-test, the vertical test channel of the adjacent two chips is turned on by the layer selection module, other test paths are turned off, test signals are input, and the cross-chip output is detected to determine the interlayer connectivity of the adjacent chips; Cross-layer test: the vertical test channels of multiple stacked chips are sequentially turned on by the layer selection module, the non-path test PIN is turned off, test signals are input, and the terminal output is detected to determine the signal connectivity of the cross-layer chips.

[0015] Preferably, the output signal judgment standard of the single-layer self-test and the single-chip cross-layer self-test is: if the consistency of the output signal and the preset test signal meets the threshold requirement, it is determined that the corresponding intra-layer or inter-layer signal path is normal; if the signal is missing or the deviation exceeds the threshold, it is determined that there is an open circuit or a short circuit fault.

[0016] Advantages of the present application: The present application is adapted to 3D stack test full coverage, through "intra-layer hexagonal layout + vertical test channel", solves the pain point of "interlayer signal difficult to test" in 3D structure, realizes full-scene coverage of intra-layer, inter-layer and cross-chip signal; The test efficiency and accuracy are effectively improved, the layered independent control circuit avoids cross-layer signal interference; the "segmented test method" reduces the test steps; the step-by-step execution of single-chip self-test and cross-layer test can accurately locate whether the fault is located in "a single chip" or "between chips".

[0017] Compared with the traditional 3D test scheme, the present application effectively reduces the use amount of TSV and reduces the complexity and cost of 3D packaging by sharing the intra-layer test PIN and the vertical channel. DETAILED DESCRIPTION

[0018] In order to facilitate the understanding of the present application, the present application will be described more fully below. However, the present application can be realized in many different forms and is not limited to the embodiments described in the present application. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0019] Unless otherwise defined, all technical and scientific terms used in the present application have the same meaning as understood by a person skilled in the art to which the present application belongs. The terms used in the present application are only for the purpose of describing the specific embodiments of the present application and are not intended to limit the present application. In order to facilitate the understanding of the present application, the present application will be described more fully below. However, the present application can be realized in many different forms and is not limited to the embodiments described in the present application. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0020] The embodiment is directed to the test requirements of 3D stacked core particles (i.e. formed by stacking 2 or more core particles through vertical interconnection), and designs a "in-layer + inter-layer" coordinated test point layout: The test points of each layer of core particles are arranged in a hexagonal shape (continuing the high-efficiency coverage advantage of 2D structure), one in-layer test PIN (denoted as Pn, n is the layer number) is connected with six signal PINs (S1-S6) in the same layer at equal distances, ensuring comprehensive coverage of signals in a single layer; at the same time, a through silicon via (TSV) is arranged at the center position of each in-layer test PIN as a vertical test channel, so that Pn is connected with the upper test PIN Pn+1 and the lower test PIN Pn-1 through the TSV.

[0021] The technical effect of the layout is that: 1. The in-layer hexagonal arrangement maintains the high efficiency of "one test PIN covering six signal PINs" in the 2D structure, reducing the number of in-layer test PINs; 2. The vertical test channel is designed to be co-centered with the in-layer test PIN, making the cross-layer signal transmission path the shortest and reducing signal attenuation; 3. The vertical projections of adjacent layer test PINs coincide, avoiding misalignment interference of test channels in 3D stacking.

[0022] The embodiment also designs a layered independent control test circuit: To realize the compatibility of "in-layer independent test" and "cross-layer accurate test" in 3D structure, the embodiment designs a layered independent control test circuit, mainly including: In-layer control module: an independent control signal (such as Cntl_Pn_x, where n is the layer number and x is the test PIN number of the layer) is configured for each in-layer test PIN of each layer, which controls the opening / closing of the test PIN through high / low level. This module ensures that when testing signals in a layer, the target test PIN can be activated alone, avoiding signal interference from other test PINs in the same layer.

[0023] Layer selection module: an upward selection signal (Up_n, controlling the conduction of the nth layer test PIN and the (n+1)th layer) and a downward selection signal (Dn_n, controlling the conduction of the nth layer test PIN and the (n-1)th layer) are configured for each vertical test channel, and the "step-by-step enable" logic is used to realize accurate control of the cross-layer path. For example, when testing the connectivity between the 2nd layer and the 3rd layer, only the Up_2 and Dn_3 signals are activated, and other layer selection signals remain closed, preventing signal crosstalk to the 1st layer or the 4th layer.

[0024] The effect of the circuit design is that through the double logic of "in-layer control + hierarchical selection", the test independence in a single core particle is retained, and flexible switching of the cross-layer test path is realized, and the problem of "interlayer signal interference leading to inaccurate testing" in traditional 3D testing is solved.

[0025] Based on the above layout and circuit, the 3D test process of the embodiment is executed in two steps, and the test integrity and efficiency are considered: Single core particle self-test, the purpose is to verify the in-layer and interlayer signal connectivity in a single 3D core particle, including: 1. Single in-layer self-test: taking the second layer as an example, activate P2_1 through the in-layer control module, close other test PINs (P2_2-P2_m) and all Up / Dn signals (cut off the vertical channel) of the layer; input test signal to P2_1, detect the output of S1-S6. If the output is normal, it is determined that the second layer signal path is fault-free.

[0026] 2. Single core particle cross-layer self-test: when verifying the vertical connectivity between the second layer and the third layer in the same core particle, activate the in-layer control signals of P2_1 and P3_1, and activate Up_2 and Dn_3 at the same time (turn on the TSV between the two layers); input test signal to P2_1, detect the output of P3_1. If the output is normal, it is determined that the vertical channel between layers 2 and 3 in the core particle is fault-free.

[0027] Cross-layer connection test: after single core particle self-test, verify the signal connectivity between multiple stacked core particles, including: 1. Adjacent layer connection test: when testing the connection between core particle A (the top layer is the second layer) and core particle B (the bottom layer is the third layer), activate P2_1 of A and P3_1 of B, and turn on Up_2 of A and Dn_3 of B (through package interconnection); input signal to P2_1 of A, detect the output of P3_1 of B, and judge the interlayer connectivity of the two core particles.

[0028] 2. Cross multi-layer connection test: when testing the cross three-layer path of core particle A-core particle B-core particle C, use "segmented test method": first verify the connectivity of A and B, then verify the connectivity of B and C, if both segments are normal, it is directly determined that the A-B-C path is normal, and there is no need to repeat the test of the complete path.

[0029] Compared with the prior art, the present application is suitable for 3D stacking test full coverage, through "in-layer hexagonal layout + vertical test channel", solves the pain point of "interlayer signal difficult to test" in 3D structure, realizes the full-scene coverage of in-layer, interlayer and cross-core particle signals; The test efficiency and accuracy are effectively improved, the layered independent control circuit avoids cross-layer signal interference, the segmented test method reduces the redundancy of test steps, and the step-by-step execution of single-core self-test and cross-layer connection test can accurately locate whether the fault is located in the single core or between the cores.

[0030] Compared with the traditional 3D test scheme, the method effectively reduces the TSV usage, and reduces the complexity and cost of 3D packaging by sharing the in-layer test PIN and the vertical channel.

[0031] In summary, the application provides a complete test solution for 3D structure cores, taking into account test coverage, efficiency and cost, and is suitable for mass production test scenarios of high-density 3D stacked integrated circuits.

[0032] It should be understood that the above detailed description of the technical solutions of the application by means of the preferred embodiments is illustrative rather than limiting. Those skilled in the art can modify the technical solutions recorded in each embodiment or replace some of the technical features equivalently on the basis of the description of the application; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solutions of each embodiment of the application.

Claims

1. A method for 3D structure die test layout design supporting cross-hierarchy chain test and single-die self-test, characterized in that, The method comprises the following steps: a. Designing a test point layout of a 3D stacked core particle, adopting a hexagonal arrangement for each layer of core particles, so that one layer-in test PIN is connected to six signal PINs in the same layer; and setting a vertical test channel, so that the layer-in test PIN of each layer is connected to the corresponding test PIN of the adjacent layer through a vertical interconnection structure; b. Configuring an independent layer-in test circuit for each layer of core particles, and connecting the layer-in test circuit and the vertical test channel through a hierarchical selection switch; c. Designing a test process, based on the test circuit, first performing single-core particle self-test, then performing cross-layer hierarchical test, and judging the layer-in and interlayer signal connectivity through the test results.

2. The 3D structure die test floor planning design method supporting cross- hierarchy chained test and single-die self-test according to claim 1, wherein, The vertical interconnection structure in step a is a through-silicon via, each layer-in test PIN is connected to the layer-in test PIN at the corresponding position in the upper and lower layers through one TSV, and the connection point of the TSV and the layer-in test PIN is located at the center position of the hexagonal layout.

3. The 3D structure die test layout design method supporting cross-hierarchy chained test and single-die self-test according to claim 1, wherein, The layer-in test PINs of each layer of core particles in step a are arranged equidistantly with the six signal PINs in the same layer, and the layer-in test PINs of adjacent layers are projected to coincide in the vertical direction.

4. The 3D structure die test layout design method supporting cross-hierarchy chained test and single-die self-test according to claim 1, wherein, The test circuit in step b is independently controlled in layers and comprises: a layer-in control module: an independent control signal is configured for each layer-in test PIN to control the opening or closing of the test PIN during layer-in test; a hierarchical selection module: a hierarchical selection signal is configured for the vertical test channel to control the conduction or disconnection between the test PINs of adjacent layers, so as to selectively activate the cross-layer test path.

5. The 3D structure die test layout design method supporting cross-hierarchy chained test and single-die self-test according to claim 1, wherein, The single-core particle self-test comprises: single-layer-in self-test: turn on a layer-in test PIN of a target core particle in a certain layer through the layer-in control module, turn off other test PINs in the same layer and all vertical test channels, input test signals and detect the output, and judge the layer-in signal connectivity; single-core particle cross-layer self-test: turn on the vertical test channels of adjacent two layers in the target core particle through the hierarchical selection module, turn off the test PINs of other layers, input test signals and detect the cross-layer output, and judge the interlayer connectivity of the core particle.

6. The method of claim 1, wherein the method of designing a 3D structure die test layout to support cross-hierarchy chained testing and single-die self-testing, further comprises: The cross-layer hierarchical test comprises: adjacent layer hierarchical test: after completing the single-core particle self-test, turn on the vertical test channels of adjacent two core particles through the hierarchical selection module, turn off other test paths, input test signals and detect the cross-core particle output, and judge the interlayer connectivity of adjacent core particles; cross-multi-layer hierarchical test: sequentially turn on the vertical test channels of a plurality of stacked core particles through the hierarchical selection module, turn off the non-path test PINs, input test signals and detect the terminal output, and judge the signal connectivity of the cross-multi-layer core particles.

7. The 3D structure die test layout design method supporting cross-hierarchy chained test and single-die self-test according to claim 5, wherein, The output signal judgment criteria of the single-layer-in self-test and the single-core particle cross-layer self-test are: if the consistency of the output signal with the preset test signal meets the threshold requirement, it is determined that the corresponding layer-in or interlayer signal path is normal; if the signal is missing or the deviation exceeds the threshold, it is determined that there is an open circuit or a short circuit fault.