High-integration-level high-signal-to-noise-ratio spaceborne fluorescence hyper-spectral detector electronics system

Abstract

The invention relates to a satellite-borne fluorescence hyper-spectral detector electronics system with high integration level and high signal-to-noise ratio. A signal processing module is used for controlling the working mode of a detector; receiving a second pulse signal of a satellite GPS subsystem to generate a time count of a frame synchronization signal; carrying out extremely low noise quantization on an analog signal transmitted by the focal plane driving unit; the image data and the auxiliary data are coded and integrated and then sent to a satellite data transmission subsystem; a global clock and a global reset signal are generated and sent to the sequential control unit; the time sequence control unit generates a frame synchronization signal and a clock synchronization signal, and generates a driving time sequence signal of a CCD in the focal plane driving unit; the focal plane driving unit generates various bias voltages required by the work of the CCD; receiving a driving time sequence signal to generate various high-voltage driving signals required by the work of a CCD (Charge Coupled Device); and the CCD output analog signal is output to the signal processing unit after being subjected to power amplification and impedance matching. The signal-to-noise ratio of the system is improved, and the size, weight and power consumption of imaging electronics of the detector are reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of aerospace optical remote sensing, and relates to a high-integration high-signal-to-noise-ratio electronic system of a spaceborne fluorescence hyperspectral detector. BACKGROUND

[0002] Vegetation fluorescence detection is to obtain spatially continuous distribution of vegetation fluorescence signals by using a hyperspectral resolution detection mode under weak reflection signal conditions, analyze photosynthetic capacity of land vegetation, and further answer and explain carbon absorption capacity of forests and growth conditions of crops. The task of the spaceborne hyperspectral detector is to obtain solar-induced vegetation fluorescence remote sensing data, so as to accurately draw spatial and temporal distribution rules of vegetation fluorescence in a region of interest, and meet the needs of global carbon source and carbon sink quantitative monitoring and forest vegetation productivity evaluation.

[0003] Because vegetation fluorescence is a low-brightness and weak-signal target, the requirement of system signal-to-noise ratio for quantitative spectral detection of the target is very high. System noise mainly consists of photon noise, dark current noise, readout noise, analog circuit noise and quantization noise. For noise suppression of a low-brightness and weak-signal detection system, photon noise is not a major factor, and dark current noise and readout noise are determined by the process of the CCD detector itself, so the suppression of analog circuit noise and quantization noise of the imaging circuit is a key link.

[0004] In addition, with the development trend of high-integration and miniaturization of spaceborne detection payloads, the requirement for reduction of the number of devices, volume and power consumption control of the electronic system is higher, so it is necessary to integrate and optimize the functional modules of the electronic system. SUMMARY

[0005] The application solves the technical problem of overcoming the shortcomings of the prior art, and proposes a high-integration high-signal-to-noise-ratio electronic system of a spaceborne fluorescence hyperspectral detector, which meets the needs of low-brightness and weak-signal vegetation fluorescence target detection, reduces circuit noise, improves system signal-to-noise ratio, and reduces the volume, weight and power consumption of the detector imaging electronics.

[0006] The solution to the technical problem of the application is: a high-integration high-signal-to-noise-ratio electronic system of a spaceborne fluorescence hyperspectral detector, comprising a signal processing unit, a timing control unit and a focal plane driving unit, wherein:

[0007] The signal processing unit filters and voltage converts the input secondary power supply; receives bus instructions and broadcast data of the satellite service, and completes control of the working mode of the detector; collects information reflecting the working state of the detector, and uploads it to the satellite service through the bus interface; receives the second pulse signal sent by the satellite GPS subsystem timing unit, generates the time count of the frame synchronization signal, quantizes the analog signal from the focal plane driving unit with extremely low noise, encodes and integrates the image data and auxiliary data, and sends them to the satellite data transmission subsystem; and generates a global clock and a global reset signal and sends them to the timing control unit;

[0008] The timing control unit filters and voltage converts the input secondary power supply; generates the secondary power supply required by the focal plane driving unit; receives the global clock and global reset signal sent by the signal processing unit to generate the frame synchronization signal and clock synchronization signal, so that the electronic system works under the same source clock; generates the driving timing signal required by the CCD in the focal plane driving unit; and sends the telemetry quantity reflecting the state of the timing control unit to the signal processing unit;

[0009] The focal plane driving unit filters and voltage converts the input secondary power supply, generates various bias voltages required for the working of the CCD, receives the driving timing signal of the timing control unit, generates various high-voltage driving signals required for the working of the CCD, and outputs the CCD output analog signal to the signal processing unit after power amplification and impedance matching.

[0010] Further, the signal processing unit comprises a main board and a backup board; the focal plane driving unit uses a secondary operational amplifier to output the CCD analog signal after power amplification and impedance matching to the signal processing unit main board and backup board respectively.

[0011] Further, the signal processing unit comprises a first power supply filtering and voltage conversion module, a low-noise analog signal active filtering module, an extremely low-noise analog-to-digital conversion module, a 1553B bus communication module, a second pulse receiving module, a first FPGA module, a data storage module, a data transmission interface module, and a timing control interface module;

[0012] The front end of the filtering network of the first power supply filtering and voltage conversion module is a common-mode choke, and the rear end of the filtering network is a differential-mode choke; the input voltage is converted into the voltage value required for the working of the signal processing unit through a voltage conversion chip;

[0013] The low-noise analog signal active filtering module uses a single power supply rail-to-rail operational amplifier to perform active filtering on the CCD analog signal input by the focal plane driving unit, and matches a proper filtering network according to the output frequency of the analog signal to reduce the noise of the operational amplifier;

[0014] The extremely low-noise analog-to-digital conversion module is used to perform analog-to-digital conversion on the CCD analog signal output by the low-noise analog signal active filtering module.

[0015] 1553B bus communication module exchanges data with satellite data processing subsystem through 1553B bus, receives data type interface instruction and polling instruction, and sends packaged telemetry parameters to satellite data processing subsystem;

[0016] Second pulse receiving module is used for receiving second pulse signal sent by satellite GPS subsystem timing unit, as time counting reference of detector, and sending second pulse signal to first FPGA module;

[0017] First FPGA module generates global clock and global reset signal; receives 1553B bus instruction and data sent by satellite and returns telemetry information; receives two-way second pulse signal of second pulse receiving module, generates time count of frame synchronization signal; receives quantized digital image signal of extremely low noise analog-digital conversion module; drives extremely low noise analog-digital conversion module to work normally according to working mode requirement; analyzes and arranges whole satellite auxiliary data sent by 1553B bus communication module, and sends auxiliary data and image data to data transmission interface module;

[0018] Data storage module uses external SRAM to cache image data of first FPGA module;

[0019] Data transmission interface module outputs quantized data of extremely low noise analog-digital conversion module in the form of LVDS level, adopts cross hot backup working mode, so that signal processing unit main board or backup board has signal output when working;

[0020] Timing control interface module sends global clock and global reset signal generated by first FPGA module to timing control unit.

[0021] Further, the extremely low noise analog-digital conversion module adopts AD9814 chip, output noise is only 0.55LSBrms, quantization bit number is 14 bits, single-channel maximum sampling rate is 7Msps, internal integration sampling and holding function and correlated double sampling mode are integrated, and programmable gain and programmable bias function are provided;

[0022] In order to control quantization noise to the maximum, AD9814 chip is set in correlated double sampling working mode, and inputted direct-current-isolated analog signal is embedded into a fixed voltage of 4V, which is generated by AD9814 chip internally; in addition, source terminal series matching resistor is used at each bit of digital output end of AD9814 chip, so as to prevent current feedback error formed by digital output end data jump on analog-digital conversion internal, and ensure signal integrity of digital signal outputted to subsequent circuit after AD quantization.

[0023] Further, the 1553B bus communication module adopts a double-redundant 1553B bus structure, including two buses A and B, which are hot backups for each other.

[0024] Further, the timing control unit includes a second power filter and voltage conversion module, a second FPGA module, a timing generation module, and a signal processing unit interface module.

[0025] The front end of the filter network of the second power filter and voltage conversion module is a common-mode choke, and the rear end of the filter network is a differential-mode choke; the input voltage is converted into a voltage value required by the timing control unit to work through a voltage conversion chip;

[0026] The second FPGA module uses an anti-fuse FPGA chip to generate different CCD drive timing signals according to the requirements of the working mode, and has the function of communicating with the signal processing unit;

[0027] The timing generation module generates clock synchronization, reset synchronization, and frame synchronization signals to the second FPGA module according to the global clock and global reset signal input by the signal processing unit.

[0028] The signal processing unit interface module receives the global clock and global reset signal generated by the first FPGA module.

[0029] Further, the timing control unit further includes a buffer, which is used to solve the problem of limited I / O port driving capability of the second FPGA module, and the drive signal generated by the second FPGA module is sent to the focal plane driving unit through the buffer.

[0030] Further, the CCD drive timing signal includes a vertical transfer signal, including an integration zone vertical transfer signal and a storage zone vertical transfer signal a horizontal transfer signal, including a horizontal register transfer signal and a reset signal and a control signal, including a DG signal for dumping charge in the horizontal register zone and an IG signal for dumping charge in the imaging zone.

[0031] The second FPGA module reads out the signal charge of adjacent pixels after superimposition by controlling the storage zone vertical transfer signal, thereby improving the signal-to-noise ratio of the electronic system; according to different detection requirements, two-pixel merging or three-pixel analog signal merging mode is set.

[0032] Further, the focal plane driving unit includes a third power filter and voltage conversion module, a drive signal conditioning module, and an analog signal preprocessing module.

[0033] The front end of the filter network of the third power supply filter and voltage conversion module is a common mode choke, and the rear end of the filter network is a differential mode choke, which attenuates the interference of differential mode current; the input voltage is converted into the power supply required by the CCD, the driving chip and the operational amplifier through the voltage conversion chip;

[0034] The driving signal conditioning module shapes and amplifies the vertical transfer signal, the horizontal transfer signal and the control signal for driving the CCD to work, and generates various high-voltage driving signals required by the CCD to work;

[0035] The analog signal preprocessing module enhances the CCD analog signal output driving capability and long-distance transmission capability through the rail-to-rail operational amplifier suitable for impedance matching network and single power supply, and improves the signal-to-noise ratio of the electronic system.

[0036] Compared with the prior art, the present application has the following beneficial effects:

[0037] (1) The present application adopts an extremely low-noise analog-to-digital conversion module, which internally integrates a sample-and-hold function and a correlated double sampling mode, and has a programmable gain and a programmable bias function. In order to control the quantization noise to the maximum extent, the ADC chip is set in the correlated double sampling mode during design, and a source terminal series matching resistor is used for each bit at the ADC digital output end, so as to prevent the current feedback error caused by the digital output end data jump, and at the same time, ensure the signal integrity of the digital signal output to the subsequent circuit after AD quantization.

[0038] (2) The present application adopts a low-noise analog signal active filter module, which uses a single power supply low-noise rail-to-rail operational amplifier to perform active filtering on the CCD analog signal input by the focus driving unit, so as to eliminate the noise on the transmission cable between the two and the noise of the signal processing unit itself. According to the analog signal output frequency, a proper filter network is matched to obtain smaller operational amplifier noise. The above-mentioned comprehensive means makes the system circuit noise decrease by 82%.

[0039] (3) The analog signal preprocessing module of the present application realizes the enhancement of the CCD analog signal output driving capability and the long-distance transmission capability through the rail-to-rail operational amplifier suitable for impedance matching network and single power supply, has high voltage slew rate and excellent load driving capability, well improves the problem that the analog signal is not suitable for long-distance transmission, reduces the signal distortion in the cable transmission process, and the system signal-to-noise ratio can be improved by 80%.

[0040] (4) In order to meet the detection requirements of the hyperspectral detector for weak signal targets, the signal charges of adjacent pixels are superimposed and read out through the control of the vertical transfer signal of the detector storage area, so as to greatly improve the signal-to-noise ratio of the system. According to different detection requirements, two-pixel merging or three-pixel merging mode can be set.

[0041] (5) The FPGA module in the signal processing unit of the application integrates the 1553B bus communication function, the second pulse receiving function, the digital image signal receiving function, the synchronization signal generating function, the auxiliary data parsing and scheduling function, and the image data sending function, so that the management control unit and the video processing unit in the traditional on-board electronic system architecture are no longer needed, the number of devices is reduced, the number of software configuration items is compressed, the system volume, weight and power consumption are reduced, the integration of the on-board electronic system is greatly improved, and resource consumption is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is a high-integration high-SNR on-board fluorescence hyperspectral detector electronics system principle diagram for an embodiment of the application;

[0043] Figure 2 It is a signal processing unit principle diagram for an embodiment of the application;

[0044] Figure 3 It is a timing control unit principle diagram for an embodiment of the application;

[0045] Figure 4 It is a focal plane driving unit principle diagram for an embodiment of the application. DETAILED DESCRIPTION

[0046] The application will be further described below in combination with the drawings and embodiments.

[0047] Embodiment 1

[0048] As shown in the drawings, Figure 1 The application provides a high-integration high-SNR on-board fluorescence hyperspectral detector electronics system, which comprises a signal processing unit (including a main board and a backup board), a timing control unit and a focal plane driving unit, wherein:

[0049] The signal processing unit filters and converts the voltage of the input secondary power supply; receives and processes bus instructions and broadcast data of the satellite service to complete the control of the working mode of the detector; collects information reflecting the working state of the detector and uploads it to the satellite service through the bus interface; receives the second pulse signal sent by the satellite GPS subsystem timing unit to generate the time count of the frame synchronization signal; performs extremely low noise quantization on the analog signal transmitted by the focal plane driving unit; encodes and integrates the image data and auxiliary data and sends them to the satellite data transmission subsystem through the data transmission interface; generates a global clock and a global reset signal and sends them to the timing control unit;

[0050] The timing control unit filters and voltage converts the input secondary power supply, generates the secondary power supply required by the focal plane driving unit, receives the global clock and global reset signal sent by the signal processing unit to generate the frame synchronization signal and clock synchronization signal, so that the electronic system works under the same source clock, generates the driving timing signal required by the CCD in the focal plane driving unit, and sends the telemetry reflecting the state of the timing control unit to the signal processing unit.

[0051] The focal plane driving unit filters and voltage converts the input secondary power supply, generates various bias voltages required by the CCD, receives the driving timing signal from the timing control unit, generates various high voltage driving signals required by the CCD, uses a first operational amplifier to power amplify and impedance match the CCD output analog signal, and uses a second operational amplifier to output the power amplified and impedance matched main and backup CCD analog signals to the signal processing unit main board and backup board.

[0052] As shown in Figure 2 The signal processing unit includes a first power supply filtering and voltage conversion module, a low-noise analog signal active filtering module, an extremely low-noise analog-to-digital conversion module, a 1553B bus communication module, a second pulse receiving module, a first FPGA module, a data storage module, a data transmission interface module, and a timing control interface module.

[0053] The front end of the filtering network of the first power supply filtering and voltage conversion module is a common-mode choke coil, which is composed of two windings wound on the same high magnetic permeability magnetic core. The structure of the two windings makes the magnetic field generated by the common-mode current cancel each other out. This structure can obtain a larger inductance value with a smaller volume, and the inductance of each winding can attenuate the common-mode interference current with the ground. The back end of the filtering network is a differential-mode choke coil, which attenuates the interference of differential-mode current. Four voltage conversion chips (LDO) are used to convert the input voltage into the voltage value required by the signal processing unit.

[0054] The low-noise analog signal active filtering module uses a single power supply low-noise rail-to-rail operational amplifier to actively filter the CCD analog signal input from the focal plane driving unit, which can eliminate the noise on the transmission cable between the two and the noise of the signal processing unit itself. According to the output frequency of the analog signal, a suitable filtering network is matched to obtain smaller operational amplifier noise.

[0055] The extremely low noise analog-digital conversion module is used for analog-digital conversion of the CCD analog signal output by the low noise analog signal active filter module. In the embodiment, the extremely low noise ADC chip AD9814 is selected, and the output noise of the chip is only 0.55LSBrms. The quantization bit number of the chip is 14 bits, the single channel maximum sampling rate can reach 7Msps, the internal integrated sampling holding function and the correlated double sampling mode are integrated, and the programmable gain and programmable bias functions are provided. In order to control the quantization noise to the maximum extent, the ADC chip is set in the correlated double sampling mode during design, and the input direct current isolated analog signal is embedded into a fixed voltage of 4V, which is generated by the internal ADC chip. In addition, the source terminal is connected with a matching resistor at each bit of the ADC digital output end, so as to prevent the current feedback error caused by the data jump of the digital output end, and ensure the signal integrity of the digital signal output by the AD quantization to the subsequent circuit.

[0056] The 1553B bus communication module exchanges data with the satellite number tube sub-system through the 1553B bus, receives data type interface instructions and polling instructions, and sends the packaged telemetry parameters to the satellite number tube sub-system. The module adopts a double-redundant 1553B bus structure, including A and B two buses, which are hot backups for each other.

[0057] The second pulse receiving module is used for receiving the second pulse signal sent by the satellite GPS sub-system timing unit, as the time counting reference of the detector, and sending the second pulse signal to the first FPGA module. The first FPGA module starts the local 1MHz counting clock to count the sub-second according to the second pulse signal, and simultaneously calibrates the clock frequency by counting the adjacent two second pulses by using the local 1MHz clock, accurately calculates the imaging starting time of each frame, and marks in the corresponding image auxiliary data, so as to realize the function of accurately calibrating the imaging time of the detector.

[0058] The first FPGA module generates global clock and global reset signal; receives the 1553B bus instructions and data sent by the satellite and returns the telemetry information; receives the two-way second pulse signal of the second pulse receiving module, generates the time count of the frame synchronization signal; receives the digital image signal quantized by the extremely low noise analog-digital conversion module; drives the extremely low noise analog-digital conversion module to work normally according to the working mode requirement; parses and arranges the satellite auxiliary data sent by the 1553B bus communication module, and sends the auxiliary data and image data to the data transmission interface module.

[0059] The data storage module uses external SRAM to cache image data from the first FPGA module, and provides a large amount of storage space for data caching. According to the requirements of the working mode, two frames of image data need to be cached, i.e. two pieces of storage space need to be opened up, respectively for storing the image data of the current frame and outputting the image data of the previous frame, so as to meet the processing of a large amount of image data in a short frame period.

[0060] The data transmission interface module outputs the quantized data of the extremely low noise analog-digital conversion module in the form of LVDS level. In order to ensure the reliability of data transmission, the data transmission interface module adopts a cross hot backup working mode, so that when the signal processing unit main board or the backup board is working, the main and backup data transmission interfaces simultaneously have signal output.

[0061] The timing control interface module sends the global clock and global reset signal generated by the first FPGA module to the timing control unit.

[0062] In the signal processing unit, the first FPGA module integrates the 1553B bus communication function, the second pulse receiving function, the digital image signal receiving function, the synchronization signal generating function, the auxiliary data parsing and scheduling function, and the image data sending function, so that the management control unit and the video processing unit in the traditional spaceborne electronic system architecture are no longer needed, the number of devices is reduced, the number of software configuration items is compressed, the system volume, weight and power consumption are reduced, the integration of the spaceborne electronic system is greatly improved, and the resource consumption is reduced.

[0063] As shown in Figure 3 The timing control unit includes a second power filter and voltage conversion module, a second FPGA module, a buffer, a timing generation module and a signal processing unit interface module.

[0064] The front end of the filter network of the second power filter and voltage conversion module is a common mode choke, which is composed of two windings wound on the same high magnetic permeability magnetic core. The structure of them makes the magnetic field generated by the common mode current offset each other. This structure can obtain larger inductance value with smaller volume, and the inductance of each winding can attenuate the common mode interference current with the ground; the back end of the filter network is a differential mode choke, which attenuates the interference of differential mode current; the input voltage is converted into the voltage value required by the timing control unit through the LDO.

[0065] The second FPGA module is the working core of the timing control unit. In order to ensure the on-orbit reliability, a anti-fuse FPGA chip is used. The main function of the second FPGA is to generate different CCD driving timing signals according to the requirements of the working mode, and at the same time, it has the function of communicating with the signal processing unit.

[0066] The CCD detector used by the spaceborne fluorescence hyperspectral detector needs multiple driving timing signals, which are vertical transfer signals including integration zone vertical transfer signals and storage zone vertical transfer signals horizontal transfer signals including horizontal register transfer signals and reset signals and The control signals include a DG signal for dumping charges in the horizontal register zone and an IG signal for dumping charges in the imaging zone. The timing control unit uses a second FPGA to generate the above driving timing signals.

[0067] In order to meet the detection requirements of the hyperspectral detector for weak signal targets, the second FPGA module controls the storage zone vertical transfer signals of the detector to superimpose and read out the signal charges of adjacent pixels, thereby greatly improving the signal-to-noise ratio of the electronic system. According to different detection requirements, two-pixel merging or three-pixel analog signal merging mode can be set.

[0068] The buffer is used to solve the problem of limited driving capability of the I / O port of the second FPGA module. The driving signals generated by the second FPGA module need to pass through the buffer before being sent to the focal plane driving unit.

[0069] The timing generation module generates clock synchronization, reset synchronization and frame synchronization signals to the second FPGA module according to the global clock and global reset signal input by the signal processing unit.

[0070] The signal processing unit interface module receives the global clock and global reset signal generated by the first FPGA module.

[0071] As shown in Figure 4 , the focal plane driving unit includes a third power filter and voltage conversion module, a driving signal conditioning module and an analog signal preprocessing module.

[0072] The front end of the filter network of the third power filter and voltage conversion module is a common-mode choke, which is composed of two windings wound on the same high magnetic permeability magnetic core. Their structure makes the magnetic field generated by the common-mode current cancel each other out. This structure can obtain a larger inductance value with a smaller volume, and the inductance of each winding can attenuate the common-mode interference current with the ground; the back end of the filter network is a differential-mode choke, which attenuates the interference of differential-mode current; the input voltage is converted into the power required by the CCD detector, the driving chip and the operational amplifier through the LDO.

[0073] The driving signal conditioning module shapes and amplifies the vertical transfer signals, horizontal transfer signals and control signals for driving the CCD to work, and generates various high-voltage driving signals required by the CCD. The vertical transfer signals include integration zone vertical transfer signals and storage zone vertical transfer signals The horizontal transfer signal includes a horizontal register transfer signal and a reset signal and The control signal includes a DG signal for pouring charges in the horizontal register area and an IG signal for pouring charges in the imaging area.

[0074] The analog signal pre-processing module realizes the enhancement of the driving capacity of the CCD analog signal output and the long-distance transmission capacity through a suitable impedance matching network and a rail-to-rail operational amplifier powered by a single power supply, has high voltage swing and excellent load driving capacity, well improves the problem that the analog signal is not suitable for long-distance transmission, reduces the signal distortion in the cable transmission process, and further improves the signal-to-noise ratio of the electronic system.

[0075] To sum up, the high-integration high-signal-to-noise-ratio satellite-borne fluorescence hyperspectral detector electronic system provided by the application adopts highly integrated design, reduces the volume, weight and power consumption of the hyperspectral detector imaging electronic system, simultaneously greatly reduces circuit noise through multiple ways, and adopts multi-pixel analog merging imaging mode, greatly improves the signal-to-noise ratio of the hyperspectral detector system, ensures high-precision quantitative detection of low-brightness and weak-signal targets of ground vegetation fluorescence, and greatly improves the use efficiency of the load.

[0076] Although the application has been disclosed as above with preferred embodiments, it is not intended to limit the application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the application by using the disclosed methods and technical contents without departing from the spirit and scope of the application, therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application without departing from the technical solutions of the application all belong to the protection scope of the technical solutions of the application.

[0077] The contents not described in detail in the specification of the application are the known technology of the person skilled in the art.

Claims

1. A high-integration high-signal-to-noise-ratio spaceborne fluorescence hyperspectral detector electronics system, characterized in that, The signal processing unit, the timing control unit and the focal plane driving unit are included, wherein: The signal processing unit filters and voltage converts the input secondary power supply, receives bus instructions and broadcast data of the satellite service, controls the working mode of the detector, collects information reflecting the working state of the detector, uploads the information to the satellite service through a bus interface, receives a second pulse signal sent by a satellite GPS subsystem timing unit, generates a time count of a frame synchronization signal, performs extremely low noise quantization on an analog signal from the focal plane driving unit, encodes and integrates image data and auxiliary data, and sends the image data and the auxiliary data to a satellite data transmission subsystem; and generates a global clock and a global reset signal and sends the global clock and the global reset signal to the timing control unit; The timing control unit filters and voltage converts the input secondary power supply, generates a secondary power supply required by the focal plane driving unit, receives the global clock and the global reset signal sent by the signal processing unit, generates a frame synchronization signal and a clock synchronization signal, and makes the electronic system work under the same source clock; generates a driving timing signal required by a CCD in the focal plane driving unit; and sends telemetry of the timing control unit to the signal processing unit; The focal plane driving unit filters and voltage converts the input secondary power supply, generates various bias voltages required by the CCD, receives the driving timing signal of the timing control unit, generates various high-voltage driving signals required by the CCD, and outputs the CCD output analog signal to the signal processing unit after power amplification and impedance matching.

2. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 1, characterized in that, The signal processing unit includes a main board and a backup board; and the focal plane driving unit uses a two-stage operational amplifier to output the CCD analog signal after power amplification and impedance matching to the main board and the backup board of the signal processing unit.

3. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 2, characterized in that, The signal processing unit includes a first power supply filtering and voltage conversion module, a low-noise analog signal active filtering module, an extremely low-noise analog-to-digital conversion module, a 1553B bus communication module, a second pulse receiving module, a first FPGA module, a data storage module, a data transmission interface module and a timing control interface module; The front end of the filtering network of the first power supply filtering and voltage conversion module is a common-mode choke, and the rear end of the filtering network is a differential-mode choke; and the input voltage is converted into a voltage value required by the signal processing unit through a voltage conversion chip; The low-noise analog signal active filtering module uses a single power supply rail-to-rail operational amplifier to perform active filtering on the CCD analog signal input by the focal plane driving unit, matches a proper filtering network according to the output frequency of the analog signal, and reduces the operational amplifier noise; The extremely low-noise analog-to-digital conversion module is used to perform analog-to-digital conversion on the CCD analog signal output by the low-noise analog signal active filtering module; The 1553B bus communication module exchanges data with the satellite data transmission subsystem through the 1553B bus, receives data inter-type instructions and polling instructions, and sends the packaged telemetry parameters to the satellite data transmission subsystem; The second pulse receiving module is used to receive the second pulse signal sent by the satellite GPS subsystem timing unit, as a time counting reference of the detector, and send the second pulse signal to the first FPGA module. The first FPGA module generates a global clock and a global reset signal, receives 1553B bus commands and data sent by a satellite and returns telemetry information, receives two second pulse signals of a second pulse receiving module, generates time count of a frame synchronization signal, receives quantized digital image signals of an extremely low noise analog-digital conversion module, drives the extremely low noise analog-digital conversion module to work normally according to the requirements of a working mode, parses and arranges auxiliary data of the whole satellite sent by the 1553B bus communication module, and sends the auxiliary data and image data to a data transmission interface module; The data storage module uses an external SRAM to cache image data of the first FPGA module; The data transmission interface module outputs quantized data of the extremely low noise analog-digital conversion module in the form of an LVDS level, adopts a cross hot backup working mode, and enables the signal processing unit mainboard or the backup board to output signals when working; The timing control interface module sends the global clock and the global reset signal generated by the first FPGA module to a timing control unit.

4. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 3, characterized in that, The extremely low noise analog-digital conversion module uses an AD9814 chip, has an output noise of only 0.55LSB rms, a quantization bit number of 14 bits, a single-channel maximum sampling rate of 7Msps, and an internal integrated sampling and holding function and a correlated double sampling mode, and has programmable gain and programmable bias functions; To maximize the control of quantization noise, the AD9814 chip is set in a correlated double sampling working mode, and an input direct-current-isolated analog signal is embedded into a fixed voltage of 4V, which is generated by the AD9814 chip internally; in addition, a source terminal is connected with a matching resistor at each bit of a digital output end of the AD9814 chip, so as to prevent current feedback errors caused by data jumps of the digital output end, and to ensure signal integrity of digital signals output by the AD after quantization to a subsequent circuit.

5. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 3, characterized in that, The 1553B bus communication module adopts a double-redundant 1553B bus structure, including two buses A and B, which are hot backups of each other.

6. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 3, characterized in that, The timing control unit includes a second power supply filtering and voltage conversion module, a second FPGA module, a timing generation module and a signal processing unit interface module; The front end of a filtering network of the second power supply filtering and voltage conversion module is a common-mode choke, and the rear end of the filtering network is a differential-mode choke; an input voltage is converted into a voltage value required by the timing control unit through a voltage conversion chip; The second FPGA module uses an anti-fuse FPGA chip, which is used to generate different CCD driving timing signals according to the requirements of the working mode, and has the function of communicating with the signal processing unit; The timing generation module generates clock synchronization, reset synchronization and frame synchronization signals to the second FPGA module according to the global clock and the global reset signal input by the signal processing unit; The signal processing unit interface module receives the global clock and the global reset signal generated by the first FPGA module.

7. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 6, characterized in that, The timing control unit further comprises a buffer, which is used to solve the problem of limited driving capability of the I / O port of the second FPGA module, and the driving signal generated by the second FPGA module is sent to the focal plane driving unit through the buffer.

8. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 6, characterized in that, The CCD driving timing signals include: vertical transfer signals, including integration zone vertical transfer signals and storage zone vertical transfer signals horizontal transfer signals, including horizontal register transfer signals and reset signals and control signals, including DG signals for dumping charges in the horizontal register zone and IG signals for dumping charges in the imaging zone The second FPGA module controls the vertical transfer signal of the storage area, superimposes and reads out the signal charges of adjacent pixels, and improves the signal-to-noise ratio of the electronic system; according to different detection requirements, two-pixel merging or three-pixel analog signal merging mode is set.

9. The high-integration high-SNR spaceborne fluorescence hyperspectral detector electronics system according to claim 8, characterized in that, The focal plane driving unit comprises a third power filter and voltage conversion module, a driving signal conditioning module and an analog signal preprocessing module. The front end of the filter network of the third power filter and voltage conversion module is a common-mode choke coil, and the rear end of the filter network is a differential-mode choke coil, which attenuates the interference of differential-mode current; the input voltage is converted into the power required by the CCD, the driving chip and the operational amplifier through the voltage conversion chip; The driving signal conditioning module shapes and amplifies the vertical transfer signal, the horizontal transfer signal and the control signal for driving the CCD to work, and generates various high-voltage driving signals required by the CCD to work; The analog signal preprocessing module enhances the CCD analog signal output driving capability and long-distance transmission capability through the rail-to-rail operational amplifier suitable for impedance matching network and single power supply, and improves the signal-to-noise ratio of the electronic system.

Images