Variable gain amplifier with wide linear gain range and working method

Abstract

The invention relates to the technical field of amplifiers, in particular to a variable gain amplifier with a wide linear gain range and a working method, and the variable gain amplifier comprises the steps that a linear gain generation circuit receives a differential input signal and provides gain-adjustable differential output based on linear control voltage; the linear gain generation circuit comprises at least one stage of variable gain unit which comprises differential input pair transistors MN1 and MN2. The load resistor elements R1 and R2 are connected between the power supply voltage VDD and the drain electrodes of the differential input pair transistors MN1 and MN2; the tail current source MN3 provides bias current for the differential input pair transistors MN1 and MN2; the active load network is connected between the drain electrodes of the differential input pair transistors MN1 and MN2 and the ground; the active load network comprises a control tube MN8, the control tube MN8 works in a sub-threshold region, a grid electrode receives linear control voltage, equivalent impedance of the active load network is enabled to be in exponential change along with the linear control voltage through exponential I-V characteristics, and dB linear gain adjustment of the variable gain unit is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of amplifier technology, in particular to a variable gain amplifier with wide linear gain range and a working method. BACKGROUND

[0002] The statements in this section merely provide background information related to the present application and do not necessarily constitute the prior art.

[0003] Variable gain amplifier (VGA) is the core module to realize automatic gain control (AGC) function in modern wireless communication, radar and high-precision data acquisition system. The performance indicators such as gain adjustment range, dB linearity, noise figure and bandwidth directly determine the dynamic range, sensitivity and signal integrity of the receiving link.

[0004] The gain of the differential amplifier is determined by the transconductance of the amplifier and the load resistance. The current mainstream variable gain amplifier is mainly based on three technical paths: one is to fix the load resistance and adjust the transconductance of the differential input pair to realize gain variation; the second is to fix the transconductance of the differential pair and adjust the load impedance to realize gain control; the third is to adjust the transconductance and load impedance together. However, these traditional schemes have significant limitations. For example, the scheme based on body effect to adjust the load has very limited tuning ability. Related research shows that even with a complex cascade structure of up to 15 stages, the total gain adjustment range is only about 56dB, and the single-stage linear adjustment range is as low as 3.7dB, which not only greatly increases the chip area and power consumption, but also introduces additional phase noise and mismatch risk. Although some other technologies reduce the number of stages, the single-stage adjustment capability is further deteriorated to 1.6dB, which is difficult to meet the application requirements of modern wide dynamic range systems. SUMMARY

[0005] The present application provides a variable gain amplifier with wide linear gain range and a working method, which solves the contradiction between the gain range, linearity and circuit complexity of the traditional variable gain amplifier (VGA). It aims to avoid the high power consumption, large noise and large layout area caused by traditional multi-stage cascade, and overcome the defects of limited gain adjustment range of single adjustment mechanism (such as body effect). The ultimate goal is to realize a single-stage VGA solution that can provide extremely wide (≥40dB) and high-precision dB linear gain adjustment range under standard CMOS process, while maintaining good bandwidth and driving capability, to meet the stringent requirements of modern high-speed wireless communication and data acquisition systems for dynamic range and signal integrity.

[0006] In order to achieve the above purpose, the present application adopts the following technical scheme: The first aspect of the present application provides a variable gain amplifier with wide linear gain range, comprising a linear gain generation circuit for receiving a differential input signal and providing a gain-adjustable differential output based on a linear control voltage; The linear gain generation circuit comprises at least one variable gain cell, which comprises: a differential input pair of transistors MN1 and MN2 for receiving the differential input signal; a load resistance element R 1 and R 2 connected between a power supply voltage VDD and the drain of the differential input pair of transistors MN1 and MN2; a tail current source MN3 for providing a bias current for the differential input pair of transistors MN1 and MN2; an active load network connected between the drain of the differential input pair of transistors MN1 and MN2 and ground; the active load network comprises a control transistor MN8 configured to operate in a sub-threshold region, with its gate receiving the linear control voltage, such that the equivalent impedance of the active load network varies exponentially with the linear control voltage through the exponential I-V characteristic of the control transistor MN8 operating in the sub-threshold region, thereby achieving a dB-linear gain adjustment of the variable gain cell.

[0007] As a further solution, the active load network further comprises a cross-coupled pair of transistors MN4 and MN5 and current source loads MN6 and MN7; the gates and drains of the cross-coupled pair of transistors MN4 and MN5 are cross-connected to the drain output nodes of the differential input pair of transistors MN1 and MN2; the drains of the current source loads MN6 and MN7 are connected to the sources of the cross-coupled pair of transistors MN4 and MN5, respectively, with their sources grounded; the drain and source of the control transistor MN8 are connected to the source nodes of the cross-coupled pair of transistors MN4 and MN5, respectively.

[0008] As a further solution, the transconductance g m of the cross-coupled pair of transistors MN4 and MN5 R 1 and R 2 satisfies the constraint condition: .

[0009] As a further solution, the linear gain generation circuit is formed by cascading two variable gain cells.

[0010] As a further solution, it further comprises a fixed gain amplifier circuit connected to the output of the linear gain generation circuit for improving the bandwidth of the overall circuit.

[0011] As a further scheme, the fixed gain amplifier circuit is a complementary symmetric structure, comprising a second differential input pair of transistors MN9 and MN 10 , a second tail current source MN 11 , a load resistor R 3 and R 4 , and an active load formed by PMOS transistors MP1 and MP2.

[0012] As a further scheme, it further comprises an output buffer circuit, which is connected to the output end of the preceding stage circuit, for providing low output impedance and enhancing the load capacity.

[0013] As a further scheme, the output buffer circuit is a unity gain amplifier, which adopts a double differential pair input structure.

[0014] As a further scheme, the control transistor MN8 is a deep N-well MOS transistor, whose body terminal is not connected to the source terminal, so as to independently control the source and drain potentials.

[0015] The second aspect of the present application provides a working method of a variable gain amplifier with a wide linear gain range, comprising the following steps: Applying a linear control voltage to the gate of the control transistor MN8 in the linear gain generation circuit, so that the control transistor MN8 works in the sub-threshold region, and the exponential I-V characteristic of the sub-threshold region is used to make the equivalent impedance of the control transistor MN8 change exponentially with the linear control voltage, so as to realize gain adjustment; The differential input pair of transistors MN1 and MN2 in the linear gain generation circuit receives a differential input signal, and amplifies the differential input signal through a load determined by the exponentially changed equivalent impedance and the load resistor R 1 and R 2 to generate a differential output signal with a gain that changes linearly in dB with the linear control voltage.

[0016] Compared with the prior art, the above one or more technical solutions have the following beneficial effects: 1. The present application uses the exponential I-V characteristic of the deep N-well MOS transistor (MN8) in the sub-threshold region to construct an equivalent active load that changes exponentially with the linear control voltage, so that a single-stage variable gain amplifier can realize a linear gain adjustment range of more than 30dB. Compared with the traditional scheme, when the same total adjustment range (such as 60dB) is obtained, the required number of stages is reduced by more than 80% (2 stages vs. traditional 10-15 stages), which fundamentally avoids the problems of phase noise accumulation, significant increase in power consumption and chip area expansion caused by multi-stage cascading.

[0017] 2. The gain (dB) in this scheme presents an inherent linear relationship with the control voltage. This mechanism does not rely on complex linearization compensation circuits or digital calibration algorithms, eliminating the design redundancy, additional power consumption and calibration costs introduced thereby, improving the response speed and reliability of the circuit, and enabling good performance consistency under different process corners.

[0018] 3. The modular architecture effectively compensates for the bandwidth contraction of the core VGA unit in high gain mode by a post-stage fixed gain wideband amplifier, ensuring sufficient operating bandwidth throughout the entire gain adjustment range. Meanwhile, the output stage unit gain buffer provides low output impedance, greatly enhancing the circuit's ability to drive the load and system isolation, enabling it to directly drive the subsequent sampling circuit or transmission line.

[0019] 4. All circuits can be implemented based on standard CMOS process without any special process modules. The extremely simple core circuit structure (only a single transistor controls the gain) and the extremely wide single-stage adjustment range greatly reduce the chip area and component quantity required to achieve the same function, significantly reducing manufacturing costs and facilitating the integration of high-performance analog in system-on-chip (SoC). BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which form a part of this description, are included to provide further understanding of the application, and are incorporated in and constitute a part of this application. The embodiments of the application, and their

[0021] Figure 1 is a schematic diagram of the circuit architecture provided by one or more embodiments of the application; Figure 2 is a schematic diagram of the variable gain amplifier partial circuit structure provided by one or more embodiments of the application; Figure 3 is a schematic diagram of the fixed gain amplifier partial circuit structure provided by one or more embodiments of the application; Figure 4 is a schematic diagram of the unit gain amplifier structure provided by one or more embodiments of the application; Figure 5 is a schematic diagram of the output gain curve of the variable gain amplifier controlled by the linear bias voltage provided by one or more embodiments of the application; Figure 6 is a schematic diagram of the output frequency response curve of the variable gain amplifier under different control voltages provided by one or more embodiments of the application. DETAILED DESCRIPTION

[0022] The application will be further described below with reference to the accompanying drawings and embodiments.

[0023] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0024] Deep N-Well MOSFET is a kind of metal-oxide-semiconductor field effect transistor (MOSFET) realized by special semiconductor manufacturing process, which electrically isolates its body region (P-Well) from the global P-type substrate, so that its body terminal potential can be independently biased, thereby obtaining MOSFET devices with characteristics such as body effect elimination, noise isolation enhancement, and support for multi-power domain operation.

[0025] The present scheme provides a variable gain amplifier with a wide linear gain range and a working method. By accurately controlling a deep N-Well MOSFET (MN8) to work in the sub-threshold region, an equivalent active load resistor that changes accurately and exponentially with a linear control voltage is constructed using its inherent exponential I-V characteristic. Through circuit design, the exponentially changing load resistor becomes the only variable of the total dominant differential output impedance, thereby directly converting linear voltage control into dB linear gain change. This "exponential load adjustment mechanism" is the core of realizing wide-range and high-linearity gain adjustment, and has a simple structure without the need for complex auxiliary circuits, greatly improving performance and reducing design redundancy.

[0026] The technical solutions in the embodiments of the application will be described clearly and completely in the embodiments of the application combined with the drawings. Obviously, the described embodiments are only part of the embodiments of the application, not all. The preferred embodiments of the application are described in detail in combination with the drawings. The application protects a variable gain amplifier and the topology of its gain adjustment circuit. Figure 2 The transistors presented in the drawings are only exemplary embodiments, and any one of the following cases falls within the protection scope of the application.

[0027] (1) The same circuit topology connection relationship as shown in the drawings is adopted, and only the transistor type is replaced; (2) The semiconductor manufacturing process is changed (such as replacing CMOS process with BiCMOS process), but the overall circuit topology structure defined by the application is not changed, only the device parameters or specific implementation forms are adjusted to adapt to the process requirements; (3) The circuit is partially cascaded, split, adjusted, or the gain adjustment function module is replaced (such as replacing the Vctrl control logic in other ways), but the core variable gain adjustment topology mechanism is not destroyed, only auxiliary stabilization circuits are added to adapt to the application scenario.

[0028] Figure 3 With Figure 4The shown structure is a typical implementation example, and those skilled in the art can replace it with an equivalent circuit structure based on known technology. The embodiments described in the specification are only used to illustrate the technical principles of the application and do not constitute a limitation on the scope of protection. Any equivalent transformation or technical combination based on the core innovative point of the application belongs to the protection scope of the patent.

[0029] Under the following core conditions, structural adjustments to non-essential modules are allowed: 1) Maintain the sub-threshold operating characteristics of the exponential active load; 2) Ensure that the single-stage VGA gain range is greater than or equal to 40 dB (measured standard).

[0030] Embodiment one: The overall architecture of the variable gain amplifier of this embodiment can be divided into three parts: a linear gain generation circuit, a fixed gain amplifier circuit, and a buffer, which is a unit gain amplifier circuit.

[0031] The linear gain generation circuit is composed of two stages of VGAs with the same structure, and the gain adjustment is achieved through the exponential characteristics of the active load. Specifically, the load tube bias is modulated by a linear control voltage, and the MOS tube exponential I-V characteristics in the sub-threshold region are used to make the load impedance change accurately exponentially with the control voltage, thereby ensuring the dB linear gain characteristic. The fixed gain amplifier circuit adopts a wideband amplifier structure to improve the overall circuit bandwidth range and compensate for the frequency band contraction effect caused by gain adjustment; the buffer circuit is composed of a unit gain amplifier, which provides low output impedance characteristics to enhance the load capacity of the overall circuit.

[0032] By using standard CMOS technology, the overall NMOS transistor is a special case in this structure, in which the control tube MN8 works in the sub-threshold state to ensure that the transistor works in the exponential I-V relationship in the sub-threshold region, that is: Since the source voltage VS of the control tube remains unchanged, the gate voltage VG can be changed VGS to ensure that ID changes exponentially. At the same time, combined with Ohm's law and the equivalent idea, the MN8 drain-source voltage VDS remains unchanged, and through the exponential change of I D , the exponential change of the equivalent impedance of the control tube MN8 can be indirectly realized. Therefore, the overall circuit can realize the accurate exponential change of the load impedance with the linear control voltage, ensuring the dB linear gain adjustment characteristic.

[0033] Based on the auxiliary theorem of linear circuits: , the scheme adopts a fixed transconductance , change the idea of Rout design, compared with other existing structure is special in the circuit structure is simple, high overall stability, low static power consumption, no additional auxiliary circuit for gain control, direct feeding external control signal can realize the function, at the same time, the circuit layout area is small, single stage structure can realize the linear gain range is wide (about 30dB), is conducive to save production cost.

[0034] (1) circuit module function and performance analysis; The architecture diagram of the variable gain generation circuit in the embodiment is shown in Figure 1 .

[0035] The embodiment adopts three modular design: A1: variable gain amplifier (VGA) module, two-stage same structure of VGA cascade constitutes the core gain regulation unit; A2: fixed gain amplifier, used for compensating high frequency response, is an optional module; A3: output buffer circuit, used for enhancing the load capacity of the overall circuit.

[0036] This structure is only the architecture of the embodiment, when the single-stage VGA meets the following conditions, the architecture can be simplified: When the gain range is greater than or equal to 30dB and the bandwidth is greater than or equal to 10MHz, the fixed gain amplifier can be omitted; When the output impedance is less than or equal to 50Ω, the buffer can be omitted.

[0037] The linear gain adjustment performance of the circuit is shown in Figure 5 , the linear regulation voltage VCTRL range is 0.8V-1.6V, the output gain linear range is-46dB-14dB within the 1dB gain error range, that is, the two-stage VGA cascade can realize 60dB linear adjustment range, and the average single-stage VGA can realize 30dB linear range. With 0.1V as the step, V CTRL From 0.8V to 1.6V, the frequency response analysis of the circuit is shown in Figure 6 . V CTRL When =1.6V, the output gain is maximum 14dB, and the 3dB bandwidth is 65MHz. V CTRL When =0.8V, the output gain is minimum-46dB, and the 3dB bandwidth is 5GHz.

[0038] (2) variable gain generation circuit structure; As shown in Figure 2As shown, in this embodiment, the variable gain generation circuit adopts a hybrid design of low subthreshold NMOS transistors (MN1-MN7) + deep N-well MOS transistors (MN8) to form the main circuit of the variable gain amplifier and the gain adjustment circuit of the variable gain amplifier.

[0039] The main circuit structure of the gain amplifier is as follows: MN1 and MN2 form a basic differential pair, and their gates are respectively connected to the input signal. V IN_N , V IN_P The drain is connected to the load resistor respectively. R 1 and R 2 (load resistance) R 1 and R 2 The other end connects VDD The source and tail current transistor MN3 are connected together, and the gate of MN3 is connected to the bias voltage V. BIAS Source grounding ( GND The drain is connected to the source of MN1 / MN2 to provide a constant bias current.

[0040] The variable gain amplifier gain adjustment circuit is structured as follows: the active load structure employs cross-coupling and exponential impedance tuning design, consisting of MN4-MN8, where MN4 and MN5 form a cross-coupled pair of transistors, with the gate of MN4 and the drain of MN5 connected to the output terminal. V OUT_P The gate of MN5 and the drain of MN4 are connected to the output terminal. V OUT_N The sources of MN6 and MN7 are both grounded, and their drains are connected to the sources of MN4 and MN5, respectively. The gates of MN6 and MN7 are connected and powered by an external voltage. V BIAS1 Apply a bias.

[0041] Most importantly, in this embodiment, the drain of the deep N-well transistor MN8 is connected to the source of MN4, and its source is connected to the source of MN5. Its gate is connected to the line control voltage. V CTRL Adjusting the load impedance is a special case. For ease of explanation, the drain of MN8 can also be connected to the source of MN5, and the source to the source of MN4. Utilizing the exponential IV characteristic of MN8 in the subthreshold region, the load impedance is adjusted accordingly. V CTRL The gain varies exponentially, achieving dB linear gain adjustment. To ensure MN8 operates in the subthreshold region, the voltage difference between the gate and source of MN8 must be maintained. V GSAlways meet the MOS tube sub-threshold working conditions: V GS V TH . That is, the gate voltage V CTRL of MN8 V D The difference between the source voltage of MN8 and the threshold voltage of MN8 is less than the threshold voltage of MN8.

[0042] The body terminal (buck terminal) of all the above transistors is grounded. When the two-stage VGA is cascaded, the front stage V OUT_P / V OUT_N Directly connect the back stage V IN_P / V IN_N The rest of the bias V BIAS 、V BIAS1 、V CTRL Synchronous connection.

[0043] (3) Active load impedance exponential variation principle; Based on the fixed differential pair transconductance (g m ), the idea of realizing wide linear range gain adjustment is to accurately control the load resistance (R R L ) The core of this scheme is to use the sub-threshold exponential characteristics of deep N-well MOS tube (MN8) to make the equivalent load impedance change exponentially with the control voltage V CTRL , So as to realize the dB linear gain adjustment. The following will be described in conjunction with the variable gain generation circuit.

[0044] According to the Thevenin equivalent principle, from V OUT_N , V OUT_P The load resistance fed from the port upwards is composed of two parts in parallel: 1) Fixed resistance R 1 and R 2 ; 2) Active load network cross-coupled structure MN4 and MN5 and control tube MN8. Since the control tube MN8 is in the sub-threshold region, for the convenience of subsequent analysis, it is assumed that the equivalent resistance of MN8 is R eq , The following is the derivation process of the equivalent resistance RL of the cross-coupled structure MN4 and MN5 and the control tube MN8 as a whole. ​

[0045] Since MN6 and MN7 act as current sources, they are assumed to be ideal current sources when analyzing small-signal models, and these ideal current sources are disconnected. For example... Figure 2 As indicated by the markings, the circuit has a symmetrical structure. Transistors MN4 and MN5 have the same W / L, and transistors MN6 and MN7 have the same W / L and the same gate bias voltage. Therefore, the current flowing through the two branches is the same. gm 4 =gm 5 =gm , R 1 =R 2 =R .

[0046] Applying the KCL equations to the branches containing MN4 and MN5, we obtain: ; ; in, V A 、V B 、V C 、V D These are the node voltages.

[0047] Combining the above equations, we get: ; in, Differential pair transconductance.

[0048] According to Thevenin equivalence We can obtain, Substituting into the KCL equation, we get: ; because R 1 and R 2 Serial and whole with R L Parallel connection, therefore differential pair load resistance Right now: ; To achieve load impedance Controlled solely by the equivalent resistance R8 of MN8, the key constraints are as follows: Substituting into the above formula, we get: By precisely matching the transconductance of the differential pair ( ) and load resistance (R ),make The expression is simplified to only with R 8 The relevant functions thus completely transform gain adjustment into adjustment of MN. 8 Control. If R 8 Able to follow V CTRL If the gain changes exponentially, it can be adjusted linearly by dB. Based on the characteristics of analog integrated circuits, when MN8 operates in the subthreshold region, its electrical characteristics exhibit an exponential function relationship. Therefore, the design aims to make MN8 operate in this region. It is important to maintain... R 8 and R The resistance values ​​are on the same order of magnitude, if R 8 Much larger R 1 This will cause the equation to fail, which can be controlled by adjusting the number of MN8 connected in parallel. R 8 Make it close R .

[0049] (4) Fixed gain amplifier structure; like Figure 3 As shown, the fixed-gain amplifier section in this embodiment adopts a complementary symmetry structure and is composed of the following components: 3 NMOS transistors (MN9-MN1). 11 ), 2 PMOS transistors (MP1-MP2), 2 resistors ( R 3 - - R 4 Composed of MN9 and MN. 10 This forms a differential input pair of transistors, with their gates connected to the input signals respectively. V IP and V IN The source is connected to MN. 11 The drain, MN 11 As a tail current source, the gate is connected V BIAS2 The source is grounded; the resistor R 3 and R 4 Connected in series, one end is connected to the drain of MN9, output V OUTP The other end is connected to MN 10 Drain, Output V OUTN MP1 and MP2 constitute an active load, with their sources connected in common. VDD Gate interconnect and connected to R3- R 4 Connection points. The NMOS transistor's body (buck terminal) is grounded, and the PMOS transistor's body (buck terminal) is connected to... VDD .

[0050] (5) Unity-gain amplifier structure; like Figure 4 As shown, in this embodiment, the fixed-gain amplifier adopts a dual differential pair input structure, consisting of 6 NMOS transistors (MN). 12 --MN 17 ), 2 resistors ( R 5 --R 6 ) constitutes. MN 12 and MN 14 The gates are connected together to the input signal. V INP1 MN 13 and MN 15 The gates are connected together to the input signal. V INN1 Their sources are respectively connected to MN 16 and MN 17 Drain of MN; 16 and MN 17 As a tail current source, its gate is connected to a common bias voltage. V BIAS2 Both the source and the resistor are grounded. R 5 Connected to VDD With MN 12 Resistance between drain and outlet R 6 Connected to VDD With MN 15 Between the drain and the body. The body (buck) of all NMOS transistors is grounded.

[0051] This solution utilizes the exponential IV characteristic of a deep N-well MOSFET (MN8) in the subthreshold region to construct an equivalent active load that changes precisely exponentially with the linear control voltage. This allows a single-stage variable gain amplifier to achieve a linear gain adjustment range of over 30dB. Compared to traditional solutions, the number of stages required to achieve the same total adjustment range (e.g., 60dB) is reduced by over 80% (2 stages vs. traditional 10-15 stages), fundamentally avoiding the problems of phase noise accumulation, significantly increased power consumption, and chip area expansion caused by multi-stage cascading.

[0052] The dB linearity of the present scheme is directly determined by the physical characteristics of the MOS device, and the gain (dB) and the control voltage present an inherent linear relationship. The mechanism does not depend on complex linearization compensation circuits or digital calibration algorithms, thereby eliminating the design redundancy, additional power consumption and calibration costs introduced thereby, improving the response speed and reliability of the circuit, and enabling it to maintain good performance consistency under different process angles.

[0053] The present scheme adopts a modular architecture, and effectively compensates the bandwidth contraction of the core VGA unit in the high gain mode through the fixed gain wideband amplifier in the later stage, ensuring that sufficient operating bandwidth can be maintained within the entire gain adjustment range. At the same time, the output stage unit gain buffer provides low output impedance, greatly enhancing the load capacity and system isolation of the circuit, enabling it to directly drive the subsequent sampling circuit or transmission line.

[0054] The present scheme can be implemented based on standard CMOS process, without any special process modules. The extremely simple core circuit structure (only a single transistor controls the gain) and the extremely wide single-stage adjustment range greatly reduce the chip area and the number of components required to achieve the same function, significantly reducing the manufacturing cost, and are very beneficial to the integration and promotion of high-performance analog IP in system-on-chip (SoC).

[0055] Embodiment two: A variable gain amplifier with a wide linear gain range, the working method comprising the following steps: A linear control voltage is applied to the gate of the control tube MN8 in the linear gain generation circuit, so that the control tube MN8 works in the sub-threshold region, and the exponential I-V characteristic of the sub-threshold region is used to make the equivalent impedance of the control tube MN8 change exponentially with the linear control voltage, so as to realize gain adjustment; The differential input pair tubes MN1 and MN2 in the linear gain generation circuit receive the differential input signal, and the differential output signal with dB linearly changing gain with the linear control voltage is generated by the load resistance R 1 And R 2 The load determined by the exponentially changing equivalent impedance amplifies the differential input signal to generate a differential output signal with dB linearly changing gain with the linear control voltage.

[0056] By using standard CMOS process, the whole adopts NMOS transistor, which is a special case. In this structure, the control tube MN8 works in the sub-threshold state to ensure that the transistor works in the sub-threshold region to meet the inherent exponential I-V relationship, that is: Since the control tube source voltage VS remains unchanged, the control of its gate voltage VG can change VGS and ensure the exponential change of ID. At the same time, combined with Ohm's law and equivalent idea, the MN8 drain-source voltage VDS is unchanged, and through the exponential change of ID, the exponential change of the equivalent impedance of the control tube MN8 can be indirectly realized. Therefore, the overall circuit can realize the accurate exponential change of the load impedance with the linear control voltage, and ensure the dB linear gain adjustment characteristic.

[0057] Based on the auxiliary theorem of linear circuit: The scheme adopts the idea of fixing the transconductance Gm and changing the Rout for design, and compared with other existing structures, the special place is that the circuit structure is simple, the overall stability is high, the static power consumption is low, no additional auxiliary circuit is needed for gain control, the external control signal can be directly fed to realize the function, at the same time, the circuit layout area is small, the linear gain range (about 30dB) can be realized by single-stage structure, which is beneficial to save production cost.

[0058] The above only describes the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A variable gain amplifier with a wide linear gain range, characterized by, The linear gain generation circuit comprises a linear gain generation circuit for receiving a differential input signal and providing a gain-adjustable differential output based on a linear control voltage; The linear gain generation circuit comprises at least one variable gain unit, which comprises: a differential input pair of transistors MN1 and MN2 for receiving a differential input signal; Load resistance element R 1 And R 2 connected between a supply voltage VDD and the drains of the differential input pair transistors MN1 and MN2; a tail current source MN3 for providing a bias current for the differential input pair of transistors MN1 and MN2; an active load network connected between the drains of the differential input pair of transistors MN1 and MN2 and ground; the active load network comprises a control transistor MN8 configured to operate in a sub-threshold region, with its gate receiving a linear control voltage, and through its exponential I-V characteristic in the sub-threshold region, the equivalent impedance of the active load network changes exponentially with the linear control voltage, thereby achieving dB linear gain adjustment of the variable gain unit.

2. A variable gain amplifier of wide linear gain range as claimed in claim 1, characterized in that, The active load network further comprises a cross-coupled pair of transistors MN4 and MN5 and current source loads MN6 and MN7; The gates and drains of the cross-coupled pair of transistors MN4 and MN5 are cross-connected to the drain output nodes of the differential input pair of transistors MN1 and MN2; The drains of the current source loads MN6 and MN7 are respectively connected to the sources of the cross-coupled pair of transistors MN4 and MN5, and their sources are grounded; The drain and source of the control transistor MN8 are respectively connected to the source nodes of the cross-coupled pair of transistors MN4 and MN5.

3. A variable gain amplifier of wide linear gain range as claimed in claim 2, characterized in that, The transconductance g of the cross-coupled pair of transistors MN4 and MN5 m with the load resistance element R 1 and R 2 the resistance value of the load resistance element satisfies a constraint condition: .

4. A variable gain amplifier of wide linear gain range as claimed in claim 1, characterized in that, The linear gain generation circuit is formed by cascading two variable gain unit stages.

5. A variable gain amplifier of wide linear gain range as claimed in claim 1, characterized in that, Further comprising: a fixed gain amplifier circuit connected to the output of the linear gain generation circuit for improving the bandwidth of the overall circuit.

6. A variable gain amplifier of wide linear gain range as claimed in claim 5, characterized in that, The fixed gain amplifier circuit is a complementary symmetrical structure, including a second differential input pair of transistors MN9 and MN 10 , a second tail current source MN 11 , a load resistor R 3 and R 4 , and an active load composed of PMOS transistors MP1 and MP2.

7. A variable gain amplifier of wide linear gain range as claimed in claim 1, characterized in that, Further comprising: an output buffer circuit connected to the output of the previous stage circuit for providing low output impedance and enhancing load capability.

8. A variable gain amplifier of wide linear gain range as claimed in claim 7, characterized in that, The output buffer circuit is a unity gain amplifier using a double differential pair input structure.

9. A variable gain amplifier of wide linear gain range as claimed in claim 1, characterized in that, The control transistor MN8 is a deep N-well MOS transistor with its body and source not connected to achieve independent control of the source and drain potentials.

10. A method of operating a variable gain amplifier having a wide linear gain range according to any one of claims 1-9, characterized by, The steps include: applying a linear control voltage to the gate of the control transistor MN8 in the linear gain generation circuit to make the control transistor MN8 operate in a sub-threshold region, and using its exponential I-V characteristic in the sub-threshold region to make its equivalent impedance change exponentially with the linear control voltage to achieve gain adjustment; The differential input signal is received by the tubes MN1 and MN2 in the linear gain producing circuit, and is amplified by the load resistance R 1 and R 2 The differential input signal is amplified by the load resistance, which is determined by the exponentially varying equivalent impedance, to produce a differential output signal with a gain that varies linearly in dB with the linear control voltage.

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