Signal source and test system

Abstract

The invention provides a signal source and a test system, and belongs to the technical field of signal processing, the signal source comprises a phase-locked loop and a controller connected with the phase-locked loop, the controller is used for obtaining a first test parameter, and the first test parameter comprises a target output frequency; determining a target locking voltage corresponding to the target output frequency based on the mapping data table; adjusting an output voltage of a resistance voltage dividing network in the phase-locked loop to be a target locking voltage; the working state of the phase-locked loop is modified from a closed-loop state to an open-loop state, so that the resistance potential-divider network outputs voltage to a loop filter in the phase-locked loop; and modifying the working state of the phase-locked loop from an open-loop state to a closed-loop state, so that a phase discriminator in the phase-locked loop outputs voltage to a loop filter. The resistance potential-divider network is used for outputting voltage to the loop filter, the frequency can be rapidly adjusted to be close to the target output frequency, when the phase-locked loop is in a closed loop state, the frequency is rapidly locked to the target output frequency, and frequency agility is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and in particular to a signal source and a test system. BACKGROUND

[0002] With the rapid development of communication technology, especially with the rapid development of digital communication, radar, information warfare, electronic countermeasure and other technologies, higher requirements are put forward for signal sources. For example, for some test scenarios, a signal source is required to generate a high-speed frequency hopping signal, and the hopping speed of the high-speed frequency hopping signal reaches 10,000 hops / s.

[0003] In the related technical solution, the following two ways are used to generate a frequency modulation signal: The first way is to use a standard microwave analog signal source to realize, specifically, the standard microwave analog signal source generates a continuous wave signal corresponding to the frequency first, then generates a pulse signal and modulates it to the continuous wave signal. Such a process takes a long time, and the frequency switching time of the standard microwave analog signal source is relatively long, so that a single test frequency point needs to consume a long time, thereby affecting the overall test process.

[0004] The second way is to use a voltage-controlled oscillator (VCO) to directly generate a frequency hopping signal. This way is suitable for the case where the frequency of the frequency hopping signal is low. For the case where the frequency of the frequency hopping signal is high, the hardware requirement is relatively high, so that the cost of the test is relatively high.

[0005] As can be seen from the above, if a standard microwave analog signal source is used to generate a high-speed frequency hopping signal for testing, the test time-consuming is relatively long, and directly using a voltage-controlled oscillator has the problem of high test cost. SUMMARY

[0006] The present application provides a signal source and a test system to solve the problem in the related art that using a standard microwave analog signal source to generate a high-speed frequency hopping signal for testing results in relatively long test time-consuming, and directly using a voltage-controlled oscillator has the problem of high test cost.

[0007] The present application provides a signal source, which comprises a phase-locked loop and a controller connected with the phase-locked loop, and the controller is used to: obtain a first test parameter, the first test parameter comprising a target output frequency; determine a target locking voltage corresponding to the target output frequency based on a mapping data table, the mapping data table comprising a plurality of mapping relationships, each mapping relationship comprising an output frequency and a locking voltage corresponding to the output frequency, and the output frequencies in different mapping relationships are different; adjusting an output voltage of a resistance voltage dividing network in the phase-locked loop to be the target locking voltage; modifying an operating state of the phase-locked loop from a closed loop state to an open loop state, so that the resistance voltage dividing network outputs a voltage to a loop filter in the phase-locked loop; modifying the operating state of the phase-locked loop from the open loop state to the closed loop state, so that a phase detector in the phase-locked loop outputs a voltage to the loop filter.

[0008] The signal source provided by the application comprises: a first switch, a first input end of the first switch being connected with an output end of the resistance voltage dividing network, a second input end of the first switch being connected with an output end of the phase detector, and an output end of the first switch being connected with an input end of the loop filter; a voltage controlled oscillator, an input end of the voltage controlled oscillator being connected with an output end of the loop filter, and an output end of the voltage controlled oscillator serving as an output end of the phase-locked loop; a radio frequency divider, an input end of the radio frequency divider being connected with the voltage controlled oscillator, and an output end of the radio frequency divider being connected with a first input end of the phase detector; The controller is specifically configured to: control the first switch to perform a first action, so that the first input end of the first switch is in communication with the output end of the first switch; The controller is specifically configured to: control the first switch to perform a second action, so that the second input end of the first switch is in communication with the output end of the first switch.

[0009] The controller is specifically configured to: determine a first output frequency in the mapping data table that is closest to the target output frequency; determine a locking voltage corresponding to the first output frequency as the target locking voltage.

[0010] The signal source provided by the application further comprises: a multiplexer; a frequency multiplier, an input end of the frequency multiplier being connected with an output end of the voltage-controlled oscillator, an output end of the frequency multiplier being connected with a first input end of the multiplexer, the output end of the voltage-controlled oscillator being connected with a second input end of the multiplexer; a first frequency divider, an input end of the first frequency divider being connected with the output end of the voltage-controlled oscillator, an output end of the first frequency divider being connected with a third input end of the multiplexer.

[0011] The signal source provided by the application further comprises: a first voltage-controlled attenuator, an input end of the first voltage-controlled attenuator being connected with an output end of the phase-locked loop; a second voltage-controlled attenuator, an input end of the second voltage-controlled attenuator being connected with an output end of the first voltage-controlled attenuator; a mechanical attenuator, an input end of the mechanical attenuator being connected with an output end of the second voltage-controlled attenuator; a digital-to-analog converter, output ends of the digital-to-analog converter being connected with control ends of the first voltage-controlled attenuator and the second voltage-controlled attenuator respectively, an input end of the digital-to-analog converter being connected with the controller; The first test parameter further comprises a target output power, and the controller is further configured to: determine a target control voltage corresponding to the target output power based on a calibration data table, the calibration data table comprising a plurality of calibration data relationships, each calibration data relationship comprising an output power and a control voltage corresponding to the output power; control the digital-to-analog converter to output the target control voltage to the first voltage-controlled attenuator and the second voltage-controlled attenuator.

[0012] The signal source provided by the application, the mechanical attenuator has at least two signal output ends, and signals output by different signal output ends are the same.

[0013] The signal source provided by the application, the controller is further configured to: obtain a test parameter list, the test parameter list comprising a plurality of test parameters, and the plurality of test parameters comprising a first test parameter; if a trigger signal is received during operation of the phase-locked loop according to the first test parameter, a second test parameter is searched based on the test parameter list to control the phase-locked loop to operate according to the second test parameter; The first test parameter and the second test parameter are adjacent test parameters.

[0014] The signal source provided by the application further comprises: a frequency synthesizer; The phase-locked loop further comprises: a reference frequency divider, an input terminal of the reference frequency divider being connected with an output terminal of the frequency synthesizer, and an output terminal of the reference frequency divider being connected with a second input terminal of the phase detector.

[0015] The signal source provided by the application has a control interface of the frequency synthesizer being a parallel interface.

[0016] The application provides a test system, comprising: The signal source according to any one of the above; The device to be tested; The host computer is in communication with the signal source and the device to be tested respectively, and is configured to send a trigger signal to the signal source and the device to be tested, the trigger signal comprising a first rising edge, a first falling edge and a first low-level signal with a first time length. The signal source is configured to set the first test parameter when the first rising edge is detected, confirm the first test parameter taking effect when the first falling edge is detected, and output a pulse signal corresponding to the first test parameter when the time length of the low-level signal is greater than or equal to the first time length.

[0017] The signal source and the test system provided by the application can pre-construct a mapping data table, so that after receiving the first test parameter, the target locking voltage corresponding to the target output frequency in the first test parameter can be determined by using the mapping data table, and the output voltage of the resistance voltage dividing network in the phase-locked loop can be adjusted to the target locking voltage. When the phase-locked loop works in an open loop state, the output voltage of the resistance voltage dividing network to the loop filter in the phase-locked loop can quickly adjust the frequency of the phase-locked loop output signal to the vicinity of the target output frequency, and by switching the working state of the phase-locked loop to a closed loop state, the frequency of the phase-locked loop output signal can be quickly locked to the target output frequency. In this process, the response time of the phase-locked loop can be reduced, and frequency agility can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0019] Figure 1 is a flowchart of the working logic of the controller provided by the application; Figure 2 is one of the partial topological schematic diagrams of the signal source provided by the application; Figure 3Figure 2 is a second part of a topological diagram of a signal source provided by the present application; Figure 4 Figure 3 is a diagram of power conversion provided by the present application; Figure 5 Figure 4 is a schematic block diagram of a signal source provided by the present application; Figure 6 Figure 5 is a flow diagram of a running flow of a signal source provided by the present application; Figure 7 Figure 6 is a diagram of a working principle of a trigger signal provided by the present application.

[0020] Reference signs: 200, phase-locked loop; 201, resistance voltage division network; 202, loop filter; 203, phase discriminator; 204, first switch; 205, voltage-controlled oscillator; 206, radio frequency frequency divider; 207, multiplexer; 208, frequency multiplier; 209, first frequency divider; 210, reference frequency divider; 300, frequency synthesizer; 401, first voltage-controlled attenuator; 402, second voltage-controlled attenuator; 403, mechanical attenuator; 404, digital-to-analog converter. DETAILED DESCRIPTION

[0021] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0022] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device including the element. The terms "upper", "lower" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. Unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0023] The terms "first", "second", and the like used in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / ", generally means that the front and rear associated objects are in an "or" relationship.

[0024] The following will be described in conjunction with Figures 1-7 The signal source and test system provided by the present application are described, aiming at improving the related art that uses a standard microwave analog signal source to generate a high-speed frequency hopping signal for testing, which takes a relatively long time, and directly using a voltage-controlled oscillator has the problem of high test cost.

[0025] The present application provides a signal source, Figure 1 is a flowchart of the working logic of the controller provided by the present application, Figure 2 is one of the partial topological schematic diagrams of the signal source provided by the present application, as Figure 1 and Figure 2 As shown in the figure, the signal source includes a phase-locked loop 200 and a controller (not shown in the figure) connected with the phase-locked loop, and the controller performs the following steps: Step 101, obtaining a first test parameter, the first test parameter comprising a target output frequency.

[0026] The target output frequency is the frequency of the frequency hopping signal that the signal source wants to output.

[0027] For example, the target output frequency can be 5 GHz, 10 GHz or other values, which are not described here.

[0028] Step 102, determining a target locking voltage corresponding to the target output frequency based on a mapping data table, the mapping data table comprising a plurality of mapping relationships, each mapping relationship comprising an output frequency and a locking voltage corresponding to the output frequency, and the output frequencies in different mapping relationships being different.

[0029] In some embodiments, the mapping data table is obtained in the following way: The working state of the phase-locked loop 200 is switched to a closed-loop state, all test frequencies are traversed at a preset step size (the step size can be configured, and the default is 1 MHz), after each frequency is stabilized, the locking voltage of the voltage-controlled oscillator 205 in the phase-locked loop 200 is collected through an analog-to-digital converter, and a data table of the frequency and the locking voltage is generated based on the frequency and the locking voltage of the voltage-controlled oscillator 205 in the phase-locked loop 200 collected by the analog-to-digital converter, wherein the frequency is the output frequency in the present application, and the data table of the frequency and the locking voltage is the mapping data table in the present application.

[0030] Step 103, adjusting the output voltage of the resistance voltage dividing network in the phase-locked loop to the target locking voltage.

[0031] In some embodiments, the maximum value (Vmax) and the minimum value (Vmin) of the locking voltage in the mapping data table are obtained, the resistance parameter of the resistance voltage dividing network 201 in the phase-locked loop 200 is adjusted so that the output voltage range of the resistance voltage dividing network 201 covers [Vmin, Vmax], for example, [Vmin-0.1V, Vmax+0.1V], and the voltage dividing positions are divided according to the frequency interval, so that the output voltage of each position is approximately matched with the average locking voltage of the corresponding interval.

[0032] The average locking voltage is obtained by using an analog-to-digital converter to realize data collection and obtain an average value.

[0033] In this process, the output voltage of the resistance voltage dividing network 201 is selected by selecting the voltage dividing position of the resistance voltage dividing network 201, so that the output voltage of the resistance voltage dividing network 201 is the target locking voltage.

[0034] Exemplarily, the target lock voltage is 6.5V, and the resistance voltage dividing network 201 has three voltage dividing gears, i.e., a first gear, a second gear and a third gear, wherein the average lock voltage of the resistance voltage dividing network 201 corresponding to the first gear is 3V, the average lock voltage of the resistance voltage dividing network 201 corresponding to the second gear is 6V, and the average lock voltage of the resistance voltage dividing network 201 corresponding to the third gear is 9V. 6V is the closest to the target lock voltage, and thus the voltage dividing gear of the resistance voltage dividing network 201 is selected as the second gear.

[0035] In step 104, the working state of the phase-locked loop is modified from the closed loop state to the open loop state, so that the resistance voltage dividing network outputs a voltage to the loop filter in the phase-locked loop.

[0036] In step 105, the working state of the phase-locked loop is modified from the open loop state to the closed loop state, so that the phase detector in the phase-locked loop outputs a voltage to the loop filter.

[0037] In this embodiment, the mapping data table is constructed in advance, so that after receiving the first test parameter, the target lock voltage corresponding to the target output frequency in the first test parameter can be determined by using the mapping data table, and the output voltage of the resistance voltage dividing network 201 in the phase-locked loop 200 is adjusted to the target lock voltage. When the phase-locked loop 200 works in the open loop state, the frequency of the output signal of the phase-locked loop 200 can be quickly adjusted to the vicinity of the target output frequency by using the resistance voltage dividing network 201 to output a voltage to the loop filter 202 in the phase-locked loop 200. By switching the working state of the phase-locked loop 200 to the closed loop state, the frequency of the output signal of the phase-locked loop 200 can be quickly locked to the target output frequency by using the phase detector 203 to output a voltage to the loop filter 202. In this process, the response time of the phase-locked loop 200 can be reduced, and frequency agility can be achieved.

[0038] In this process, the frequency synthesizer 300 does not need to have a higher hardware requirement, and thus the response time of the phase-locked loop 200 can be reduced while the original cost is maintained, and frequency agility can be achieved.

[0039] Exemplarily, for the target output frequency ft, the target lock voltage Vt corresponding to the target output frequency is obtained by searching the mapping data table, and when the phase-locked loop 200 is switched to the open loop state, a voltage close to Vt is output by the resistance voltage dividing network 201. At this time, the voltage controlled oscillator 205 in the phase-locked loop 200 is driven to quickly approach the target output frequency, and after a preset time delay, the phase-locked loop 200 is switched to the closed loop state. The phase-locked loop 200 is closed loop locked, and a signal with the accurate target output frequency is output.

[0040] In some embodiments, the phase-locked loop 200 comprises: The first switch 204 has a first input end connected with the output end of the resistance voltage dividing network 201, a second input end connected with the output end of the phase detector 203, and an output end connected with the input end of the loop filter 202. The voltage controlled oscillator 205 has an input end connected with the output end of the loop filter 202, and an output end as the output end of the phase-locked loop 200. The radio frequency divider 206 has an input end connected with the voltage controlled oscillator 205, and an output end connected with the first input end of the phase detector 203. The controller is specifically configured to: control the first switch 204 to perform a first action, so that the first input end of the first switch 204 is in communication with the output end of the first switch 204; The controller is specifically configured to: control the first switch 204 to perform a second action, so that the second input end of the first switch 204 is in communication with the output end of the first switch 204.

[0041] In this embodiment, when the first switch 204 performs the first action so that the first input end of the first switch 204 is in communication with the output end of the first switch 204, the resistance voltage dividing network 201 outputs the voltage to the loop filter 202 in the phase-locked loop 200, at this time, the voltage controlled oscillator 205 can quickly work near the target output frequency, and when the first switch 204 performs the second action so that the second input end of the first switch 204 is in communication with the output end of the first switch 204, the phase detector 203 is used to output the voltage to the loop filter 202, so as to realize the locking of the voltage controlled oscillator 205 from the nearby frequency to the target output frequency, in this process, the signal locking time during frequency switching is greatly shortened, the response time of the phase-locked loop 200 is shortened, so as to reduce the frequency hopping time and realize the frequency agility.

[0042] In some embodiments, the first action is an action of connecting the first input end of the first switch 204 with the output end of the first switch 204. Similarly, the second action is an action of connecting the second input end of the first switch 204 with the output end of the first switch 204.

[0043] In some embodiments, the first switch 204 is a single-pole double-throw switch.

[0044] In the case that the second input end of the first switch 204 is in communication with the output end of the first switch 204, the radio frequency divider 206 feeds back the signal collected from the voltage-controlled oscillator 205 to the first input end of the phase discriminator 203, so that the phase discriminator 203 compares the signal collected by the radio frequency divider 206 with the received reference signal, thereby determining the signal output to the loop filter 202.

[0045] The signal source provided by the application determines a target locking voltage corresponding to a target output frequency based on a mapping data table, and the controller is specifically used for: determining a first output frequency in the mapping data table that is closest to the target output frequency; taking a locking voltage corresponding to the first output frequency as the target locking voltage.

[0046] In this embodiment, the target locking voltage corresponding to the target output frequency can be quickly located, thereby greatly shortening the signal locking time during frequency switching, shortening the response time of the phase-locked loop 200, thereby reducing the frequency hopping time and realizing frequency agility.

[0047] In some embodiments, the mapping data table includes three mapping relationships, namely a first mapping relationship, a second mapping relationship and a third mapping relationship, wherein the output frequency in the first mapping relationship is 3GHz, the output frequency in the second mapping relationship is 4GHz, and the output frequency in the third mapping relationship is 5GHz, if the target output frequency is 3.6GHz, the second mapping relationship is selected, 4GHz is taken as the closest first output frequency, and the locking voltage corresponding to 4GHz is taken as the target locking voltage.

[0048] In some embodiments, as shown in Figure 2 the signal source further includes: a multiplexer 207; a frequency multiplier 208, the input end of the frequency multiplier 208 is connected with the output end of the voltage-controlled oscillator 205, the output end of the frequency multiplier 208 is connected with the first input end of the multiplexer 207, and the output end of the voltage-controlled oscillator 205 is connected with the second input end of the multiplexer 207; a first frequency divider 209, the input end of the first frequency divider 209 is connected with the output end of the voltage-controlled oscillator 205, and the output end of the first frequency divider 209 is connected with the third input end of the multiplexer 207.

[0049] In this embodiment, the core function of the frequency multiplier 208 is to amplify the frequency of the input signal by a fixed integer multiple (2 times, 3 times, 4 times, …, N times, N is a positive integer), while keeping the key characteristics of the signal (such as phase continuity, modulation information), and output a higher frequency signal; the core function of the first frequency divider 209 is to separate the input wideband signal into multiple sub-signals with different frequency ranges according to a preset standard.

[0050] The frequency multiplier 208 can amplify the frequency of the signal output by the output end of the voltage-controlled oscillator 205, and the first frequency divider 209 can separate the frequency of the signal output by the output end of the voltage-controlled oscillator 205 to obtain a signal with a lower frequency. The multi-selector 207 can select the output result of the frequency multiplier 208, the signal output by the output end of the voltage-controlled oscillator 205, or the output result of the first frequency divider 209 for output, so as to expand the frequency of the signal that the signal source can output, and thus meet the testing needs in more scenarios.

[0051] For example, if the frequency of the signal output by the output end of the voltage-controlled oscillator 205 is 1 GHz to 4 GHz, after using the frequency multiplier 208, it can be expanded to 4 GHz to 16 GHz, and the use of the first frequency divider 209 can expand 0.25 GHz to 1 GHz. As can be seen from the above, the use of the frequency multiplier 208, the first frequency divider 209 and the voltage-controlled oscillator 205 can make the signal source have a wider range of output signals, and thus meet the testing needs in more scenarios.

[0052] In some embodiments, as shown in Figure 3 The signal source further includes: A first voltage-controlled attenuator 401, the input end of the first voltage-controlled attenuator 401 is connected with the output end of the phase-locked loop 200; A second voltage-controlled attenuator 402, the input end of the second voltage-controlled attenuator 402 is connected with the output end of the first voltage-controlled attenuator 401; A mechanical attenuator 403, the input end of the mechanical attenuator 403 is connected with the output end of the second voltage-controlled attenuator 402; A digital-to-analog converter 404, the output end of the digital-to-analog converter 404 is connected with the control end of the first voltage-controlled attenuator 401 and the control end of the second voltage-controlled attenuator 402 respectively, and the input end of the digital-to-analog converter 404 is connected with a controller; The first test parameter further includes a target output power, and the controller is further configured to: determine a target control voltage corresponding to the target output power based on a calibration data table, the calibration data table includes a plurality of calibration data relationships, each calibration data relationship includes an output power and a control voltage corresponding to the output power; The digital-to-analog converter 404 outputs a target control voltage to the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402.

[0053] The internal structure of the mechanical attenuator 403 is mechanical, and it is difficult to realize fast switching. Therefore, if only the mechanical attenuator 403 is used to realize fast adjustment of power, the mechanical attenuator 403 is easily damaged.

[0054] In the technical solution of the present application, the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 are arranged on the basis of the mechanical attenuator 403, and the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 are used to realize small-step attenuation of power. The mechanical attenuator 403, as a large-step attenuator, is used as a final power adjustment device, and does not need to be switched fast. Only the small-step attenuation of the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 is needed to realize fast adjustment of power. In this process, a wide range of signal power adjustment can be realized.

[0055] Specifically, the attenuation amount of the mechanical attenuator 403 is fixed, and the power is completely adjusted by the small-step voltage-controlled attenuator (i.e., the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402), so as to improve the signal switching efficiency and the reliability of the test working condition.

[0056] In the above technical solution, the target control voltage for controlling the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 is obtained by searching the calibration data table with the target output power as the target. In this process, the target control voltage of the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 during power adjustment can be quickly located, the time for power adjustment is shortened, and the power adjustment accuracy is improved.

[0057] In some embodiments, the mechanical attenuator 403 has at least two signal output ends, and the signals output by different signal output ends are the same.

[0058] In this embodiment, by limiting the mechanical attenuator 403 to have at least two signal output ends, the signal source can output the same signal through the at least two signal output ends at the same time, so as to meet the test needs in different scenarios.

[0059] In the present application, the signals output by different signal output ends are frequency hopping signals, which are output in the form of pulses.

[0060] In some embodiments, the mechanical attenuator 403 has two signal output ends, and the signals output by the two signal output ends are the same, as shown in FIG. 2. Figure 5As shown, the signal output from one of the two signal output terminals (such as channel 1) is used as the horizontal polarization excitation signal, and the signal output from the other of the two signal output terminals (such as channel 2) is used as the vertical polarization excitation signal, thereby performing tests on the device under test in different scenarios.

[0061] In some embodiments, the signal source has a first signal output terminal, a second signal output terminal and a third signal output terminal, wherein the first signal output terminal is the output terminal of the first voltage-controlled attenuator 401, the second signal output terminal is the output terminal of the second voltage-controlled attenuator 402, and the third signal output terminal is the signal output terminal of the mechanical attenuator 403.

[0062] During this process, the target control voltage of the first voltage-controlled attenuator 401 and the second voltage-controlled attenuator 402 can be configured according to the test requirements, and then signals with different power can be output using the first signal output terminal, the second signal output terminal and the third signal output terminal, so as to meet the test requirements under different scenarios.

[0063] For example, such as Figure 4 As shown, power switching from -40dBm to 0dBm can be achieved within 2ms.

[0064] In some embodiments, the controller is further configured to: Obtain the test parameter list, which includes multiple test parameters, including the first test parameter; During the operation of the phase-locked loop 200 according to the first test parameters, if a trigger signal is received, the second test parameters are searched based on the test parameter list to control the phase-locked loop 200 to operate according to the second test parameters; Among them, the first test parameter and the second test parameter are two adjacent test parameters.

[0065] In this embodiment, the test parameters can exist in the form of a test parameter list. By constructing a test parameter list, the second test parameters can be quickly determined after the test is completed according to the first test parameters. In this process, the overall test efficiency can be improved.

[0066] In some embodiments, the test parameter list is a list of multiple preprocessed test parameters.

[0067] Preprocessing is the process of setting test parameters for the signal source. This involves processing the set test parameters in real time and then transmitting the processing results to various functional modules through the control interface, thereby completing the parameter setting.

[0068] In the signal source, the parameter quick change response needs to be tested, and the above process needs to be executed for each test parameter, which takes a long time. By limiting the test parameter list, which is a list of pre-processed multiple test parameters, the processing of each test parameter is not required, and thus the overall test efficiency can be improved.

[0069] In some embodiments, the test parameter list is a list stored in the memory, so that the signal source can quickly call the test parameters when performing the test.

[0070] If the trigger signal is received, the test parameter list in the memory can be used to quickly switch to the next test parameter, and the parameter call distribution can be directly completed.

[0071] In some embodiments, the running process of the signal source includes a parameter initialization configuration process and a test process, wherein the parameter initialization configuration process corresponds to steps 601 to 606, and the test process corresponds to steps 607 to 611, as shown in Figure 6 The running process of the signal source includes: Step 601, set the signal frequency and power list.

[0072] The signal frequency and power list is also the test parameter list in the present application.

[0073] Step 602, calculate the module parameters according to the signal frequency and power list.

[0074] Step 603, write the module parameters into the memory.

[0075] Step 604, set the test parameters and switch to the external trigger mode.

[0076] Step 605, set the signal pulse width and turn on the internal pulse generation switch.

[0077] Step 606, set the signal pulse trigger mode to frequency scanning trigger.

[0078] Step 607, turn on the signal output.

[0079] Step 608, the signal source receives the trigger signal, and if the judgment result is yes, step 609 is executed, and if the judgment result is no, step 610 is executed.

[0080] Step 609, the signal source extracts the corresponding parameters in the memory to generate the corresponding pulse signal.

[0081] Step 610, wait for the trigger signal.

[0082] Step 611, whether it is the last list parameter, if the judgment result is yes, end, and if the judgment result is no, execute step 610.

[0083] In some embodiments, such as Figure 2 As shown, the signal source also includes: Frequency synthesizer 300; Phase-locked loop 200 also includes: The reference frequency divider 210 has its input terminal connected to the output terminal of the frequency synthesizer 300, and its output terminal connected to the second input terminal of the phase detector 203.

[0084] In some embodiments, the control interface of the frequency synthesizer 300 is a parallel interface.

[0085] Among them, the control interface of the frequency synthesizer 300 is the interface for the frequency synthesizer 300 to receive data. Compared with the current serial interface for data transmission, the parallel interface of the control interface can improve the data transmission speed and provide a basis for the rapid response of the signal source.

[0086] In some embodiments, the control interface of the frequency synthesizer 300 is modified from the Serial Peripheral Interface (SPI) to a parallel interface, which can increase the signal transmission rate by 8 times for a single register of the frequency synthesizer 300.

[0087] In some embodiments, a testing system is provided, comprising: The signal source as described in any of the above embodiments; The device under test; The host computer communicates with the signal source and the device under test respectively, and is used to send trigger signals to the signal source and the device under test. The trigger signals include a first rising edge, a first falling edge and a low-level signal of a first duration. Specifically, when the signal source detects a first rising edge, it configures a first test parameter; when it detects a first falling edge, it confirms that the first test parameter is effective; and when it detects that the duration of a low-level signal is greater than or equal to a first duration, it outputs a pulse signal corresponding to the first test parameter.

[0088] In this embodiment, such as Figure 7 As shown, the host computer can achieve synchronous control of the device under test and the signal source by outputting a trigger signal. Specifically, when the signal source detects the first rising edge, it configures the first test parameter; when it detects the first falling edge, it confirms that the first test parameter is effective; and when it detects that the duration of the low-level signal is greater than or equal to the first duration, it outputs a pulse signal corresponding to the first test parameter.

[0089] In this process, the signal source can output the corresponding parameter signal at the same time when the device to be tested needs to receive the signal.

[0090] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing examples, or make equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal source, characterized by, The signal source comprises a phase-locked loop and a controller connected with the phase-locked loop, and the controller is used for: acquiring a first test parameter, the first test parameter comprising a target output frequency; determining a target locking voltage corresponding to the target output frequency based on a mapping data table, the mapping data table comprising a plurality of mapping relationships, each of the mapping relationships comprising an output frequency and a locking voltage corresponding to the output frequency, and the output frequencies in different mapping relationships being different; adjusting an output voltage of a resistance voltage dividing network in the phase-locked loop to be the target locking voltage; modifying a working state of the phase-locked loop from a closed-loop state to an open-loop state, so that the resistance voltage dividing network outputs a voltage to a loop filter in the phase-locked loop; modifying the working state of the phase-locked loop from the open-loop state to the closed-loop state, so that a phase detector in the phase-locked loop outputs a voltage to the loop filter.

2. The signal source of claim 1, wherein, The phase-locked loop comprises: a first switch, a first input end of the first switch being connected with an output end of the resistance voltage dividing network, a second input end of the first switch being connected with an output end of the phase detector, and an output end of the first switch being connected with an input end of the loop filter; a voltage-controlled oscillator, an input end of the voltage-controlled oscillator being connected with an output end of the loop filter, and an output end of the voltage-controlled oscillator serving as an output end of the phase-locked loop; a radio frequency divider, an input end of the radio frequency divider being connected with the voltage-controlled oscillator, and an output end of the radio frequency divider being connected with a first input end of the phase detector; In the step of modifying the working state of the phase-locked loop from the closed-loop state to the open-loop state, so that the resistance voltage dividing network outputs a voltage to the loop filter in the phase-locked loop, the controller is specifically used for: controlling the first switch to perform a first action, so that the first input end of the first switch is in communication with the output end of the first switch; In the step of modifying the working state of the phase-locked loop from the open-loop state to the closed-loop state, so that the phase detector in the phase-locked loop outputs a voltage to the loop filter, the controller is specifically used for: controlling the first switch to perform a second action, so that the second input end of the first switch is in communication with the output end of the first switch.

3. The signal source of claim 2, wherein, In the step of determining the target locking voltage corresponding to the target output frequency based on the mapping data table, the controller is specifically used for: determining a first output frequency in the mapping data table that is closest to the target output frequency; taking a locking voltage corresponding to the first output frequency as the target locking voltage.

4. The signal source of claim 2, wherein, The signal source further comprises: a multiplexer; a frequency multiplier, an input end of the frequency multiplier being connected with an output end of the voltage-controlled oscillator, an output end of the frequency multiplier being connected with a first input end of the multiplexer, and the output end of the voltage-controlled oscillator being connected with a second input end of the multiplexer; a first frequency divider, an input end of the first frequency divider being connected with the output end of the voltage-controlled oscillator, and an output end of the first frequency divider being connected with a third input end of the multiplexer.

5. The signal source of claim 2, wherein, The signal source further comprises: a first voltage-controlled attenuator, an input terminal of the first voltage-controlled attenuator being connected with an output terminal of the phase-locked loop; a second voltage-controlled attenuator, an input terminal of the second voltage-controlled attenuator being connected with an output terminal of the first voltage-controlled attenuator; a mechanical attenuator, an input terminal of the mechanical attenuator being connected with an output terminal of the second voltage-controlled attenuator; a digital-to-analog converter, output terminals of the digital-to-analog converter being connected with control terminals of the first voltage-controlled attenuator and the second voltage-controlled attenuator respectively, an input terminal of the digital-to-analog converter being connected with the controller; the first test parameter further comprises a target output power, and the controller is further configured to: determine a target control voltage corresponding to the target output power based on a calibration data table, the calibration data table comprising a plurality of calibration data relationships, each of the calibration data relationships comprising an output power and a control voltage corresponding to the output power; control the digital-to-analog converter to output the target control voltage to the first voltage-controlled attenuator and the second voltage-controlled attenuator.

6. The signal source of claim 5, wherein, the mechanical attenuator has at least two signal output terminals, and signals output by different signal output terminals are the same.

7. The signal source of any one of claims 1 to 6, wherein, the controller is further configured to: obtain a test parameter list, the test parameter list comprising a plurality of test parameters, and the plurality of test parameters comprising a first test parameter; if a trigger signal is received during operation of the phase-locked loop according to the first test parameter, search for a second test parameter based on the test parameter list to control the phase-locked loop to operate according to the second test parameter; wherein the first test parameter and the second test parameter are adjacent test parameters.

8. The signal source of any one of claims 2 to 6, wherein, the signal source further comprises: a frequency synthesizer; the phase-locked loop further comprises: a reference frequency divider, an input terminal of the reference frequency divider being connected with an output terminal of the frequency synthesizer, and an output terminal of the reference frequency divider being connected with a second input terminal of the phase detector.

9. The signal source of claim 8, wherein, the control interface of the frequency synthesizer is a parallel interface.

10. A test system, characterized by comprise: the signal source according to any one of claims 1 to 9; a device to be tested; a host computer, in communication with the signal source and the device to be tested respectively, configured to send a trigger signal to the signal source and the device to be tested, the trigger signal comprising a first rising edge, a first falling edge and a first low-level signal with a first time length; wherein the signal source is configured to configure the first test parameter upon detection of the first rising edge, confirm the first test parameter takes effect upon detection of the first falling edge, and output a pulse signal corresponding to the first test parameter upon detection that the duration of the low-level signal is greater than or equal to the first time length.

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