High-precision synchronization method and system for distributed power system
By adopting a high-precision synchronization mechanism with a CPU+FPGA architecture in the distributed power system, the problems of high synchronization resource consumption and high construction complexity in the existing technology have been solved, achieving extremely high synchronization accuracy and anti-interference capability, and reducing cost and construction difficulty.
Patent Information
- Application Number
- CN202511541313.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-01-30
AI Technical Summary
Existing distributed power system synchronization methods suffer from high resource consumption, high cost, and high construction complexity in achieving high-precision synchronization. In particular, they can easily lead to misjudgment of faults or delayed response of protection devices in new energy power plants, affecting power grid security.
Adopting a CPU+FPGA architecture, a high-precision synchronization mechanism is implemented within the FPGA. By performing synchronization compensation time and error calculation within each message transmission cycle, the synchronization cycle is adaptively adjusted to reduce network overhead and achieve extremely high synchronization accuracy and anti-interference capability.
It achieves extremely high synchronization accuracy without consuming processor resources or affecting business operations, reducing the construction complexity and cost of synchronization design, and has high engineering application value.
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Figure CN121440913A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power systems, in particular to a high-precision synchronization method and system for distributed power systems. BACKGROUND
[0002] Under the background of the evolution of power systems to high penetration of new energy and complex grid forms, the distributed master-slave architecture has become a core technical solution to ensure the reliable operation of key equipment. Among them, the stability control device for new energy stations and the distributed bus protection device covering multiple intervals are directly related to the "nerve endings" of grid safety and stability. The architecture design and synchronization performance of such systems not only determine the control accuracy of the equipment itself, but also deeply affect the fault response speed and risk resistance ability of the regional power grid.
[0003] The reliable operation of the system is highly dependent on the high-precision synchronization between the master and slave machines. From the effectiveness of the measurement data, the analog quantities (such as bus branch currents) collected by different slave machines need to be integrated and calculated based on a unified time reference. For example, when the distributed bus protection device judges whether a short-circuit fault has occurred on the bus, it needs to compare the phase difference and amplitude relationship of the branch currents. If the synchronization deviation between the slave machines exceeds 1 μs, the current phase calculation error will exceed 0.18° (calculated at a power frequency of 50 Hz), which may lead to misjudgment of the fault branch or missed judgment of the fault, causing protection refusal or misoperation; from the control strategy execution, the stability control device of the new energy station needs to dynamically adjust the power distribution scheme according to the dispersed power output data collected by each slave machine. If there is a time deviation in the slave machine data, it will cause the calculated value of the master machine for the total output of the station to deviate from the actual value by more than 0.5%. When the deviation accumulates to a certain extent, it may trigger the "excessive protection" of the grid dispatching system, forcing the station to reduce output or even shut down, resulting in loss of new energy generation. More seriously, in the event of a short-circuit fault in the grid, insufficient synchronization accuracy will cause the master machine to be unable to accurately determine the fault occurrence time and fault location, causing the delay of the protection device trip command to exceed 20 ms, missing the "golden time" of fault removal, and thus causing the expansion of the fault, even causing regional grid collapse. Therefore, in the secondary equipment of the power system, if the synchronization accuracy is large, the data of different slave machines is difficult to unify, which may cause the stability control to stop running and other serious consequences.
[0004] The existing distributed system synchronization is mainly realized through two ways: (1) the time and business co-network transmission mode. This mode generally adopts PTP protocol, adopts fixed cycle transmission of time message, in order to achieve high precision synchronization effect, the synchronization cycle is generally small interval, not only occupies higher transmission bandwidth, affects the transmission efficiency of business message, but also occupies higher processor resources. For example, the technical solutions of CN118353568A and CN120474656A two patents adopt mature PTP mode to realize network message synchronization, this method is suitable for the distributed system which exists in the switching network and the network message delay exists high uncertainty, this method can realize higher time accuracy, but occupies higher communication resources, must adopt the special protocol and special chip based on IEEE1588, the realization method is more complex, the cost is higher, and it is not suitable for the direct power system which directly adopts point-to-point interconnection of high reliability network. (2) independent synchronization time fiber realizes the synchronization of distributed system. But this way makes the function of distributed system depend on the time fiber, the reliability is obviously reduced, on the other hand, in the new energy field, the number of sub machines is large, the huge time fiber will greatly increase the construction complexity of the field. SUMMARY
[0005] The purpose of the application is to provide a high-precision synchronization method and system for a distributed power system, which can realize high synchronization precision with extremely low network overhead without processor sensing, and reduce the construction complexity and cost of the distributed system synchronization design.
[0006] The technical scheme of the application is a high-precision synchronization method for a distributed power system, which comprises a host and a plurality of sub machines interconnected with the host in point-to-point mode to be synchronized; the host and the sub machines both adopt CPU+FPGA architecture, and the high-precision synchronization mechanism is realized in the FPGA.
[0007] The high-precision synchronization mechanism is that the host sends a synchronization request message to the sub machines to be synchronized in each message sending cycle, the sub machines update the local time information according to the synchronization compensation time and calculate the synchronization error after receiving the synchronization request message, and the implementation steps of the high-precision synchronization mechanism include:
[0008] Step 1: in the first message sending cycle, set the initial synchronization compensation time and the initial synchronization error;
[0009] Step 2: in the second message sending cycle, set the first synchronization compensation time, and calculate the first synchronization error according to the host local time and the sub machine local time;
[0010] Step 3: in the third message sending cycle, calculate the second synchronization compensation time according to the first synchronization error, and calculate the second synchronization error according to the host local time and the sub machine local time;
[0011] Step 4, if the second synchronization error is less than the minimum requirement of the synchronization error, then re-perform step 3 after adjusting the interval step, calculate the second synchronization error, until the second synchronization error is in a reasonable range;
[0012] If the second synchronization error is greater than the maximum requirement of the synchronization error, then re-perform steps 1 to 4.
[0013] Further, the high-precision synchronization mechanism divides the packet sending process into packet sending periods at fixed intervals, and the packet sending period is divided into a synchronization packet time slot and an application packet time slot.
[0014] In the synchronization packet time slot of each packet sending period, the host sends a synchronization request packet to the to-be-synchronized slave.
[0015] Further, the host sends a synchronization request packet to the to-be-synchronized slave, and the synchronization request packet at least contains the packet type, the host local time, and the synchronization compensation time.
[0016] Further, after receiving the synchronization request packet, the slave updates the local time information according to the synchronization compensation time, and immediately sends a synchronization response packet, and the synchronization response packet at least contains the packet type, the slave local actual, and the synchronization error.
[0017] Further, in the second packet sending period, the first synchronization error = - ; wherein is the host local time of the second packet sending period, is the slave local time of the second packet sending period
[0018] In the third packet sending period, the second synchronization error = - ; wherein is the host local time of the third packet sending period, is the slave local time of the third packet sending period; and the second synchronization compensation time .
[0019] Further, the reasonable range of the synchronization error is , , is the set value, is the minimum requirement of the synchronization error, is the maximum requirement of the synchronization error.
[0020] Based on the same inventive concept, the high-precision synchronization method of the distributed power system comprises a host and a plurality of sub-machines to be synchronized which are interconnected with the host in a point-to-point manner; the host and the sub-machines both adopt a CPU+FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA.
[0021] The implementation steps of the high-precision synchronization mechanism comprise:
[0022] Step 1: in a first message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and sets an initial synchronization compensation time; after receiving the synchronization request message, the sub-machines update local time information according to the initial synchronization compensation time, and set an initial synchronization error.
[0023] Step 2: in a second message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and sets an initial synchronization compensation time; after receiving the synchronization request message, the sub-machines update local time information according to the initial synchronization compensation time, and calculate a first synchronization error according to the host local time and the sub-machine local time.
[0024] Step 3: in a third message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and calculates a second synchronization compensation time according to the first synchronization error; after receiving the synchronization request message, the sub-machines update local time information according to the first synchronization compensation time, and calculate a second synchronization error according to the host local time and the sub-machine local time.
[0025] Step 4: the host adjusts according to the second synchronization error; if the second synchronization error is less than a minimum requirement of the synchronization error, the step 3 is re-executed after an interval adjustment step, the second synchronization error is calculated, and the second synchronization error is located in a reasonable range until the second synchronization error is located in the reasonable range.
[0026] If the second synchronization error is greater than a maximum requirement of the synchronization error, the steps 1 to 4 are re-executed.
[0027] Further, the high-precision synchronization mechanism divides a message sending process into message sending periods at fixed intervals, and the message sending periods are divided into synchronization message time slots and application message time slots.
[0028] In the synchronization message time slot of each message sending period, the host sends a synchronization request message to the sub-machines to be synchronized.
[0029] Further, the host sends a synchronization request message to the sub-machines to be synchronized, and the synchronization request message at least comprises a message type, a host local time and a synchronization compensation time.
[0030] Further, after receiving the synchronization request message, the sub-machines update local time information according to the synchronization compensation time, and immediately send a synchronization response message, and the synchronization response message at least comprises a message type, a sub-machine local actual time and a synchronization error.
[0031] Further, in the second message sending period, the first synchronization error = - ; wherein is the host local time of the second message sending period, is the slave local time of the second message sending period
[0032] In the third message sending period, the second synchronization error = - ; wherein is the host local time of the third message sending period, is the slave local time of the third message sending period; the second synchronization compensation time .
[0033] Further, the reasonable range of the synchronization error is , , is the setting value, is the lowest requirement of the synchronization error, is the highest requirement of the synchronization error.
[0034] Based on the same inventive concept, the high-precision synchronization system of the distributed power system provided by the present application comprises: the distributed power system comprises a host and a plurality of slaves to be synchronized which are interconnected with the host in point-to-point mode; the host and the slaves both adopt the CPU+FPGA architecture, and the high-precision synchronization mechanism is realized in the FPGA.
[0035] The high-precision synchronization mechanism, in each message sending period, the host sends a synchronization request message to the slaves to be synchronized, and the slaves update the local time information according to the synchronization compensation time and calculate the synchronization error after receiving the synchronization request message; the high-precision synchronization mechanism is realized through the following modules.
[0036] The initial setting module, in the first message sending period, sets the initial synchronization compensation time and the initial synchronization error.
[0037] The synchronization adjustment module, in the second message sending period, sets the first synchronization compensation time and calculates the first synchronization error according to the host local time and the slave local time; in the third message sending period, calculates the second synchronization compensation time according to the first synchronization error and calculates the second synchronization error according to the host local time and the slave local time; if the second synchronization error is less than the lowest requirement of the synchronization error, the content of the third message sending period is re-executed after an interval adjustment step, the second synchronization error is calculated, until the second synchronization error is in the reasonable range; if the second synchronization error is greater than the highest requirement of the synchronization error, the initial setting module is returned.
[0038] Further, the high-precision synchronization mechanism divides the message sending process into message sending periods at fixed intervals, and the message sending period is divided into a synchronization message time slot and an application message time slot.
[0039] In the synchronization message time slot of each message sending period, the host sends a synchronization request message to the to-be-synchronized slave.
[0040] Further, the host sends a synchronization request message to the to-be-synchronized slave, and the synchronization request message at least contains a message type, a host local time and a synchronization compensation time.
[0041] Further, after receiving the synchronization request message, the slave updates the local time information according to the synchronization compensation time, and immediately sends a synchronization response message, and the synchronization response message at least contains a message type, a slave local actual and a synchronization error.
[0042] Further, in the synchronization adjustment module, in the second message sending period, the first synchronization error = - ; wherein is the host local time of the second message sending period, is the slave local time of the second message sending period
[0043] In the third message sending period, the second synchronization error = - ; wherein is the host local time of the third message sending period, is the slave local time of the third message sending period; and the second synchronization compensation time .
[0044] Further, in the synchronization adjustment module, the reasonable range of the synchronization error is , , is a set value, is the lowest requirement of the synchronization error, is the highest requirement of the synchronization error.
[0045] Based on the same inventive concept, the computer readable storage medium of the application stores a computer program, and the computer program is executed by a processor to realize the high-precision synchronization method of the distributed power system.
[0046] Based on the same inventive concept, the computer program product of the application comprises a computer program, and the computer program is executed by a processor to realize the high-precision synchronization method of the distributed power system.
[0047] Beneficial effects: compared with the prior art, the advantages of the present application are: the present application is based on FPGA implementation, which realizes multi-machine synchronization in distributed architecture power secondary equipment through single-channel service communication link under the premise of no influence on processor resource consumption and service operation, realizes extremely high synchronization precision through extremely low network overhead occupation; the present application has extremely high precision synchronization effect and strong anti-interference ability through adaptive synchronization period adjustment, basically has no influence on normal service transmission; the present application reduces the complexity and cost of distributed system synchronization design construction, has high engineering application value. BRIEF DESCRIPTION OF DRAWINGS
[0048] Figure 1 It is a synchronization system architecture diagram in embodiment 3 of the present application.
[0049] Figure 2 It is a synchronization message format schematic diagram of embodiment 3 of the present application.
[0050] Figure 3 It is a high-precision synchronization mechanism implementation process schematic diagram of embodiment 3 of the present application.
[0051] Figure 4 It is a high-precision synchronization mechanism implementation flowchart of embodiment 3 of the present application. DETAILED DESCRIPTION
[0052] The technical solutions of the present application will be further described below in combination with the drawings.
[0053] Embodiment 1
[0054] The high-precision synchronization method of the distributed power system described in this embodiment, the distributed power system includes a host computer and a plurality of sub-computers to be synchronized interconnected with the host computer in point-to-point mode; the host computer and the sub-computers both adopt CPU+FPGA architecture, and the high-precision synchronization mechanism is realized in the FPGA;
[0055] The high-precision synchronization mechanism is that, in each message sending period, the host computer sends a synchronization request message to the sub-computers to be synchronized, the sub-computers update local time information and calculate synchronization error according to the synchronization compensation time after receiving the synchronization request message, and the implementation steps of the high-precision synchronization mechanism include:
[0056] Step 1.1, in the first message sending period, set the initial synchronization compensation time and the initial synchronization error;
[0057] Step 1.2, in the second message sending period, set the first synchronization compensation time, and calculate the first synchronization error according to the host computer local time and the sub-computer local time;
[0058] Step 1.3, in the third message sending period, a second synchronization compensation time is calculated according to the first synchronization error, and a second synchronization error is calculated according to the host local time and the slave local time;
[0059] Step 1.4, if the second synchronization error is less than the minimum requirement of the synchronization error, step 1.3 is re-executed after interval adjustment step, the second synchronization error is calculated until the second synchronization error is in a reasonable range;
[0060] If the second synchronization error is greater than the maximum requirement of the synchronization error, steps 1.1 to 1.4 are re-executed.
[0061] Embodiment 2
[0062] The high-precision synchronization method of the distributed power system described in this embodiment includes a host and a plurality of slaves to be synchronized which are interconnected with the host in point-to-point mode; the host and the slave both adopt CPU+FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA;
[0063] The implementation steps of the high-precision synchronization mechanism include:
[0064] Step 2.1, in the first message sending period, the host sends a synchronization request message to the slave to be synchronized, and sets an initial synchronization compensation time; after receiving the synchronization request message, the slave updates the local time information according to the initial synchronization compensation time, and sets an initial synchronization error;
[0065] Step 2.2, in the second message sending period, the host sends a synchronization request message to the slave to be synchronized, and sets an initial synchronization compensation time; after receiving the synchronization request message, the slave updates the local time information according to the initial synchronization compensation time, and calculates a first synchronization error according to the host local time and the slave local time;
[0066] Step 2.3, in the third message sending period, the host sends a synchronization request message to the slave to be synchronized, and calculates a second synchronization compensation time according to the first synchronization error; after receiving the synchronization request message, the slave updates the local time information according to the first synchronization compensation time, and calculates a second synchronization error according to the host local time and the slave local time;
[0067] Step 2.4, the host adjusts according to the second synchronization error, if the second synchronization error is less than the minimum requirement of the synchronization error, step 2.3 is re-executed after interval adjustment step, the second synchronization error is calculated until the second synchronization error is in a reasonable range;
[0068] If the second synchronization error is greater than the maximum requirement of the synchronization error, steps 2.1 to 2.4 are re-executed.
[0069] Embodiment 3
[0070] In this embodiment, the synchronization system architecture of the high-precision synchronization method for distributed power systems is as follows: Figure 1 As shown in the diagram, the synchronization system architecture includes a host machine and multiple sub-machines interconnected point-to-point for synchronization. The host machine and the sub-machines communicate through a single bidirectional communication channel using a high-precision synchronization mechanism to achieve shared network transmission of synchronization messages and service messages.
[0071] Both the host and slave adopt a CPU+FPGA architecture, where the generation and processing of synchronization messages are implemented inside the FPGA; the host time information is obtained by the host through timing signals or its own timekeeping information; the slave time information is obtained by the slave FPGA by parsing the synchronization messages sent by the host or through timekeeping.
[0072] Synchronization message reference format as follows Figure 2 As shown, the messages are divided into synchronization request messages and synchronization response messages. A synchronization request message must include at least the message type, local timestamp information, and synchronization compensation time; a synchronization response message must include at least the message type, slave timestamp information, and synchronization error.
[0073] High-precision synchronization mechanisms are applied in the real-time domain of power systems, dividing the message transmission process into transmission cycles at fixed intervals. Each cycle is divided into synchronization message time slots. Application message slots .
[0074] The high-precision synchronization mechanism mentioned above is as follows: Figure 3 and Figure 4 As shown, the steps include the following.
[0075] Step 3.1: In the initial stage, within the fixed synchronization message time slot of the first message sending cycle, the host FPGA sends a message to the slave device to be synchronized. Send a synchronization request message. The time delay between the synchronization message slot and the message sending period is fixed and optional, and is a configurable option.
[0076] The time information in the synchronization request message is the host's local time information. ;
[0077] The initial synchronization compensation time in the synchronization request message is set to , It can be set based on experience values;
[0078] The number of slave devices to be synchronized is optional and shall not exceed [number]. .
[0079] Step 3.2, Synchronization slave machine Within the first transmission cycle, after receiving the synchronization request message, according to... Update the local time information and immediately send a synchronization response message.
[0080] The time information in the synchronization response message is the local time information of the slave ;
[0081] The synchronization error in the synchronization response message is set to 0.
[0082] Step 3.3. The host FPGA sends a synchronization request message to the slave to be synchronized in a fixed time slot of the second message sending period. The fixed time slot is fixed in time delay of the message sending period, and is optionally a configurable item. The time information in the synchronization request message is the local time information of the host
[0083] ; The synchronization compensation time in the synchronization request message is initially set to
[0084] , , which can be set according to an empirical value.
[0085] Step 3.4. The slave to be synchronized updates the local time information according to the synchronization request message received in the second sending period, and immediately sends a synchronization response message. The time information in the synchronization response message is the local time information of the slave maintained before
[0086] ; The synchronization error in the synchronization response message is
[0087] = - 0. .
[0088] Step 3.5. The host FPGA sends a synchronization request type message to the slave to be synchronized in a fixed time slot of the third message sending period. The fixed time slot is fixed in time delay of the message sending period, and is optionally a configurable item. The time information in the synchronization request type message is the local time information of the host
[0089] ; The synchronization compensation time in the synchronization request type message is initially set to
[0090] , . Step 3.6. The slave to be synchronized
[0091] updates the local time information according to the synchronization request message received in the third sending period, and immediately sends a synchronization response message. The time information in the synchronization response message is the local time information of the slave maintained before ;
[0092] The time information in the synchronization response message is used to maintain the local time information of the slave ;
[0093] The synchronization error in the synchronization response message is = - .
[0094] Step 3.7, the master receives the synchronization request message from the slave After receiving the synchronization response message, the synchronization error is judged, and if the synchronization error is less than the minimum requirement of the synchronization error , the sending of the synchronization request message is stopped, and the adjustment step is increased , and then the synchronization request message is sent again, i.e., the synchronization adjustment is performed again after an interval of time.
[0095] The increase value of the adjustment step is a set value.
[0096] Step 3.8, steps 3.5-3.6 are repeated, and the synchronization error is judged again, and if the conditions are met, the sending of the synchronization message is stopped, and the adjustment step is further increased , and then the synchronization request message is sent again, and steps 3.5-3.6 are repeated until the adjustment step is , and the synchronization error is within a reasonable range, the master-slave synchronization period is set to , and the master-slave synchronization is performed according to .
[0097] The increase value of the adjustment step is a set value;
[0098] The reasonable range of the synchronization error is: , the minimum requirement of the synchronization error , the maximum requirement of the synchronization error , a set value.
[0099] Step 3.9, once the master receives the synchronization error in the synchronization response message that exceeds the maximum requirement of the synchronization error, steps 3.1-3.8 are repeated immediately.
[0100] Embodiment 4
[0101] This embodiment verifies the high-precision synchronization method of the distributed power system described in embodiments 1-3 through specific examples.
[0102] The distributed system defined in the present example comprises one host and 32 slaves, both the host and the slaves adopt a "CPU+FPGA" architecture, and the architecture is as shown in Figure 1 .
[0103] The message structure is as shown in Figure 2 , wherein the message type occupies 2 bytes, the channel information occupies 2 bytes, the synchronization technology occupies 4 bytes, the synchronization request message is 0X8001, the synchronization response message is fixed as 0X8002, the time scale information occupies 4 bytes, the century-second format, the synchronization compensation time and the synchronization error each occupy 4 bytes, the CRC information occupies 4 bytes, and the total message length is 20 bytes.
[0104] The high-precision synchronization mechanism is implemented based on FPGA, and the following is a specific method for the synchronization between the host and the first slave: the high-precision synchronization mechanism is used to send messages at a fixed interval of 100us as a fixed sending period, and each period is divided into a synchronization message time slot of 20us and an application message time slot of 80us. The sending period can be reduced to 100ms once by the following method, the service message bandwidth is increased from 80Mbps to close to 100Mbps, and the time synchronization accuracy of about 200ns is realized. The specific method is as follows:
[0105] Step 4.1. In the fixed time slot of the first message sending period, the host FPGA sends a synchronization request message to the slave to be synchronized. The initial synchronization compensation time is set to 1us.
[0106] Step 4.2. In the first sending period, the slave to be synchronized receives the synchronization request message and updates the local time information, and immediately sends a synchronization response message, and the synchronization error in the synchronization response message is set to 0.
[0107] Step 4.3. In the fixed time slot of the second message sending period, the host FPGA sends a synchronization request message to the slave to be synchronized. The initial synchronization compensation time is set to 1us.
[0108] Step 4.4. In the second sending period, the slave to be synchronized receives the synchronization request message and updates the local time information, and immediately sends a synchronization response message, and the synchronization error in the synchronization response message is = - .
[0109] Step 4.5. In the fixed time slot of the third message sending period, the host FPGA sends a synchronization request message to the slave to be synchronized. The initial synchronization compensation time in the synchronization request message is , wherein .
[0110] Step 4.6: Upon receiving the synchronization request message and updating its local time information within the third transmission cycle, the synchronization slave device immediately sends a synchronization response message; the synchronization error in the synchronization response message is... = - .
[0111] Step 4.7: After the host receives the synchronization response message, the slave device to be synchronized judges the synchronization error. At this time, the synchronization error... If the value is 10ns, and it falls within the reasonable range of 100ns to 200ns, then the synchronization message will be stopped, and the synchronization request message will be sent again after the adjustment step size is 200us.
[0112] Step 4.8: Repeat steps 4.5-4.6, and re-evaluate the synchronization error. If the condition is met, continue to stop sending synchronization messages, further increase the adjustment step size to 400µs, resend the synchronization request message, and repeat steps 4.5-4.6. When the adjustment step size is 100ms, the synchronization error... It takes about 200ns, at which point the master-slave synchronization period is set to 100ms.
[0113] Step 4.9: Once the synchronization error in the synchronization response message received by the host exceeds the maximum synchronization error requirement, steps 4.1 to 4.6 are immediately repeated.
[0114] Example 4
[0115] The high-precision synchronization system for a distributed power system described in this embodiment includes: a distributed power system comprising a host and several slave units interconnected point-to-point with the host for synchronization; both the host and slave units adopt a CPU+FPGA architecture, and the high-precision synchronization mechanism is implemented inside the FPGA;
[0116] The high-precision synchronization mechanism involves the host sending a synchronization request message to the slave device to be synchronized within each message transmission cycle. After receiving the synchronization request message, the slave device updates its local time information according to the synchronization compensation time and calculates the synchronization error. The high-precision synchronization mechanism is implemented through the following modules:
[0117] The initial setup module sets the initial synchronization compensation time and initial synchronization error during the first message transmission period;
[0118] The synchronous adjustment module sets a first synchronization compensation time in the second message sending period, calculates a first synchronization error according to the host local time and the slave local time; calculates a second synchronization compensation time according to the first synchronization error in the third message sending period, calculates a second synchronization error according to the host local time and the slave local time; if the second synchronization error is less than a lowest requirement of the synchronization error, re-executes the content of the third message sending period after an interval adjustment step, calculates the second synchronization error until the second synchronization error is in a reasonable range; if the second synchronization error is greater than a highest requirement of the synchronization error, returns to the initial setting module.
[0119] Embodiment 5
[0120] The computer readable storage medium described in the embodiment stores a computer program, and the computer program is executed by a processor to implement the high-precision synchronization method of the distributed power system.
[0121] The computer readable storage medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory or any other medium that can be used to store program codes in the form of instructions or data structures and can be accessed by a computer.
[0122] The processor is used to execute the computer program stored in the memory to implement each step in the method involved in the above-mentioned embodiments.
[0123] Embodiment 6
[0124] The computer program product described in the embodiment includes a computer program, and the computer program is executed by a processor to implement the high-precision synchronization method of the distributed power system.
Claims
1. A high-precision synchronization method for a distributed power system, characterized by, The distributed power system comprises a host and a plurality of sub-machines to be synchronized in point-to-point interconnection with the host; the host and the sub-machines both adopt a CPU+FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA; The high-precision synchronization mechanism is that, in each message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and the sub-machines update local time information according to a synchronization compensation time and calculate a synchronization error after receiving the synchronization request message; the implementation steps of the high-precision synchronization mechanism comprise: Step 1, in a first message sending period, an initial synchronization compensation time and an initial synchronization error are set; Step 2, in a second message sending period, a first synchronization compensation time is set, and a first synchronization error is calculated according to the host local time and the sub-machine local time; Step 3, in a third message sending period, a second synchronization compensation time is calculated according to the first synchronization error, and a second synchronization error is calculated according to the host local time and the sub-machine local time; Step 4, if the second synchronization error is less than a minimum requirement of the synchronization error, step 3 is re-executed after an interval adjustment step to calculate the second synchronization error until the second synchronization error is in a reasonable range; If the second synchronization error is greater than a maximum requirement of the synchronization error, steps 1 to 4 are re-executed.
2. The method of claim 1, wherein, The high-precision synchronization mechanism divides a message sending process into message sending periods at fixed intervals, and the message sending period is divided into a synchronization message time slot and an application message time slot; In the synchronization message time slot of each message sending period, the host sends a synchronization request message to the sub-machines to be synchronized.
3. The method of claim 1, wherein, The synchronization request message sent by the host to the sub-machines to be synchronized at least comprises a message type, a host local time and a synchronization compensation time.
4. The method of claim 1, wherein, After receiving the synchronization request message, the sub-machines update local time information according to the synchronization compensation time and immediately send a synchronization response message, which at least comprises a message type, a sub-machine local actual time and a synchronization error.
5. The method of claim 1, wherein, In the second message sending period, the first synchronization error = - ; wherein is the host local time of the second message sending period, is the slave local time of the second message sending period In the third message sending period, the second synchronization error = - ; wherein is the host local time of the third message sending period, is the slave local time of the third message sending period; Second synchronization compensation time .
6. The method of claim 1, wherein, The reasonable range of synchronization error is , , is the set value, is the lowest requirement of synchronization error, is the highest requirement of synchronization error.
7. A high-precision synchronization method for a distributed power system, characterized by, The distributed power system comprises a host and a plurality of sub-machines to be synchronized in point-to-point interconnection with the host; the host and the sub-machines both adopt a CPU+FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA; The implementation steps of the high-precision synchronization mechanism comprise: Step 1, in a first message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and an initial synchronization compensation time is set; after receiving the synchronization request message, the sub-machines update local time information according to the initial synchronization compensation time and set an initial synchronization error; Step 2, in a second message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and an initial synchronization compensation time is set; after receiving the synchronization request message, the sub-machines update local time information according to the initial synchronization compensation time and calculate a first synchronization error according to the host local time and the sub-machine local time; Step 3, in a third message sending period, the host sends a synchronization request message to the sub-machines to be synchronized, and a second synchronization compensation time is calculated according to the first synchronization error; after receiving the synchronization request message, the sub-machines update local time information according to the first synchronization compensation time and calculate a second synchronization error according to the host local time and the sub-machine local time; Step 4, the host adjusts according to the second synchronization error, if the second synchronization error is less than the lowest requirement of the synchronization error, then the step 3 is re-executed after interval adjustment step, the second synchronization error is calculated until the second synchronization error is in a reasonable range; If the second synchronization error is greater than the highest requirement of the synchronization error, then the steps 1 to 4 are re-executed.
8. The high-precision synchronization method for distributed power systems according to claim 7, characterized in that, The high-precision synchronization mechanism divides the packet sending process into packet sending periods according to fixed intervals, and the packet sending period is divided into a synchronization packet time slot and an application packet time slot. In the synchronization packet time slot of each packet sending period, the host sends a synchronization request packet to the to-be-synchronized slave.
9. The method of claim 7, wherein the step of determining the phase angle of the voltage of the power source comprises the steps of: determining the phase angle of the voltage of the power source by using a phase lock loop (PLL) circuit. The host sends a synchronization request packet to the to-be-synchronized slave, and the synchronization request packet at least contains a packet type, a host local time and a synchronization compensation time.
10. The method of claim 7, wherein, After receiving the synchronization request packet, the slave updates the local time information according to the synchronization compensation time and calculates a synchronization error, and immediately sends a synchronization response packet, and the synchronization response packet at least contains a packet type, a slave local actual and a synchronization error.
11. The method of claim 7, wherein, In the second message sending period, the first synchronization error = - ; wherein is the host local time of the second message sending period, is the slave local time of the second message sending period In the third message sending period, the second synchronization error = - ; wherein is the host local time of the third message sending period, is the slave local time of the third message sending period; Second synchronization compensation time .
12. The method of claim 7, wherein, The reasonable range of synchronization error is , , is the set value, is the lowest requirement of synchronization error, is the highest requirement of synchronization error.
13. A high-precision synchronization system for a distributed power system, characterized by It comprises: The distributed power system comprises a host and a plurality of to-be-synchronized slaves interconnected with the host in a point-to-point manner; the host and the slaves both adopt a CPU+FPGA architecture, and a high-precision synchronization mechanism is realized in the FPGA; In each packet sending period, the host sends a synchronization request packet to the to-be-synchronized slave, and the slave receives the synchronization request packet, updates the local time information according to the synchronization compensation time and calculates a synchronization error; the high-precision synchronization mechanism is realized through the following modules: An initial setting module sets an initial synchronization compensation time and an initial synchronization error in a first packet sending period; A synchronization adjustment module sets a first synchronization compensation time in a second packet sending period, calculates a first synchronization error according to the host local time and the slave local time, calculates a second synchronization compensation time according to the first synchronization error in a third packet sending period, calculates a second synchronization error according to the host local time and the slave local time, re-executes the content of the third packet sending period after an interval adjustment step to calculate the second synchronization error until the second synchronization error is in a reasonable range if the second synchronization error is less than the lowest requirement of the synchronization error, and returns to the initial setting module if the second synchronization error is greater than the highest requirement of the synchronization error.
14. The high-precision synchronization system of a distributed power system according to claim 13, characterized in that, The high-precision synchronization mechanism divides the packet sending process into packet sending periods according to fixed intervals, and the packet sending period is divided into a synchronization packet time slot and an application packet time slot. In the synchronization packet time slot of each packet sending period, the host sends a synchronization request packet to the to-be-synchronized slave.
15. The high-precision synchronization system of a distributed power system according to claim 13, characterized by, The host sends a synchronization request packet to the to-be-synchronized slave, and the synchronization request packet at least contains a packet type, a host local time and a synchronization compensation time.
16. The high-precision synchronization system of a distributed power system according to claim 13, characterized by, After receiving the synchronization request packet, the slave updates the local time information according to the synchronization compensation time and calculates a synchronization error, and immediately sends a synchronization response packet, and the synchronization response packet at least contains a packet type, a slave local actual and a synchronization error.
17. The high-precision synchronization system of a distributed power system of claim 13, wherein, In the synchronous adjustment module, in the second message sending period, the first synchronization error = - ; wherein is the host local time of the second message sending period, is the slave local time of the second message sending period In the third message sending period, the second synchronization error = - ; wherein is the host local time of the third message sending period, is the slave local time of the third message sending period; Second synchronization compensation time .
18. The high-precision synchronization system of a distributed power system of claim 13, wherein, In the synchronization regulation module, the reasonable range of the synchronization error is , 、 is the set value, is the lowest requirement of the synchronization error, is the highest requirement of the synchronization error.
19. A computer-readable storage medium, the computer-readable storage medium storing a computer program, characterized in that, The computer program is executed by the processor to realize the high-precision synchronization method of the distributed power system according to any one of claims 1-12.
20. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the high-precision synchronization method of the distributed power system according to any one of claims 1-12.
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