Wafer-level packaging atlas processing method and system

Abstract

The invention provides a wafer-level packaging atlas processing method and system, and belongs to the technical field of semiconductors, and the method comprises the steps: uploading a received incoming material atlas to a specified file server based on a client code and an atlas type, binding the received incoming material atlas with a wafer batch, and converting the bound incoming material atlas into an internal atlas; generating an internal atlas number based on the client code, the process flow, the atlas format and the site name of the internal atlas; according to the yield requirement, determining the yield standard threshold of the associated wafer of the internal atlas, and performing associated storage with the internal atlas number; performing optical detection and electrical test on the associated wafer to obtain a detection atlas, comparing the detection atlas with the reference atlas, counting the defect condition of the chip unit of the associated wafer based on the comparison result, and calculating to obtain the wafer yield and the batch yield; and judging the wafer yield and the batch yield with a wafer yield standard-reaching threshold value and a batch yield standard-reaching threshold value in the yield standard-reaching threshold values respectively to obtain judgment results. According to the invention, the accuracy and traceability of wafer yield judgment are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a wafer-level packaging pattern processing method and system. Background Technology

[0002] As chip manufacturing processes continue to shrink, incoming material maps, as key data reflecting the characteristics of raw materials, directly impact the stability of subsequent production processes through their standardized storage, accurate correlation, and interpretation. In traditional models, incoming material maps are loosely linked to wafer batches, and inconsistent numbering rules lead to difficulties in data traceability. Furthermore, yield threshold settings lack alignment with map attributes, easily causing deviations in testing standards. Simultaneously, wafer manufacturing involves multiple sites and processes, resulting in large volumes and complex dimensions of optical and electrical testing data. Manually comparing baseline and test maps is inefficient, leading to high defect statistical errors and failing to meet the real-time yield control requirements of large-scale production.

[0003] Therefore, there is an urgent need for a wafer-level packaging pattern processing method and system. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a wafer-level packaging pattern processing method and system.

[0005] A first aspect of this application provides a wafer-level packaging pattern processing method, including: The system receives incoming material patterns from customers and uploads them to a designated file server based on the customer code and pattern type. Simultaneously, the incoming material patterns are bound to wafer batches and converted into internal patterns. Based on the customer code, process flow, map format, and site name of the internal map, an internal map number is generated. Based on the yield requirements, determine the yield threshold of the associated wafer of the internal pattern, and store the yield threshold in association with the internal pattern number; Optical and electrical tests were performed on the associated wafer to obtain a detection spectrum; The baseline spectrum is compared with the detected spectrum to obtain the comparison result; Based on the comparison results, the chip cell defect situation of the associated wafer is statistically analyzed, and the wafer yield and batch yield are calculated. The wafer yield and batch yield are compared with the wafer yield threshold and batch yield threshold in the yield compliance threshold, respectively, to obtain the judgment result, and report data corresponding to the internal map number is generated.

[0006] A second aspect of this application provides a wafer-level packaging pattern processing system, comprising: The pattern receiving and conversion module is used to receive incoming material patterns input by customers, and upload them to a designated file server based on customer codes and pattern types; at the same time, the incoming material patterns are bound to wafer batches and converted into internal patterns; based on the customer codes, process flows, pattern formats and site names of the internal patterns, an internal pattern number is generated. The standard yield setting module is used to determine the yield compliance threshold of the associated wafer of the internal pattern according to the yield requirements, and to associate and store the yield compliance threshold with the internal pattern number. The detection pattern generation module is used to perform optical detection and electrical testing on the associated wafer to obtain a detection pattern. The detection spectrum comparison module is used to compare the reference spectrum with the detection spectrum to obtain the comparison result; The actual yield calculation module is used to calculate the wafer yield and batch yield based on the comparison results, by statistically analyzing the chip unit defects of the associated wafer. The report data generation module is used to compare the wafer yield and batch yield with the wafer yield compliance threshold and batch yield compliance threshold in the yield compliance threshold, respectively, to obtain the judgment result and generate report data corresponding to the internal map number.

[0007] A third aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the wafer-level packaging pattern processing method described above.

[0008] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the wafer-level packaging pattern processing system described above. The beneficial effects of the wafer-level packaging pattern processing method and system provided by this application are that: this application improves the efficiency of connecting customer data with the internal production system through standardized incoming material pattern uploading, wafer batch binding, and internal pattern number generation.

[0009] Internal pattern numbering is generated in a standardized manner based on key information such as customer codes and process flows, reducing the cost of cross-stage communication. Furthermore, by comparing internal patterns with optical inspection, electrical testing, and benchmark patterns, the accuracy of detecting chip unit defects is improved. Using scientific computing methods to calculate the wafer yield and batch yield of the associated wafers from the internal patterns enables comprehensive control over wafer quality. The comparison and reporting of yield and yield thresholds provide data support for production decisions, improving the efficiency of identifying non-conforming batches and reducing the flow of defective products. Simultaneously, the standardization and data-driven management of the entire process improves the transparency and controllability of the production process, thereby enhancing the responsiveness to customer needs. This application improves the accuracy and traceability of the wafer yield assessment process. Attached Figure Description

[0010] Figure 1 A schematic flowchart of a wafer-level packaging pattern processing method provided in an embodiment of this application; Figure 2 This is a structural block diagram of a wafer-level packaging pattern processing system provided in an embodiment of this application; Figure 3 This is a schematic block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0011] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0012] To make the purpose, technical solution, and advantages of this application clearer, the following will be described in conjunction with the appendix. Figure 1-3 The following is an explanation using specific examples.

[0013] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a wafer-level packaging pattern processing method provided in an embodiment of this application. The method includes: S101: Receives incoming material patterns from customers and uploads them to the designated file server based on the customer code and pattern type; at the same time, it binds the incoming material patterns to the wafer batch and converts them into internal patterns; based on the customer code, process flow, pattern format, and site name of the internal pattern, it generates an internal pattern number.

[0014] In this embodiment, the incoming material pattern input by the customer is first validated. The validation criteria include format, preset upper limit of incoming material pattern size, and integrity of file hash value. If the validation passes, the pattern is uploaded to the specified directory of the file server according to the customer code and pattern type. At the same time, a log including upload time, operator, and file version is generated for traceability. If the validation fails, the specific error reason is immediately fed back and a re-upload entry is provided. The error reason may include file format mismatch or only supporting TIFF / PNG format.

[0015] Secondly, by reading wafer batch information, the incoming material map is bound to the wafer batch according to preset binding rules. The wafer batch information can be provided synchronously by the customer or extracted from related orders. The binding rules associate and map the wafer batch with the map file name. After binding, map conversion is performed. On the one hand, core data, such as image features, is extracted from the incoming material map; on the other hand, internal management fields, such as batch binding identifiers, are added to form an internal map that includes the customer's original information and internal management information. During the conversion process, the data format is standardized, and the coordinate system and parameter units are unified.

[0016] In this embodiment, the number is generated in the format of [pattern code-customer code-pattern format code-process flow code-site code], for example, number 01-JH-SINF-H0011-PI4, where 01 represents the internal pattern, JH represents the customer code, SINF represents the pattern format, H0011 represents the process flow code, and P14 represents the site code. After the number is generated, it is bidirectionally bound to the internal pattern file and wafer batch information, embedding the number in the file name and establishing a related index in the database to enable quick retrieval of relevant information by number.

[0017] S102: Based on the yield requirements, determine the yield threshold of the associated wafers of the internal pattern, and store the yield threshold in association with the internal pattern number.

[0018] In this embodiment, while receiving the incoming material pattern and associated wafer batch information, the system obtains the customer's pre-set yield target threshold. This yield target threshold is manually entered by the operator and must be accompanied by a scanned copy of the customer's written confirmation as evidence, ensuring the traceability of the yield target threshold's source. Format validation is required during entry to ensure the value is within the 0-100% range. For example, if the customer sets the yield target threshold to 99.2%, the system checks whether it meets the required range. If any abnormality is found, a prompt is triggered, requiring verification of the customer's original setting or a reset of the yield target threshold.

[0019] Secondly, by associating wafer batches with customer order information, the uniqueness of the yield achievement threshold set by the corresponding customer is confirmed. For example, if a customer provides multiple yield achievement thresholds for the same batch, the primary yield achievement threshold and the secondary yield achievement threshold are distinguished according to preset rules. The primary yield achievement threshold is the batch yield, and the secondary yield achievement threshold is the wafer yield. During the binding process, information such as the customer code, wafer batch, and the yield achievement threshold set by the customer are recorded in a temporary data table.

[0020] Subsequently, the customer-defined yield target threshold is associated with and stored in relation to the internal map number. In the internal map management table of the database, a new field for "Customer-defined Yield Target Threshold" is added. Through the binding relationship between the internal map number and the wafer batch, the confirmed customer yield target threshold is written into this field. Simultaneously, the source identifier of this yield target threshold is added to the associated record table, such as manually entered voucher number, entry time, and operator information, forming a complete association chain. For example, for the wafer batch corresponding to internal map number 01-JH-SINF-H0011-PI4, if the customer-defined yield target threshold is 99.2%, the mapping relationship between this number and 99.2% is recorded in the table and associated with the corresponding order voucher.

[0021] Finally, a correlation verification is performed: Firstly, it checks whether the mapping between internal map numbers and yield achievement thresholds is unique, to avoid the same number corresponding to multiple thresholds. Secondly, it verifies the consistency of yield achievement thresholds with customer codes and batches through cross-table comparisons. For example, it checks whether the yield achievement threshold corresponding to customer A's batch LOT001 is consistent with customer A's settings. After successful verification, the stored record is locked, and unauthorized modification is not allowed. If adjustments are needed, a written change notification from the customer is obtained, and the thresholds before and after the modification, along with the reason for the change, are recorded in the log, ensuring the entire process complies with customer requirements and is traceable. S103: Perform optical inspection and electrical testing on the associated wafer with the internal pattern to obtain the detection pattern.

[0022] In this embodiment, the associated wafers of the internal pattern are scanned in their entirety using an optical inspection device to acquire optical images including each chip unit. During scanning, batch information of the associated wafers is matched to ensure a one-to-one correspondence between the optical images and the associated wafers. Key conditions such as scanning resolution and light source parameters are also recorded. The optical images are then processed. First, visual features such as the chip unit's contour, circuit texture, and surface grayscale are extracted using image algorithms. Based on preset optical defect detection rules, such as scratch length thresholds, stain area standards, and circuit breakage identification parameters, defect detection is performed on each chip unit on the associated wafer, generating optical inspection results. Next, the electrical testing equipment is activated, and standard test signals, such as specific voltage and current signals, are applied to the chip test points on the associated wafer. The electrical response parameters fed back from each test point are collected in real time, including indicators such as on-resistance, leakage current, and breakdown voltage. Then, the electrical response parameters are compared with the preset standard range, and the electrical test results are generated.

[0023] Finally, using the associated wafer coordinates as a unified benchmark, the optical inspection results and electrical test results of the same chip unit are correlated and matched to establish a correspondence between chip position, optical state, and electrical state. Based on this, an inspection map is generated, which must include the overall layout of the associated wafer, the positional identifier of each chip unit, and the optical defect information and electrical state details corresponding to each chip unit, while also associating metadata such as internal map number, wafer batch, inspection equipment model, and inspection time.

[0024] S104: Compare the baseline spectrum with the detection spectrum to obtain the comparison result.

[0025] In this embodiment, the reference spectrum is a standard qualified spectrum of the associated wafer or a standard reference spectrum specified by the customer, and is associated with basic information such as the corresponding wafer batch and process parameters to ensure consistency with the comparison object of the detection spectrum. Before comparison, the core dimensions need to be determined, which include chip unit position matching, optical feature comparison, and electrical state comparison.

[0026] In this embodiment, firstly, using the wafer physical coordinates of the reference image as a standard, pixel-level registration is performed between the detection image and the reference image. Specifically, an image registration algorithm identifies and matches key feature points such as wafer edges and chip arrays of both images, correcting positional deviations in the detection image caused by scanning angles and device displacement, resulting in a registered image that is perfectly aligned with the spatial position of the reference image. Secondly, using the registered detection image as the object, pixel-by-pixel difference analysis is performed between it and the reference image. For each chip unit region in the registered detection image, optical features such as grayscale values, texture distribution, and contour sharpness are extracted. The numerical deviations of corresponding features between the two types of images are quantified using an algorithm to obtain the optical feature difference value for each chip unit region. Simultaneously, the electrical test results of each chip unit in the registered detection image are extracted and compared numerically with the standard electrical parameters of the corresponding chip unit in the reference image. For key parameters such as on-resistance and leakage current, the difference or percentage deviation between the detected value and the standard value is calculated to generate the electrical parameter difference value for each chip unit. Finally, based on the differences in optical features and electrical parameters, the defect information for each chip unit on the associated wafer is determined one by one. This defect information includes the defect type, severity, and dimension (e.g., optical or electrical defects). Finally, the defect information for all chip units is summarized, and a structured comparison result is formed based on the physical location of the wafers.

[0027] S105: Based on the comparison results, the chip cell defects of the associated wafers are statistically analyzed, and the wafer yield and batch yield are calculated.

[0028] In this embodiment, based on the determined total number of chip cells in a single associated wafer, the defect status of each chip cell is determined and classified one by one. The statistical dimensions include: the number of defect-free normal chips, the total number of chips with defects, and the number and distribution location of different defect types, ultimately forming detailed chip defect statistics for a single wafer. The defect types include optical defects, electrical faults, and combined defects. A combined defect refers to a situation where the same chip cell simultaneously exhibits both optical defects and electrical faults.

[0029] The yield of a single wafer is calculated using a fixed formula based on the detailed statistical data of chip defects on that wafer. The formula is: wafer yield is the percentage of the number of normal chips on a single wafer to the total number of chip units on that wafer. For example, if a wafer has a total of 2000 chip units and the number of normal chips is 1984, then the yield of that wafer is (1984 ÷ 2000) × 100% = 99.2%.

[0030] This embodiment determines the batch yield of the associated wafers by summing the total number of chip units across all wafers in the batch and summing the number of normal chips across all wafers, based on statistical data of the batch. The batch yield is the percentage of the total number of normal chips to the total number of chip units in the batch. For example, if a batch contains 5 wafers with a total of 10,000 chip units and 9,920 normal chips, then the batch yield is (9,920 ÷ 10,000) × 100% = 99.2%.

[0031] S106: Compare the wafer yield and batch yield with the wafer yield threshold and batch yield threshold in the yield compliance threshold respectively, obtain the judgment result, and generate report data corresponding to the internal map number.

[0032] In this embodiment, based on the internal map number, the associated yield compliance thresholds for the wafer are obtained, and the wafer yield compliance threshold and batch yield compliance threshold are determined. Simultaneously, the calculated wafer yield values ​​of the associated wafers and the corresponding batch yield values ​​are extracted to establish two sets of one-to-one comparison data: wafer yield - wafer yield compliance threshold and batch yield - batch yield compliance threshold, improving the accuracy of matching yield data with yield compliance thresholds. Next, the two sets of comparison data are judged separately. The actual wafer yield of a single wafer is compared with the wafer yield compliance threshold. If the actual wafer yield is greater than or equal to the wafer yield compliance threshold, it is judged as wafer yield compliance; if the actual wafer yield is less than the wafer yield compliance threshold, it is judged as wafer yield non-compliance. The actual batch yield is also compared with the batch yield compliance threshold, using the same judgment logic as for wafer yield, to obtain the result of batch yield compliance or batch yield non-compliance. Finally, these are integrated to form a complete yield judgment result.

[0033] This embodiment uses the internal map number as the core association identifier to integrate all key data to generate report data. The report data must include basic information: internal map number, associated wafer batch, and customer code; yield data: wafer yield and batch yield; threshold data: wafer yield compliance threshold and batch yield compliance threshold; and judgment results: wafer yield judgment status and batch yield judgment status, along with supplementary information such as data generation time and statistical basis.

[0034] As can be seen from the above, this application improves the efficiency of connecting customer data with the internal production system through standardized incoming material pattern uploading, wafer batch binding, and internal pattern number generation. The standardized generation of internal pattern numbers based on key information such as customer codes and process flows reduces the cost of cross-stage communication. Furthermore, optical inspection, electrical testing, and comparison with benchmark patterns improve the accuracy of detecting chip unit defects. Using scientific computing to calculate the wafer yield and batch yield of the associated wafers from the internal patterns enables comprehensive control over wafer quality. The comparison and judgment of yield and yield thresholds, along with report generation, provides data support for production decisions, improving the efficiency of identifying non-conforming batches and reducing the flow of defective products. Simultaneously, the standardization and data-driven management of the entire process improves the transparency and controllability of the production process, thereby enhancing the responsiveness to customer needs. This application improves the accuracy and traceability of the wafer yield judgment process.

[0035] In one embodiment of this application, optical inspection of associated wafers with internal patterns includes an adaptive inspection step based on device status: Real-time acquisition of health status parameters of optical inspection equipment, including light source brightness attenuation rate, lens cleanliness score, and mechanical positioning accuracy deviation; By inputting health status parameters into a pre-trained device status model, the potential false detection rate and false negative rate of the device in the current detection task are predicted. If the potential false detection rate or false negative rate exceeds the preset equipment reliability threshold, the sampling frequency and detection parameters of the optical inspection will be adjusted, wherein: For areas with a high risk of missed detection, increase the image sampling resolution; For defect types with a high risk of false positives, additional verification algorithms with higher computational complexity are used for review.

[0036] In this embodiment, the health status parameters of the optical inspection equipment are acquired in real time. These parameters include the light source brightness attenuation rate, lens cleanliness score, mechanical positioning accuracy deviation, continuous operating time of the equipment, and auxiliary status parameters such as fault warning records for the past cycle. The light source brightness attenuation rate needs to be accurate to 0.1% attenuation gradient, and the light source wavelength offset is recorded simultaneously. The lens cleanliness score uses a 0-10 point quantification standard, based on the proportion of contaminant area on the lens surface and the detected value of scattered light intensity. The mechanical positioning accuracy deviation is a three-dimensional directional error value; for example, the X / Y axis accuracy is accurate to ±0.1μm, and the Z-axis focusing error is accurate to ±0.05μm.

[0037] In this embodiment, health status parameters are input into a pre-trained device status model. This model is trained using sample data on the correlation between historical inspection data and device status. It can output the potential false positive rate and false negative rate of the optical inspection equipment in the current inspection task, and simultaneously generate a risk confidence interval. The false positive rate is classified according to defect type, including scratches, particles, and color differences; the false negative rate is divided according to wafer region, including edge areas, center areas, and densely patterned areas. If the potential false positive rate or false negative rate is greater than the preset device reliability threshold, the potential false positive rate and false negative rate can be adjusted according to the wafer process stage. For example, the inspection threshold before photolithography is set to a false positive rate ≤ 0.5% and a false negative rate ≤ 0.3%, and the inspection threshold before packaging is set to a false positive rate ≤ 1.0% and a false negative rate ≤ 0.8%. The preset device reliability threshold is determined by combining historical data statistics, wafer process requirements, defect impact weights, and industry standards.

[0038] In this embodiment, for high-risk areas of missed detection, such as the edge range of 3mm or the pattern density greater than 500 points / mm², the sampling density is increased by 50%-100% based on the original sampling frequency. At the same time, the image sampling resolution is increased from the basic 1μm / pixel to 0.5μm / pixel, and the exposure time of a single area is extended by 10%-20% to compensate for the effect of light source attenuation. For high-risk defect types of false detection, such as tiny particles smaller than 2μm or low-contrast color difference defects, in addition to the basic detection algorithm, additional algorithms with higher accuracy based on the basic detection algorithm are used for verification. These include: a defect feature enhancement model based on deep learning, which can improve the feature recognition signal-to-noise ratio by more than 30%; a multispectral imaging cross-validation algorithm, which can collect 3-5 band spectral images for comparison; and a three-dimensional morphology reconstruction-assisted judgment, which generates a three-dimensional contour of the defect through focusing stacking technology. The processing priority of the above high-complexity algorithms can be dynamically allocated according to the real-time computing power load, so that the detection efficiency loss is controlled within 20%.

[0039] As can be seen from the above, this embodiment, by monitoring the health status parameters of the optical inspection equipment and predicting the potential false positive and false negative rates based on a pre-trained equipment state model, can identify the detection risks caused by equipment performance fluctuations in advance. When the risk exceeds the limit, the sampling frequency and detection parameters are adjusted accordingly, thereby enhancing the reliability of the optical inspection process.

[0040] In one embodiment of this application, optical detection and electrical testing are performed on the associated wafer of the internal pattern to obtain the detection pattern, including: Acquire scanned images of the associated wafers by optical inspection equipment as optical images; Feature extraction is performed on the optical image, and based on the preset optical defect detection rules, defects are detected in the identified chip units to generate optical detection results; Electrical response parameters are obtained by applying test signals to test points on associated wafers using electrical testing equipment. The electrical response parameters are compared with preset standards to generate electrical test results that include the electrical state of each chip unit; the electrical response parameters are obtained by applying test signals to test points on the associated wafer using electrical testing equipment; The optical detection results and electrical test results are fused to obtain the detection spectrum.

[0041] In this embodiment, optical images are acquired using a multimodal imaging method, including bright-field images with a resolution ≥0.5μm / pixel, dark-field images to enhance the contrast of minor scratches, and infrared thermal images to capture local thermal anomalies. The coordinate positioning information of each imaging region is recorded simultaneously, ensuring precise alignment with the wafer coordinate system. Next, multi-scale feature extraction is performed on the optical images. Specifically, Gaussian pyramid decomposition technology is used to separate the surface texture, edge contours, and defect candidate regions of the chip units. Based on a preset optical defect detection rule library, a YOLOv8-based defect detection model is used to classify the identified chip units for defects, generating optical inspection results including defect location, size parameters, and confidence scores. The preset optical defect detection rule library includes quantitative standards such as scratch length ≥2μm, particle diameter ≥0.3μm, and color difference deviation ≥5%. Defect classification includes metal residue, lithography defects, and cracks. Simultaneously, electrical response parameters are acquired after applying preset test signals to test points on the associated wafer using an electrical testing device probe card. The electrical response parameters include on-resistance, breakdown voltage, signal delay time, leakage current, and functional logic state, which includes high / low / abnormal states. Test points include power pins, signal interfaces, and functional test pads; test signals include DC voltage, AC signals, and timing pulses, with a voltage range of 5V-3.3V and a frequency range of 1kHz-1GHz. Finally, the electrical response parameters are compared with preset standards, such as those based on chip design specifications, using threshold judgment and trend analysis. Specifically, commercial-grade, industrial-grade, and automotive-grade correspond to different threshold ranges. For example, an abnormal flag is triggered when the parameter deviation rate between adjacent test points exceeds 10%, generating electrical test results including the electrical state, failure mode, and out-of-specification key parameters for each chip unit. The electrical state includes: normal, failed, and degraded; the failure mode includes: short circuit, open circuit, and functional abnormality.

[0042] This embodiment performs layered fusion of optical detection results and electrical test results, including a spatial layer, a feature layer, and a decision layer; wherein, Spatial layer fusion involves matching the locations of optical defects with the coordinates of electrical test points based on the wafer coordinate system, identifying strong correlations between defects and electrical anomalies at the same location, such as the correspondence between optically detected metal bridging and electrical short circuits.

[0043] Feature layer fusion includes extracting the correlation features of geometric and electrical parameters of optical defects, and establishing mapping rules between defect types and failure modes through a random forest model, such as the quantitative relationship that every 1 μm increase in scratch length corresponds to a 0.5 Ω increase in on-resistance.

[0044] The decision-making fusion process involves using the DS evidence theory to weight and fuse the confidence levels of the two types of results. When the confidence level of an optical defect is ≥80% and the probability of electrical abnormality at the corresponding location is ≥90%, it is determined to be a confirmed failure. For cases with a single abnormal result, such as a suspected optical defect but normal electrical properties, it is marked as pending review and the priority of that area is increased in subsequent sampling inspections.

[0045] The detection spectrum generated after fusion in this embodiment uses the wafer topology map as a base, overlays color-coded defect distribution and electrical parameter heatmaps, and includes a defect-electrical correlation report for each chip unit, realizing the visualized linkage analysis of optical features and electrical performance.

[0046] As can be seen from the above, this embodiment achieves multi-dimensional inspection of wafer chip units by separately acquiring physical defect information from optical inspection and performance parameter information from electrical testing. This covers both visible defects such as scratches and dirt, and hidden problems such as abnormal electrical response. By fusing the two types of inspection results to form a detection map, the limitations of a single inspection method are overcome, improving the comprehensiveness and accuracy of defect detection.

[0047] In one embodiment of this application, optical detection results and electrical test results are fused to obtain a detection spectrum, including: The position coordinates of the chip unit in the optical inspection results are mapped and matched with the position coordinates of the chip unit in the electrical test results to obtain the mapping and matching results; Based on the mapping matching results, a status identifier for the chip unit is constructed, which includes the optical and electrical status of the chip unit. A detection map is generated based on the status identifiers and position coordinates of all chip units.

[0048] In this embodiment, firstly, the two-dimensional pixel coordinates of the chip units in the optical inspection results are converted into the wafer physical coordinate system by the alignment marks of the chip units on the wafer, such as edge positioning slots and surface reference points. At the same time, the coordinates of the test points based on probe card positioning in the electrical test results are also mapped to the same physical coordinate system. The influence of mechanical errors and imaging distortion of the equipment is eliminated by the coordinate deviation correction algorithm. Finally, the mapping matching result includes a unique identifier for each chip unit, the correspondence between optical and electrical coordinates, and the matching confidence level. Among them, a matching confidence level ≥ 99.5% is a valid match.

[0049] Secondly, a multi-dimensional status identifier for the chip unit is constructed based on the mapping and matching results. For example, the status identifier adopts a hierarchical coding structure: the base layer includes optical status and electrical status. The optical status includes no defects, surface particles, edge cracks, etc., with defect size and confidence value attached; the electrical status includes normal parameters, excessive leakage current, functional failure, etc., with measured values ​​of key parameters and standard deviation rate attached; the correlation layer generates cross-judgment results through a rule engine. For example, when optical detection shows metal bridging and electrical testing shows short circuit between adjacent pins, it is marked as a strong correlation failure; when only a single dimension is abnormal, it is marked as a weak correlation failure.

[0050] Finally, the status indicators and location information of all chip units are integrated to generate a detection map. The detection map uses a top-down view of the wafer as a base and employs multi-layer overlay technology for visualization. Specifically, the location information layer depicts the chip array distribution according to scale and marks the specific coordinates of the failed units. In addition, the status indicator layer uses color coding to obtain the detection map. The colors include green, red, and yellow, where green indicates normal operation in both dimensions, red indicates strong correlation failure, and yellow indicates weak correlation anomaly.

[0051] As can be seen from the above, this embodiment establishes a correlation between optical and electrical states through position coordinate mapping and matching, enabling the quality information of each chip unit to form a complete closed loop and avoiding the isolated interpretation of the two types of detection results. Based on the detection map generated from the state identifier and position coordinates, the visualization and location of defect information are achieved. It improves the efficiency of staff in identifying problematic chips and specific defect types, while also addressing the pain point of traditional testing that emphasizes results over correlation. It provides intuitive and accurate data support for subsequent defect review and process improvement, thereby enhancing the level of precision in quality control.

[0052] In one embodiment of this application, the reference spectrum includes standard optical features and standard electrical parameters of the detection spectrum; The baseline spectrum and the detected spectrum are compared to obtain the comparison results, including: The detection map and the reference map are registered at the pixel level to obtain the registration map. A pixel-by-pixel difference analysis was performed between the registration map and the reference map to calculate the optical feature difference value of each chip region. The electrical test results in the detection spectrum are numerically compared with the standard electrical parameters in the reference spectrum, and the difference in electrical parameters of each chip unit is calculated. Based on the differences in optical features and electrical parameters, the defect information of each chip cell on the associated wafer is determined. The defect information of all chip units is summarized to obtain the comparison results.

[0053] In this embodiment, standard optical features include: surface texture template of defect-free chip, grayscale mean and standard deviation range of normal imaging, geometric dimensional tolerance of feature structure, etc.; standard electrical parameters include: resistance / capacitance reference values ​​in design specifications, signal transmission delay threshold, allowable leakage current range, etc.

[0054] This embodiment compares the reference map and the detection map to obtain the comparison result. For example, by extracting the global positioning features of the wafer in the reference map and the detection map, such as edge notch marks and alignment marks of the surface array distribution, a scale-invariant feature transformation algorithm is used to match feature points. Based on a rigid transformation and local elastic deformation correction model, map offsets caused by equipment positioning errors and the tilt of the associated wafer are eliminated, resulting in a registration map with one-to-one coordinates. Specifically, the pixel coordinate deviation after registration is ≤0.5 pixels, corresponding to a physical precision of ≤0.25μm. Next, a multi-dimensional pixel-by-pixel difference analysis is performed on the chip area of ​​the registration map and the reference map. For example, the grayscale deviation value, gradient direction difference, and texture consistency of each pixel are calculated, and an optical feature difference value is generated through weighted fusion. The range of the optical feature difference value is 0-100 points, and the fusion weight is adjusted according to the defect type; for example, the gradient difference weight is increased when detecting scratches. Simultaneously, spatial clustering analysis is performed on the optical feature difference values. For example, regions with ≥3 consecutive pixels and an optical feature difference value ≥50 are marked as suspected optical defect areas, and the geometric parameters of the defects are recorded, including area, perimeter, and circumscribed rectangle size. Finally, a chip unit-parameter mapping relationship is established between the detection map and the benchmark map, and numerical comparisons are performed according to parameter type. Specifically, for continuous parameters such as voltage and current, absolute deviation and relative deviation rate are calculated; for discrete parameters such as logic state, the matching degree is directly determined, such as consistency or inconsistency. Subsequently, the comprehensive electrical parameter difference value is calculated through a preset parameter weight matrix, and the type and trend characteristics of parameters exceeding the standard are marked. The preset parameter weight matrix is ​​constructed by comprehensively considering defect impact weight, parameter importance classification, historical data training, and industry standard calibration.

[0055] For example, when the optical feature difference value is ≥60 points and the corresponding region's electrical parameter difference rate is ≥10%, it is determined to be a deterministic defect. The defect is then classified according to the optical defect detection rule base and the corresponding electrical parameters to obtain a comparison result. For example, metal layer scratches may cause excessive on-resistance or photolithography misalignment may cause logic function failure. When a single dimension exceeds the limit, such as significant optical differences but normal electrical properties, it is marked as a potential defect and the difference characteristics are recorded. This comparison result includes: a list of wafer coordinates of the defect location, statistical distribution of the defect type, and a synchronized output highlighting of the differences between the superimposed benchmark and the detection spectrum.

[0056] As can be seen from the above, this embodiment employs pixel-level registration and pixel-by-pixel difference analysis to ensure the accuracy of optical feature comparison. Combined with numerical comparison of electrical parameters, it achieves quantitative judgment of defect information. By calculating the difference values ​​of optical features and electrical parameters separately, the causes of different types of defects can be distinguished. Simultaneously, by summarizing the defect information of all chip units to form a comparison result, it avoids the omission of defects in individual chips while ensuring the comprehensiveness of the overall wafer quality assessment.

[0057] In one embodiment of this application, defect information for each chip cell on an associated wafer is determined based on optical feature difference values ​​and electrical parameter difference values, including: The electrical parameter difference value is compared with a preset first threshold to determine whether the electrical test result of the chip unit is qualified. If the electrical test results are unqualified, the corresponding electrical defect information shall be recorded. Based on the comparison between the optical feature difference value and the preset second threshold, it is determined whether the optical detection result of the chip unit is qualified. If the optical inspection results are unqualified, the optical defect information of the corresponding chip unit is recorded.

[0058] In this embodiment, the electrical parameter difference value is compared with a preset first threshold to determine whether the electrical test result of the chip unit is qualified. The electrical parameter difference value is the absolute value of the difference between the actual electrical parameters of the chip unit in the detection spectrum and the standard electrical parameters of the corresponding chip unit in the control reference spectrum. The first threshold is set according to the product specification and historical qualified batch data, including independent threshold standards for different electrical parameters, such as a 5% threshold for on-resistance difference and a 10% threshold for leakage current difference. When the difference value of any electrical parameter is greater than the first threshold, the electrical test result of the chip unit is determined to be unqualified; otherwise, it is determined to be qualified.

[0059] If the electrical test results are unsatisfactory, the corresponding electrical defect information is recorded. This information includes the chip cell's coordinates on the wafer, the type of electrical parameter that failed (e.g., excessive leakage current), the specific difference between the actual measured value and the standard value, the test time, and the test equipment number. Simultaneously, a pre-defined electrical defect code is associated with this defect; for example, "E01" represents excessive leakage current, and "E02" represents abnormal on-resistance. The process parameters at the time of the defect are also marked, such as the test voltage and the test environment temperature.

[0060] This embodiment determines whether the optical inspection result of the chip unit is qualified based on a comparison between the optical feature difference value and a preset second threshold. The optical feature difference value includes the deviation of characteristic parameters such as the length of scratches on the chip surface, the area of ​​contamination, and the offset of bonding points from standard values. The second threshold is set according to the degree of impact of optical defects on product function. For example, the threshold for scratch length of fatal defects is set to 50 μm, and the threshold for contamination area of ​​minor defects is set to 0.01 mm². When the optical feature difference value is greater than the corresponding second threshold, the optical inspection result of the chip unit is determined to be unqualified; when the optical feature difference value is less than or equal to the corresponding second threshold, it is determined to be qualified. Minor defects may be exempted according to product grade requirements.

[0061] If the optical inspection result is unqualified, the optical defect information of the corresponding chip unit is recorded. The optical defect information includes the coordinate position of the chip unit, the type of optical defect (e.g., scratches, stains, bond offsets), quantification parameters of the defect features (e.g., scratch length 30μm, offset 20μm), the pixel coordinate range of the defect in the optical image, and the model of the inspection equipment. Simultaneously, an optical defect code is assigned to the defect; for example, "O01" represents a surface scratch, and "O02" represents a bond offset.

[0062] As can be seen from the above, this embodiment establishes clear criteria for judging optical and electrical defects by setting a first threshold and a second threshold, making the defect judgment process standardized and quantifiable, and avoiding the subjectivity and uncertainty of manual judgment. Furthermore, by independently judging the electrical test results and optical inspection results and recording the corresponding defect information, the distribution of the two types of defects can be distinguished, ensuring the effective screening of unqualified chips.

[0063] In one embodiment of this application, a wafer-level packaging pattern processing method further includes: A training dataset is constructed based on the acquired historical production data. The training dataset includes the differences in optical features and electrical parameters of the chips, as well as the corresponding final defect verification results. Based on the training dataset, an optimization algorithm is used to jointly optimize the first threshold and the second threshold. The objective function of the optimization algorithm is configured to minimize the comprehensive quality loss calculated by weighting the over-kill rate and the under-kill rate. The over-kill rate is the proportion of qualified chips that are misclassified as defects, and the under-kill rate is the proportion of defective chips that are misclassified as qualified. The optimal threshold combination obtained through optimization is used as the threshold optimization parameter to adjust the first and second thresholds.

[0064] In this embodiment, a training dataset for threshold optimization is constructed based on historical data accumulated during chip manufacturing. This training dataset includes optical feature differences generated during optical inspection, electrical parameter differences generated during electrical inspection, and the actual defect results obtained after the final physical verification of the chips corresponding to these two types of differences. Secondly, based on the constructed training dataset, an optimization algorithm is used to jointly optimize the first threshold corresponding to optical inspection and the second threshold corresponding to electrical inspection. The core objective function of the optimization algorithm is set to minimize the overall quality loss, which is calculated as follows: Overall quality loss = Overkill rate × Overkill weight + Missed detection rate × Missed detection weight Among them, the overkill weight and the miss weight are non-negative coefficients, and both meet the normalization requirement, that is, overkill weight + miss weight = 1.

[0065] The over-detection rate is the proportion of chips that are actually qualified but are mistakenly identified as defective because the detection value exceeds the threshold. The under-detection rate is the proportion of chips that are actually defective but are mistakenly identified as qualified because the detection value does not exceed the threshold.

[0066] Finally, through iterative calculations using the optimization algorithm, a combination of the first and second thresholds that minimizes the overall quality loss is obtained, and this combination is determined as the final optimal threshold optimization parameter. This parameter is then used to update and adjust the first and second thresholds in the current production inspection process, achieving optimized configuration of the inspection thresholds and improving the overall accuracy of chip defect detection.

[0067] As can be seen from the above, this embodiment constructs a training dataset based on historical production data, providing solid practical data support for threshold optimization and avoiding the blind setting of thresholds. By optimizing the algorithm to jointly optimize the first and second thresholds, and targeting the weighted comprehensive quality loss of over-detection rate and under-detection rate, it effectively balances the risks of misjudging qualified chips and under-detecting defective chips, reducing the waste of high-quality chips while ensuring product quality stability.

[0068] In one embodiment of this application, defect information for each chip unit is determined based on optical feature difference values ​​and electrical parameter difference values, including: The optical feature differences and electrical parameter differences of the same chip unit are fused at the feature layer to generate a multidimensional defect feature vector. Input the multidimensional defect feature vector into the defect classification model to obtain the defect classification result; Based on the defect classification results, the defect category of the chip unit is determined.

[0069] In this embodiment, firstly, for the same chip unit, the optical feature difference values ​​generated during the optical inspection stage and the electrical parameter difference values ​​generated during the electrical inspection stage are extracted. These two types of feature data from different inspection dimensions are fused at the feature layer to form a multi-dimensional defect feature vector that comprehensively reflects the chip state. Next, based on the preprocessed feature data, a feature layer fusion strategy is used for information integration. The integration process uses methods such as feature splicing, feature concatenation, or attention mechanism weighting to fuse the effective information of the optical and electrical features, generating a multi-dimensional defect feature vector that includes core information from both types of features.

[0070] Secondly, the multidimensional defect feature vector is input into the defect classification model. This model analyzes and judges the input multidimensional features through its internal feature learning and inference mechanism to obtain the preliminary defect classification result of the corresponding chip unit. The defect classification model is obtained by using a large number of chip multidimensional defect feature vectors labeled with real defect categories as training data, and through model structure construction, parameter initialization, and multiple rounds of iterative training and optimization.

[0071] Finally, based on the classification results output by the defect classification model, the specific defect category of the chip unit is determined. Defect categories include: material structural damage, interface delamination, and micro-short circuits. These defect categories cannot be independently determined by a single optical or electrical analysis. Material structural damage, such as lattice defects within the wafer, needs to be determined jointly based on microstructural anomalies detected by optical inspection and local resistance abrupt changes detected by electrical inspection. Interface delamination, such as poor bonding between chip layers, needs to be confirmed through the combined use of interface reflection differences in optical features and signal transmission loss in electrical parameters. Micro-short circuits, such as minor overlaps in metal wiring, need to be comprehensively identified by integrating wiring morphology deviations detected by optical inspection and abnormal current path characteristics detected by electrical inspection.

[0072] As can be seen from the above, this embodiment integrates the physical morphology information of optical detection and the performance response information of electrical testing through multi-feature fusion analysis, and also distinguishes complex defects through model-based classification, thereby improving the comprehensiveness and accuracy of defect identification.

[0073] In one embodiment of this application, the wafer yield and batch yield are compared with the wafer yield compliance threshold and batch yield compliance threshold, respectively, to obtain a judgment result, including: If the wafer yield is greater than or equal to its corresponding wafer yield compliance threshold, and the batch yield is greater than or equal to its corresponding batch yield compliance threshold, then the batch wafer is judged to have met the yield standard. Otherwise, the yield of this batch of wafers will be deemed substandard.

[0074] In this embodiment, before determining the batch wafer yield, two key thresholds need to be pre-set: one is the wafer yield threshold, which is the minimum qualified percentage standard that a single wafer must achieve; the other is the batch yield threshold, which is the overall qualified percentage standard that the entire batch of wafers must achieve. These two thresholds need to be pre-determined in conjunction with factors such as production process capabilities, product quality requirements, and customer standards.

[0075] Subsequently, a dual-condition judgment is performed on the batch wafer yield. Specifically, after completing the inspection and yield statistics for the batch of wafers, the actual yield of a single wafer is compared with the preset wafer yield threshold, and the overall wafer yield of the batch is compared with the preset batch yield threshold. Only when both conditions are met simultaneously—that is, the actual wafer yield is greater than or equal to its corresponding wafer yield threshold, and the actual batch yield is greater than or equal to its corresponding batch yield threshold—can the yield of the batch of wafers be determined to be up to standard.

[0076] If any condition is not met, the yield is deemed substandard. For example, the yield of a batch of wafers will be deemed substandard if either of the following two conditions occurs: first, the actual wafer yield is less than its corresponding wafer yield threshold; second, the actual batch yield is less than its corresponding batch yield threshold.

[0077] As can be seen from the above, this embodiment adopts a dual-threshold parallel judgment method for wafer yield and batch yield, which focuses on both the individual quality of a single wafer and the overall stability of the batch. This judgment method strictly aligns with the preset yield target threshold, ensuring the rigid implementation of quality standards, effectively avoiding quality risks caused by single-dimensional judgment, providing downstream customers with stable and reliable product assurance, and helping to enhance the company's market competitiveness.

[0078] In one embodiment of this application, a wafer-level packaging pattern processing method further includes: After determining that the yield rate is below standard, the chip units identified as defective in the comparison results and their location coordinates are used as the dataset to be reviewed. Based on a pre-defined minor defect rule base, each chip unit in the dataset to be reviewed is reviewed and judged. If the defect information of any chip cell meets any exemption condition in the minor defect rule base, its status is updated from defective to acceptable, and the wafer yield and batch yield are recalculated based on the updated status.

[0079] In this embodiment, based on the detection and comparison results generated during the previous yield assessment process, all chip units identified as defective are screened out, and the precise location coordinates of these defective chip units on the wafer are extracted simultaneously. The defective chip unit information and corresponding location coordinates are correlated and integrated to form a dataset to be further reviewed. Next, a defect review judgment is performed according to a preset minor defect rule library. For example, the pre-built minor defect rule library is used as the judgment basis, and each defective chip unit in the dataset to be reviewed is verified one by one. This rule library includes exemption conditions for various minor defects, such as minor cosmetic scratches that do not affect the core function of the chip, and minor electrical parameter deviations within the normal operating range. The review process must strictly match the defect information of the chip unit with the exemption clauses in the rule library.

[0080] Finally, after reviewing all defective chip cells, for those chip cells that meet any exemption condition in the rule base, their status is updated from defective to acceptable. Based on the updated status of all chip cells, the wafer yield and batch yield of this batch of wafers are recalculated to form the final yield data after review.

[0081] As can be seen from the above, this embodiment adds a review step after the initial yield assessment fails to meet the standard. By using a minor defect rule library to perform a secondary screening of defective chips, it avoids misjudging chips with minor defects that do not affect usability as unqualified products, reducing the over-crit rate. Simultaneously, it improves wafer resource utilization and actual production efficiency. The yield is recalculated based on the review results, making the yield assessment more closely aligned with actual usage needs. This avoids batch misjudgments caused by initial assessment biases and provides a more accurate reference for production decisions.

[0082] In one embodiment of this application, based on a preset minor defect rule base, each chip unit in the dataset to be reviewed is judged for review, including: Obtain optical defect information from the dataset to be reviewed. The optical defect information includes defect type, defect size, and defect location. The optical defect information is matched with the exemption conditions in the minor defect rule base; among which... The exemption conditions include at least one of the following: the defect type is a scratch, the defect size is less than the first size threshold, and the scratch is located in the dicing area of ​​the chip unit; the defect type is dirt, and the defect size is less than the second size threshold; the defect type is uneven color of the metal layer, and the difference in electrical parameters is within the preset tolerance range; the defect location is located in the non-functional core area of ​​the chip unit, and the defect size is less than the third size threshold.

[0083] In this embodiment, feature extraction of optical defect information is performed on the constructed dataset to be reviewed. The dataset to be reviewed includes defective chip units and their location coordinates. Based on optical inspection data, three types of core optical defect information are extracted from each defective chip unit: First, defect type, clarifying the specific morphological attributes of the defect, such as scratches, surface dirt, uneven metal layer color, and micro-dents. This classification needs to be determined according to industry-standard defect morphology and internal inspection specifications. Second, defect size, obtaining the actual physical size of the defect through the measurement function of optical inspection equipment, usually in micrometers (μm), recording key dimensional parameters such as the maximum length, width, or diameter of the defect. Third, defect location, accurately locating the coordinate position of the defect on the wafer by combining the wafer coordinate system and the internal layout diagram of the chip unit, and clarifying the specific area of ​​the location within the chip unit, such as the dicing area. Functional core areas: logic operation units, memory units; Non-functional core areas: edge redundant circuit areas, identification areas. These three types of information are associated with the unique identifier of the corresponding chip unit to form a structured optical defect information table.

[0084] Secondly, optical defect information matching and verification are performed based on the minor defect rule base. Specifically, after extracting the features of the optical defect information, it is matched with the minor defect rule base. The optical defect information of each chip unit in the dataset to be reviewed is compared and verified against the preset exemption conditions in the rule base from multiple dimensions. The minor defect rule base is constructed by combining chip product characteristics, application scenario requirements, and industry quality standards. It includes multiple exemption judgment clauses for minor defects, each with clearly defined judgment dimensions and quantification thresholds. The specific exemption conditions are as follows: Condition 1: Exemption for minor scratches in the dicing area. If the defect type is determined to be a scratch, an exemption can be granted only if two additional conditions are met: First, through size comparison, it is confirmed that the maximum length and width of the scratch are both less than a preset first size threshold, which is set according to the cutting process precision and the width of the dicing channel; second, through position verification, it is confirmed that the scratch is completely located in the dicing channel area between chip units, and this dicing channel area will be cut away in the subsequent packaging process and will not affect the function and performance of the finished chip.

[0085] Condition 2: Minor Contamination Exemption. If the defect type is surface contamination, such as dust particles or residual organic matter, only size determination is required. When the equivalent diameter of the contamination is less than a preset second size threshold, it is determined to be an exempt minor defect. The second size threshold is set according to the degree of impact of the contamination on the chip's heat dissipation and insulation performance.

[0086] Condition 3: Exemption for Uneven Metal Layer Color. If the defect type is uneven metal layer color, a joint judgment must be made based on the electrical test data of the chip unit: First, confirm that the color difference in optical characteristics is only an appearance phenomenon and there is no obvious structural abnormality; second, retrieve the electrical parameter difference value corresponding to the chip unit. If this value is within the preset tolerance range, for example, voltage deviation ≤ ±0.05V, current fluctuation deviation ≤ ±1mA. The electrical parameter difference value is set according to the chip's electrical performance indicators, indicating that the uneven color does not affect the conductivity of the metal layer, and can be exempted.

[0087] Condition 4: Exemption for Minor Defects in Non-Functional Areas. This condition applies to various defect types. The core judgment logic is based on dual constraints of location and size. Specifically, it is confirmed through the chip cell layout diagram that the defect location is entirely within a non-functional core area. This area contains no critical circuits or devices and does not participate in the implementation of the chip's core functions. Secondly, it is determined that the maximum size of the defect is less than a preset third size threshold. The third size threshold is set according to the design redundancy of the non-functional area. This defect will not affect the overall quality of the chip and meets the exemption requirements.

[0088] During the matching process, each exemption condition is compared sequentially according to a preset priority. If the defect information meets any one of the conditions, the chip unit is initially determined to meet the exemption requirements and enters the subsequent status update stage; if none of the conditions are met, its defective state is maintained. The preset priority is set around two core dimensions: the risk of the defect's impact on the finished chip and the complexity of the judgment logic, following the principle that the lower the impact risk and the simpler the judgment, the higher the priority. Specifically, the exemption for minor scratches in the dicing area is set as the first priority because the dicing area will be removed by subsequent cutting, the defect has no substantial impact, and the judgment only requires three simple dimensions: type, size, and location; the exemption for minor dirt has negligible interference with chip function and only requires judgment of type and size, so it is set as the second priority; the exemption for minor defects in non-functional areas does not affect the core function, but requires correlation with the chip layout diagram to confirm the location of the non-functional area, making the judgment slightly more complex, so it is set as the third priority; the exemption for uneven color of the metal layer requires verification across two dimensions: optical and electrical, implying potential performance risks and having the most complex judgment logic, so it is set as the fourth priority.

[0089] As can be seen from the above, this embodiment clarifies the optical defect information dimension of the dataset to be reviewed, providing a basis for judging minor defects and standardizing the review process. The exemption conditions in the minor defect rule base for different defect types, sizes, locations, and electrical parameters define the boundaries of acceptable minor defects. This ensures the quality of the core functional areas of the chip while reasonably exempting minor defects with no impact, thereby avoiding excessive quality control of related wafers. In one embodiment of this application, after determining that the yield of the batch of wafers is substandard, the method further includes: The detection spectrum or comparison results of the current batch are compared with the spectrum similarity search in the historical batch database. Spectral similarity retrieval is calculated based on the similarity of defect distribution patterns, spectral features, or electrical parameter deviation patterns. Identify one or more historical batches that have the highest similarity to the current batch defect map, and output the process equipment identifiers or raw material batch information common to these historical batches as potential root causes.

[0090] In this embodiment, firstly, a standardized historical batch database is established by using complete historical inspection data from each production batch, including core data such as optical inspection spectra, electrical parameter comparison results, and defect distribution heatmaps for each batch of wafers, while simultaneously storing the corresponding batch's entire production chain information. The entire production chain information includes the identification of the process equipment used: equipment numbers such as lithography machines and etching machines; raw material batch information: wafer substrate batches and photoresist batches; key process parameters: temperature, pressure, and reaction time; and the final defect root cause analysis report. Simultaneously, the current batch is analyzed, and core feature data for similarity retrieval is extracted. Secondly, two types of key information are selected from the inspection results of the current batch: one is defect-related characteristics, including the distribution pattern of defects on the wafer and the spectral characteristics of defects. The distribution pattern of defects on the wafer includes concentrated distribution, scattered distribution, and ring distribution, while the spectral characteristics of defects include the wavelength reflection / absorption characteristics of the defect area in optical inspection; the other is parameter deviation characteristics, i.e., the deviation pattern of electrical parameters, such as an overall high level of a certain parameter, abnormal fluctuations in local parameters, or regular deviations in specific parameters. These feature data are then structured and transformed into standardized feature vectors that can be used for similarity calculation.

[0091] In this embodiment, the standardized feature vector extracted from the current batch is used as the retrieval benchmark to initiate a multi-dimensional spectral similarity retrieval process in the historical batch database. This retrieval process uses three core calculation dimensions: defect distribution pattern, spectral features, and electrical parameter deviation pattern, employing a multi-feature fusion similarity calculation method. In specific calculations, appropriate algorithms are used for different dimensions. For example, for defect distribution patterns, an image matching algorithm is used to calculate the overlap and distribution density similarity between the current batch's defect distribution heatmap and historical batches; for spectral features, a spectral analysis algorithm is used to calculate the waveform similarity and characteristic peak position matching degree between the current batch's defect region spectral curve and historical batches; for electrical parameter deviation patterns, a data sequence comparison algorithm is used to calculate the trend similarity and deviation amplitude consistency between the current batch's parameter deviation sequence and historical batches. Subsequently, a weighted summation method is used to obtain the overall similarity score between the current batch and each historical batch. The weights can be pre-set according to the sensitivity of different defect types to each feature dimension. For example, appearance defects emphasize spectral features and distribution patterns, while performance defects emphasize electrical parameter deviation patterns. Subsequently, based on the overall similarity score, the 1-3 historical batches with the highest similarity were selected as key targets for tracing.

[0092] This embodiment, after identifying the historical batches with the highest similarity, retrieves the corresponding end-to-end production information from the historical batch database. Focusing on two core dimensions—process equipment identification and raw material batch information—it conducts common information extraction and root cause analysis. First, it reviews the usage of process equipment in key historical batches, extracting equipment identification for each batch in critical production stages, statistically analyzing the frequency of different equipment occurrences, and filtering out equipment numbers commonly used by all key historical batches. These devices may become potential factors leading to similar defects due to performance fluctuations, parameter drift, or untimely maintenance. Second, it analyzes the raw material usage information of key historical batches, extracting batch numbers for key raw materials such as wafer substrates, photoresists, and metal targets used in each batch. It checks whether multiple historical batches share the same batch of raw materials. If so, the raw materials in that batch may cause similar defects due to substandard purity or abnormal composition. Finally, it summarizes and organizes the extracted common process equipment identification and common raw material batch information to form a list of potential root causes of defects in the current batch, and marks the degree of correlation between each potential root cause and defects in historical batches.

[0093] As can be seen from the above, this embodiment, when a batch of wafers fails to meet yield standards, can locate historical batches with certain defect similarities by performing a similarity search between the current detection spectrum or comparison results and the historical batch database based on defect distribution patterns, spectral characteristics, and electrical parameter deviation patterns. Furthermore, it can extract common process equipment identifiers or raw material batch information as potential root causes. This process overcomes the limitations of traditional post-event analysis relying on experience-based judgment, shortens the root cause investigation cycle through similarity matching, and provides clues for timely tracing of problems in the process or raw material stages.

[0094] In one embodiment of this application, the spectral similarity retrieval is calculated based on the similarity of defect distribution patterns, spectral features, or electrical parameter deviation patterns, including: Calculate the individual similarity between the current batch and historical batches in terms of defect distribution patterns, spectral characteristics, and electrical parameter deviation patterns; A weight coefficient is assigned to each class of single similarity, where pattern classes that are more associated with potential root causes are assigned a higher weight coefficient; Based on the weight coefficients, various types of single similarity are weighted and fused to obtain a comprehensive similarity score; Based on the comprehensive similarity score, the batch most similar to the current batch is identified from the historical batch database.

[0095] In this embodiment, a single similarity is calculated for the current batch and historical batches across different dimensions. For example, in the defect distribution pattern dimension, the spatial coordinate distribution features of defects on the wafer are extracted, and clustering analysis or spatial distance algorithms are used to calculate the matching degree between the current batch and historical batches in terms of distribution density, aggregation morphology, and regional correlation, thus obtaining the defect distribution pattern similarity. In the spectral feature dimension, the optical detection spectral data of the defect area is preprocessed, such as through noise reduction and baseline correction, and key parameters such as characteristic peak positions and peak intensities are extracted. Cosine similarity or spectral angle mapping algorithms are used to calculate the morphological consistency of the spectral curves, thus obtaining the spectral feature similarity. In the electrical parameter deviation pattern dimension, the electrical parameter deviation values ​​of the chip units are constructed as sequential data, and dynamic time warping or Pearson correlation coefficients are used to analyze the trend consistency and amplitude correlation of the parameter deviations, thus obtaining the electrical parameter deviation pattern similarity.

[0096] Next, a correlation matrix is ​​constructed through historical root cause analysis cases to determine the correspondence between different patterns and root causes. Specifically, if defects are mostly caused by equipment precision issues, such as lithography misalignment, the defect distribution pattern has the highest correlation with the root cause, and its weight coefficient is set to the highest. If defects originate from raw material characteristics, such as wafer impurities, spectral characteristics have a stronger correlation, and the weight coefficient is increased accordingly. If defects are related to process parameter fluctuations, the weight of the electrical parameter deviation pattern is increased. The final weights need to be adjusted through expert experience and data verification to ensure that they match the root cause orientation of the current batch of defects. For example, a batch of chips from a chip factory had circuit misalignment defects. After investigation, 80% of them were caused by lithography misalignment due to decreased positioning precision of the lithography machine. These defects are concentrated at the wafer edge and are radially distributed. The defect distribution pattern has the strongest correlation with the equipment precision root cause, so the first weight is set to the highest at 0.5; the spectral characteristics have no obvious abnormalities, so the second weight is 0.2; and the electrical parameter deviation has an indirect impact, so the third weight is 0.3.

[0097] Secondly, the individual similarities are weighted and fused according to weight coefficients to generate a comprehensive similarity score. The calculation formula is as follows: Overall similarity = Defect distribution pattern similarity × First weight + Spectral feature similarity × Second weight + Electrical parameter deviation pattern similarity × Third weight.

[0098] For example, if the similarity of a certain historical batch in the three dimensions is 0.8, 0.7 and 0.6 respectively, and the weights are 0.5, 0.3 and 0.2 respectively, then the overall similarity is 0.8×0.5+0.7×0.3+0.6×0.2=0.73. The higher the value, the stronger the overall similarity between the two batches.

[0099] Finally, the overall similarity scores of the current batch and all batches in the historical batch database are sorted in descending order, and the top 1-3 batches are selected as the most similar batches from highest to lowest score. If there are batches with the same score, the dimension with the highest weight in the single similarity is further compared, and the batches with higher similarity in that dimension are selected first, so that the screening results can provide the most valuable historical data support for root cause tracing.

[0100] As can be seen from the above, this embodiment calculates the single similarity between the current batch and historical batches from three dimensions: defect distribution pattern, spectral characteristics, and electrical parameter deviation pattern. It also performs weighted fusion based on the correlation between the pattern and potential root causes. This not only achieves a comprehensive consideration of multi-dimensional features, but also highlights key influencing factors through weight settings, making the comprehensive similarity score more in line with the needs of root cause analysis.

[0101] Corresponding to the wafer-level packaging pattern processing method in the above embodiments, Figure 2This is a structural block diagram of a wafer-level packaging pattern processing system provided in one embodiment of this application. For ease of explanation, only the parts relevant to the embodiment of this application are shown. References Figure 2 The wafer-level packaging pattern processing system 20 includes: a pattern receiving and conversion module 21, a standard yield setting module 22, a detection pattern generation module 23, a detection pattern comparison module 24, and an actual yield calculation module 25.

[0102] in, The pattern receiving and conversion module 21 is used to receive incoming material patterns input by customers, and upload them to a designated file server based on customer code and pattern type; at the same time, it converts the incoming material pattern into an internal pattern after binding it with the wafer batch; and generates an internal pattern number based on the customer code, process flow, pattern format and site name of the internal pattern. The standard yield setting module 22 is used to determine the yield threshold of the associated wafer of the internal pattern according to the yield requirements, and to associate and store the yield threshold with the internal pattern number. The detection pattern generation module 23 is used to perform optical detection and electrical testing on the associated wafer to obtain the detection pattern. The detection spectrum comparison module 24 is used to compare the reference spectrum with the detection spectrum to obtain the comparison result; The actual yield calculation module 25 is used to calculate the wafer yield and batch yield based on the comparison results, by statistically analyzing the chip cell defects of the associated wafers. See Figure 3 , Figure 3 This is a schematic block diagram of an electronic device provided according to an embodiment of this application. Figure 3 The electronic device 300 in this embodiment may include one or more processors 301, one or more input devices 302, one or more output devices 303, and one or more memories 304. The processors 301, input devices 302, output devices 303, and memories 304 communicate with each other via a communication bus 305. The memories 304 store computer programs, including program instructions. The processors 301 execute the program instructions stored in the memories 304. Specifically, the processors 301 are configured to invoke the program instructions to perform the functions of the modules in the aforementioned device embodiments, for example... Figure 2 The functions of the spectrum receiving and conversion module 21, the standard yield setting module 22, the detection spectrum generation module 23, the detection spectrum comparison module 24, and the actual yield calculation module 25 are shown.

[0103] It should be understood that, in the embodiments of this application, the processor 301 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0104] Input device 302 may include a touchpad, a fingerprint sensor (for collecting the user's fingerprint information and fingerprint orientation information), a microphone, etc., and output device 303 may include a display (LCD, etc.), a speaker, etc.

[0105] The memory 304 may include read-only memory and random access memory, and provides instructions and data to the processor 301. A portion of the memory 304 may also include non-volatile random access memory. For example, the memory 304 may also store device type information.

[0106] In specific implementations, the processor 301, input device 302, and output device 303 described in the embodiments of this application can execute the implementation methods described in any embodiment of the wafer-level packaging pattern processing method provided in the embodiments of this application, or they can execute the implementation methods of the electronic devices described in the embodiments of this application, which will not be repeated here.

[0107] In another embodiment of this application, a computer-readable storage medium is provided. This computer-readable storage medium stores a computer program, which includes program instructions. When executed by a processor, the program instructions implement all or part of the processes in the methods described above. Alternatively, the computer program can instruct related hardware to complete the process. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include any entity or device capable of carrying computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0108] The computer-readable storage medium can be an internal storage unit of the electronic device in any of the foregoing embodiments, such as a hard disk or memory of the electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device. Furthermore, the computer-readable storage medium can include both internal and external storage units of the electronic device. The computer-readable storage medium is used to store computer programs and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0109] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0110] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the electronic devices and units described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed electronic devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces or units, or it may be an electrical, mechanical, or other form of connection.

[0112] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application, depending on actual needs.

[0113] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0114] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer-level packaging pattern processing method, characterized in that, include: Receive incoming material patterns from customers and upload them to the designated file server based on customer code and pattern type; Simultaneously, the incoming material pattern is bound to the wafer batch and converted into an internal pattern; Based on the customer code, process flow, map format, and site name of the internal map, an internal map number is generated. Based on the yield requirements, determine the yield threshold of the associated wafer of the internal pattern, and store the yield threshold in association with the internal pattern number; Optical and electrical tests were performed on the associated wafer to obtain a detection spectrum; The baseline spectrum is compared with the detected spectrum to obtain the comparison result; Based on the comparison results, the chip cell defect situation of the associated wafer is statistically analyzed, and the wafer yield and batch yield are calculated. The wafer yield and batch yield are compared with the wafer yield threshold and batch yield threshold in the yield compliance threshold, respectively, to obtain the judgment result, and report data corresponding to the internal map number is generated.

2. The wafer-level packaging pattern processing method according to claim 1, characterized in that, The process of performing optical and electrical testing on the associated wafer of the internal spectrum to obtain the detection spectrum includes: Acquire a scanned image of the associated wafer using an optical inspection device, as an optical image; Feature extraction is performed on the optical image, and based on preset optical defect detection rules, defect detection is performed on the identified chip units to generate optical detection results; Electrical response parameters are obtained by applying test signals to test points on the associated wafer using electrical testing equipment. The electrical response parameters are compared with a preset standard to generate electrical test results including the electrical state of each chip unit; the electrical response parameters are obtained by applying test signals to test points on the associated wafer using electrical testing equipment; The optical detection results and the electrical test results are fused to obtain the detection spectrum.

3. The wafer-level packaging pattern processing method according to claim 2, characterized in that, The step of fusing the optical detection results with the electrical test results to obtain the detection spectrum includes: The position coordinates of the chip unit in the optical detection results are mapped and matched with the position coordinates of the chip unit in the electrical test results to obtain the mapping and matching results; Based on the mapping matching result, a status identifier for the chip unit is constructed, the status identifier including the optical status and electrical status of the chip unit; The detection map is generated based on the status identifiers and position coordinates of all chip units.

4. The wafer-level packaging pattern processing method according to claim 1, characterized in that, The reference spectrum includes the standard optical features and standard electrical parameters of the detection spectrum; The step of comparing the reference spectrum with the detected spectrum to obtain the comparison result includes: The detected map and the reference map are registered at the pixel level to obtain a registered map; A pixel-by-pixel difference analysis is performed on the registration map and the reference map to calculate the optical feature difference value of each chip region; The electrical test results in the detection spectrum are numerically compared with the standard electrical parameters in the reference spectrum, and the difference in electrical parameters of each chip unit is calculated. Based on the optical feature difference values ​​and electrical parameter difference values, the defect information of each chip unit on the associated wafer is determined; The comparison results are obtained by summarizing the defect information of all chip units.

5. The wafer-level packaging pattern processing method according to claim 4, characterized in that, The step of determining the defect information of each chip unit on the associated wafer based on the optical feature difference value and the electrical parameter difference value includes: The electrical parameter difference value is compared with a preset first threshold to determine whether the electrical test result of the chip unit is qualified. If the electrical test results are unqualified, the corresponding electrical defect information shall be recorded; Based on the comparison between the optical feature difference value and the preset second threshold, it is determined whether the optical detection result of the chip unit is qualified; If the optical inspection results are unqualified, the optical defect information of the corresponding chip unit is recorded.

6. The wafer-level packaging pattern processing method according to claim 5, characterized in that, Also includes: A training dataset is constructed based on the acquired historical production data. The training dataset includes the differences in optical features and electrical parameters of the chips, as well as the corresponding final defect verification results. Based on the training dataset, an optimization algorithm is used to jointly optimize the first threshold and the second threshold. The objective function of the optimization algorithm is configured to minimize the comprehensive quality loss calculated by weighting the over-kill rate and the under-kill rate. The over-kill rate is the proportion of qualified chips that are mistakenly identified as defective, and the under-kill rate is the proportion of defective chips that are mistakenly identified as qualified. The optimal threshold combination obtained through optimization is used as the threshold optimization parameter to adjust the first threshold and the second threshold.

7. The wafer-level packaging pattern processing method according to claim 1, characterized in that, The step of comparing the wafer yield and batch yield with the wafer yield compliance threshold and batch yield compliance threshold, respectively, to obtain the comparison result includes: If the wafer yield is greater than or equal to its corresponding wafer yield compliance threshold, and the batch yield is greater than or equal to its corresponding batch yield compliance threshold, then the batch wafer is judged to have met the yield standard. Otherwise, the yield of this batch of wafers will be deemed substandard.

8. The wafer-level packaging pattern processing method according to claim 7, characterized in that, Also includes: After determining that the yield rate is below standard based on the judgment result, the chip units identified as defective in the comparison results and their location coordinates are used as the dataset to be reviewed. Based on a preset minor defect rule base, each chip unit in the dataset to be reviewed is reviewed and judged. If the defect information of any chip cell meets any exemption condition in the minor defect rule base, its status is updated from defective to acceptable, and the wafer yield and batch yield are recalculated based on the updated status.

9. The wafer-level packaging pattern processing method according to claim 8, characterized in that, The method, based on a preset minor defect rule base, performs a review and judgment on each chip unit in the dataset to be reviewed, including: Obtain the optical defect information of the dataset to be reviewed, including the defect type, defect size, and defect location; The optical defect information is matched with the exemption conditions in the minor defect rule base; wherein... The exemption conditions include at least one of the following: the defect type is a scratch, and the defect size is less than a first size threshold, and the scratch is located in the dicing area of ​​the chip unit; the defect type is dirt, and the defect size is less than a second size threshold; the defect type is uneven color of the metal layer, and the difference in electrical parameters is within a preset tolerance range; the defect location is located in the non-functional core area of ​​the chip unit, and the defect size is less than a third size threshold.

10. A wafer-level packaging pattern processing system, characterized in that, include: The image receiving and conversion module is used to receive incoming material images input by customers and upload them to the specified file server based on the customer code and image type. Simultaneously, the incoming material pattern is bound to the wafer batch and converted into an internal pattern; based on the customer code, process flow, pattern format and site name of the internal pattern, an internal pattern number is generated; The standard yield setting module is used to determine the yield compliance threshold of the associated wafer of the internal pattern according to the yield requirements, and to associate and store the yield compliance threshold with the internal pattern number. The detection pattern generation module is used to perform optical detection and electrical testing on the associated wafer to obtain a detection pattern. The detection spectrum comparison module is used to compare the reference spectrum with the detection spectrum to obtain the comparison result; The actual yield calculation module is used to calculate the wafer yield and batch yield based on the comparison results, by statistically analyzing the chip unit defects of the associated wafer. The report data generation module is used to compare the wafer yield and batch yield with the wafer yield compliance threshold and batch yield compliance threshold in the yield compliance threshold, respectively, to obtain the judgment result and generate report data corresponding to the internal map number.

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