Adder tree circuit and floating point calculation method

Abstract

The invention discloses an adder tree circuit and a floating point calculation method, and relates to the technical field of chips. The adder tree circuit comprises an analysis circuit used for determining a plurality of floating point input data corresponding to a function operator and analyzing the plurality of floating point input data to obtain indexes and mantissas corresponding to the plurality of floating point input data; wherein the function operator is used for executing additive operation on a plurality of floating point input data; the order matching processing circuit is used for performing order matching on the indexes corresponding to the floating point input data based on the indexes and mantissas corresponding to the floating point input data to obtain mantissas after order matching corresponding to the floating point input data; the additive operation circuit is used for performing additive operation on the mantissa after order based on the plurality of floating point input data to obtain a first operation result; and the normalization processing circuit is used for performing normalization processing on the first operation result to obtain a second operation result. The area overhead of the logic operation circuit can be reduced, and the accuracy of the operation result is ensured.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of chips, and particularly relates to an addition tree circuit and a floating point calculation method. BACKGROUND

[0002] With the increasing application of neural network processors, the neural network processors can be used to run various neural network models. Generally, there are many types of function operators involved in the neural network models, and the logic operation circuit in the neural network processor can support a function operator for summing multiple floating point operands.

[0003] At present, when summing multiple floating point operands, the logic operation circuit in the neural network processor usually adds the multiple floating point operands two by two, resulting in a large area overhead of the logic operation circuit. SUMMARY

[0004] To solve the above technical problems, the present disclosure provides an addition tree circuit and a floating point calculation method, which can reduce the area overhead of the logic operation circuit.

[0005] In a first aspect, the present disclosure provides an addition tree circuit, comprising: an analysis circuit configured to determine multiple floating point input data corresponding to a function operator, and analyze the multiple floating point input data respectively to obtain exponents and mantissas corresponding to the multiple floating point input data respectively; wherein the function operator is configured to perform addition operation on the multiple floating point input data; a scale processing circuit configured to perform scale on the exponents corresponding to the multiple floating point input data respectively based on the exponents and the mantissas corresponding to the multiple floating point input data respectively to obtain scaled mantissas corresponding to the multiple floating point input data respectively; an addition operation circuit configured to perform addition operation on the scaled mantissas corresponding to the multiple floating point input data to obtain a first operation result; and a normalization processing circuit configured to perform normalization processing on the first operation result to obtain a second operation result.

[0006] In a second aspect, the present disclosure provides a floating point calculation method, comprising: determining multiple floating point input data corresponding to a function operator, and analyzing the multiple floating point input data respectively to obtain exponents and mantissas corresponding to the multiple floating point input data respectively; wherein the function operator is configured to perform addition operation on the multiple floating point input data; performing scale on the exponents corresponding to the multiple floating point input data respectively based on the exponents and the mantissas corresponding to the multiple floating point input data respectively to obtain scaled mantissas corresponding to the multiple floating point input data respectively; performing addition operation on the scaled mantissas corresponding to the multiple floating point input data to obtain a first operation result; and performing normalization processing on the first operation result to obtain a second operation result.

[0007] A third aspect of this disclosure provides a neural network processor, including multiple registers and the above-described addition tree circuit, wherein the multiple registers are used to store data during the operation of the addition tree circuit.

[0008] A fourth aspect of this disclosure provides a computer-readable storage medium storing a computer program that is executed by a processor to perform the floating-point calculation method of the second aspect of this disclosure.

[0009] A fifth aspect of this disclosure provides an electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the floating-point calculation method of the second aspect of this disclosure.

[0010] A sixth aspect of this disclosure provides a computer program product that, when executed by an instruction processor, performs the floating-point calculation method proposed in the second aspect of this disclosure.

[0011] The technical solution provided in this disclosure involves determining multiple floating-point input data corresponding to a function operator through a parsing circuit, and parsing each of the multiple floating-point input data to obtain the exponent and mantissa of each of the multiple floating-point input data. Then, in a counterpoint processing circuit, based on the exponents and mantissas of the multiple floating-point input data, the exponents of the multiple floating-point input data are counterpointed to obtain the counterpointed mantissas of the multiple floating-point input data. Afterwards, in an addition operation circuit, addition is performed based on the counterpointed mantissas of the multiple floating-point input data to obtain a first operation result. Finally, a normalization processing circuit normalizes the first operation result to obtain a second operation result. Therefore, this disclosure, when performing addition on multiple floating-point input data, does not require pairwise addition of multiple floating-point operands, which necessitates a normalization process for each pairwise addition. Instead, it can obtain the first operation result by first counterpointing the multiple floating-point input data, and then perform only one normalization process on the first operation result. Therefore, the embodiments of this disclosure can effectively reduce the number of logic operation units that need to be set due to multiple normalization processes, reduce the area overhead of logic operation circuits, and ensure the accuracy of addition operation results. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of an additive tree circuit provided in this disclosure.

[0013] Figure 2 This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0014] Figure 3This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0015] Figure 4 This is a schematic diagram of the floating-point input data alignment process in the adder tree circuit provided in this disclosure.

[0016] Figure 5 This is a schematic diagram of a process for rounding the mantissa of floating-point input data after alignment in the addition tree circuit provided in this disclosure.

[0017] Figure 6 This is a schematic diagram of another process for rounding the mantissa of floating-point input data after alignment in the addition tree circuit provided in this disclosure.

[0018] Figure 7 This is a schematic diagram of the process and result of performing addition on the mantissa of the rounded floating-point input data in the addition tree circuit provided in this disclosure.

[0019] Figure 8 This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0020] Figure 9 This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0021] Figure 10 This is a schematic diagram of another process for rounding the mantissa of floating-point input data after alignment in the addition tree circuit provided in this disclosure.

[0022] Figure 11 This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0023] Figure 12 This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0024] Figure 13 This is a schematic diagram of another additive tree circuit provided in this disclosure.

[0025] Figure 14 This is a flowchart illustrating a floating-point calculation method provided in this disclosure.

[0026] Figure 15 This is a schematic diagram of the structure of a neural network processor provided in this disclosure.

[0027] Figure 16 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0028] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0029] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0030] Application Overview

[0031] When using function operators in a neural network processor to sum multiple floating-point operands, if the number of floating-point operands exceeds two, multiple alignment and normalization processes are usually required, resulting in a large area overhead for the logic operation circuit.

[0032] Taking the Reduce operator as an example, when using the Reduce operator to sum multiple floating-point operands, if the sequence of multiple floating-point operands is {a1, a2, ..., a...}, n Let n be a positive integer and n≥2. First, the first floating-point operand a1 and the second floating-point operand a2 are taken from the sequence. a1 and a2 are aligned, then summed. The sum is then normalized to obtain S1 = spec(a1 + a2), where spec() represents normalization of the floating-point number. Next, the third floating-point operand a3 is taken from the sequence. The sums S1 and a3 are aligned, then summed, and the sum is normalized to obtain S2 = spec(S1 + a3), and so on, until the sum of multiple floating-point operands in the sequence is obtained. n As can be seen from the above process, each pairwise addition requires alignment and normalization. Because this alignment and normalization is necessary for each pairwise addition, complex logic circuits are required to perform the summation of multiple floating-point operands, resulting in a large area overhead for the logic circuits.

[0033] Based on the above, this disclosure provides an addition tree circuit to solve the problem of large area overhead of logic operation circuits when adding multiple floating-point operands pairwise. The addition tree circuit of this disclosure only requires one alignment and normalization process when performing addition operations on multiple floating-point operands to obtain the addition result. This effectively reduces the number of logic operation units required for multiple normalization processes, significantly reduces the area overhead of the logic operation circuit, and ensures the accuracy of the addition result.

[0034] Exemplary System

[0035] Figure 1 This is a schematic diagram of an addition tree circuit provided in this disclosure. Figure 1 As shown, the addition tree circuit 100 includes a parsing circuit 101, an alignment processing circuit 102, an addition operation circuit 103, and a normalization processing circuit 104.

[0036] The parsing circuit 101 is used to determine multiple floating-point input data corresponding to the function operator, and to parse the multiple floating-point input data respectively to obtain the exponent and mantissa corresponding to the multiple floating-point input data; wherein, the function operator is used to perform addition operation on the multiple floating-point input data.

[0037] Function operators can be, for example, Reduce operators, softmax operators, or other operators that can perform addition operations on multiple floating-point operands. This disclosure does not limit the specific type of function operator; the following embodiments use the Reduce operator as an example for illustrative purposes.

[0038] The multiple floating-point input data corresponding to the function operator can be multiple floating-point operands of the input parsing circuit 101. The function operator can be used to perform addition operations on these multiple floating-point operands. Each floating-point operand is one floating-point input data. The number of multiple floating-point input data of the input parsing circuit 101 can exceed two, for example, it can be three, four, 24, or 64, etc. This embodiment does not limit the specific number of multiple floating-point input data; the number of multiple floating-point input data of the input parsing circuit 101 is related to the actual application scenario.

[0039] In binary floating-point systems (such as the IEEE 754 standard), the expression for a floating-point operand is: (-1)^s × 1.M × 2^e, where s is the sign bit, M is the mantissa, and e is the exponent. In this embodiment of the disclosure, the floating-point input data can be in the form of a standard binary floating-point expression.

[0040] In the parsing circuit 101, for any floating-point input data, the floating-point input data represented by the standard binary floating-point number expression can be parsed, and the exponent in the floating-point input data represented by the standard binary floating-point number expression is determined as the exponent corresponding to the floating-point input data, and the mantissa in the floating-point input data represented by the standard binary floating-point number expression is determined as the mantissa corresponding to the floating-point input data.

[0041] For example, the expression of floating-point input data f1 in the binary floating-point system is: (-1)^s1×1.M1×2^e1. The parsing circuit 101 parses f1 and obtains the mantissa M1 and the exponent e1 corresponding to the floating-point input data f1.

[0042] The parsing circuit 101 parses multiple floating-point input data separately, and can obtain the exponent and mantissa corresponding to each floating-point input data.

[0043] The method for parsing floating-point input data shall be set by those skilled in the art according to the actual situation, and the embodiments disclosed herein do not limit this.

[0044] The alignment processing circuit 102 is used to align the exponents corresponding to multiple floating-point input data based on the exponents and mantissas corresponding to the multiple floating-point input data respectively, so as to obtain the aligned mantissas corresponding to the multiple floating-point input data respectively.

[0045] In the alignment processing circuit 102, the multiple exponents corresponding to the multiple floating-point input data are aligned to make the exponents of the multiple floating-point input data the same. Based on the aligned exponents, the mantissa of each floating-point input data is adjusted so that the mantissa of each floating-point input data matches the aligned exponent of the floating-point input data, thus obtaining the aligned mantissa of each floating-point input data.

[0046] For example, let the multiple floating-point input data corresponding to the function operator be {f1, f2, ..., f...} n Taking n as an integer greater than 2 as an example, when summing these n floating-point numbers, the solution can be obtained by analyzing circuit 101 to parse f1 to f2. n The exponent and mantissa of each floating-point number are obtained through the parsing circuit 101. After obtaining the exponent and mantissa of the floating-point numbers through the alignment circuit 102, the alignment circuit 102 performs alignment based on the exponents of each floating-point number, aligning the exponents of the n floating-point numbers and obtaining the aligned mantissa of each floating-point number. It should be noted that the specific circuit structure of the parsing circuit 101 and the alignment circuit 102 is not limited in this embodiment. Any logic circuit that can realize the function of parsing the exponent and mantissa belongs to the parsing circuit 101 in this disclosure, and any logic circuit that can realize the function of alignment belongs to the alignment circuit 102 in this disclosure.

[0047] The addition circuit 103 is used to perform addition operations on the mantissas after multiple floating-point input data to obtain the first operation result.

[0048] After aligning the exponents of multiple floating-point input data once, the mantissas of the aligned floating-point input data can be added by the addition circuit 103 to obtain the result.

[0049] The normalization processing circuit 104 is used to normalize the first calculation result to obtain the second calculation result.

[0050] Since the addition circuit 103 performs addition on the mantissas of multiple floating-point input data after one alignment, after obtaining the first operation result, it is only necessary to perform normalization processing on the first operation result once in the normalization processing circuit 104 to obtain the normalized data corresponding to the first operation result, that is, the second operation result.

[0051] As can be seen from the above process, in the embodiment of this disclosure, only one alignment and one normalization process are required in the process of performing addition on multiple floating-point input data and obtaining the final second operation result, which can reduce the area overhead of the addition tree circuit.

[0052] The addition tree circuit 100 provided in this embodiment parses the exponents and mantissas corresponding to multiple floating-point input data through the parsing circuit 101. Then, the alignment processing circuit 102 aligns the exponents of the multiple floating-point input data. Finally, the addition operation circuit 103 performs addition based on the aligned mantissas of the multiple floating-point input data to obtain a first operation result. Finally, the normalization processing circuit 104 normalizes the first operation result to obtain a second operation result. In the above process of adding multiple floating-point input data, this embodiment does not require normalization for every pairwise addition, thus avoiding multiple normalization processes. Instead, it only requires one alignment and one normalization process to obtain the normalized data of the addition result of multiple floating-point input data. Therefore, this embodiment can effectively reduce the number of logic operation units required for multiple normalization processes, effectively reduce the area overhead of the logic operation circuit, and ensure the accuracy of the addition result.

[0053] In some embodiments, such as Figure 2 As shown, the alignment processing circuit 102 includes: a maximum exponent determination circuit 1021, a difference calculation circuit 1022, and an alignment circuit 1023.

[0054] The maximum exponent determination circuit 1021 is used to determine the maximum exponent from the exponents corresponding to multiple floating-point input data.

[0055] In the maximum exponent determination circuit 1021, the multiple exponents corresponding to the multiple floating-point input data parsed by the parsing circuit 101 are compared one by one, and the maximum exponent is determined among the multiple exponents.

[0056] For example, multiple floating-point input data include f1, f2, f3, ..., f n The multiple floating-point input data correspond one-to-one with the following exponents: e1, e2, e3, ..., e n For e1, e2, ..., e n Compare, if e 1＜ e 2＜ ... ＜ e n Then e n It was determined to be the largest index.

[0057] The difference calculation circuit 1022 is used to calculate the difference between the exponent and the maximum exponent corresponding to multiple floating-point input data.

[0058] Multiple floating-point input data correspond one-to-one with multiple exponents. In the difference calculation circuit 1022, the difference between each of the multiple exponents and the largest exponent is calculated.

[0059] For example, multiple floating-point input data include f1, f2, f3, ..., f n The multiple floating-point input data correspond one-to-one with the following exponents: e1, e2, e3, ..., e n If e n To calculate the maximum exponent, e n The difference between e1 and e1 (e n -e1), calculate e n The difference between e2 and e2 (e n -e2), ..., calculate e n With e n The difference (e) n -e n The difference between the exponent of f1 and the maximum exponent is (e). n The difference between the exponents of -e1 and f2 and the maximum exponent is (e n -e2), ..., f n The difference between the exponent and the maximum exponent is (e n -e n ).

[0060] The alignment circuit 1023 is used to adjust the mantissas of multiple floating-point input data based on the difference between the exponents corresponding to the multiple floating-point input data and the maximum exponent, so as to obtain the aligned mantissas of the multiple floating-point input data.

[0061] For any floating-point input data among multiple floating-point input data, the absolute value of the difference between the exponent corresponding to the floating-point input data and the maximum exponent is determined as the number of right shifts of the mantissa corresponding to the floating-point input data (i.e., the number of decimal points shifted to the left of the mantissa corresponding to the floating-point input data). The decimal point of the mantissa corresponding to the floating-point input data is shifted to the right by the above right shift number to obtain the mantissa corresponding to the exponent after alignment.

[0062] For example, multiple floating-point input data include f1, f2, f3, ..., f n The multiple floating-point input data correspond one-to-one with the following exponents: e1, e2, e3, ..., e n The multiple mantissas corresponding to these multiple floating-point input data are, in order: M1, M2, M3, ..., M n For the above multiple indices e1, e2, e3, ..., e n Perform alignment to obtain the aligned exponent, for example, e. s (e s =max[e1, e2, e3,...,e n ], max[] is the maximum value operation), which adjusts the exponent of each floating-point input data to e. s And based on the exponent e s Adjusting the mantissas M1, M2, M3, ..., M of multiple floating-point input data n This yields the adjusted mantissas M1', M2', M3', ..., M of multiple floating-point input data. n '. Among them, shifting M1 to the right (e s By shifting M2 to the right by -e1 bits, we can obtain M1'. s By using the -e2) bit, we can obtain M2' and so on.

[0063] It should be noted that during the right shift operation, the shifted-out high-order bits are filled with 0s. For the low-order bits of the mantissa, if the right shift operation causes the mantissa to exceed the set bit width, the low-order bits exceeding the set bit width are rounded. The set bit width is greater than the mantissa bit width of the floating-point input data. The set bit width can be determined as follows: Set bit width = Mantissa bit width of floating-point input data + 1 (bit width for hiding 1s) + Maximum value of accumulated error bit width + Maximum value of reserved precision margin bit width; Maximum value of accumulated error bit width = clog2(NUM), where clog2(NUM) represents the logarithm of NUM to base 2, and NUM is the number of floating-point input data points used in the addition operation; The maximum value of the reserved precision margin bit width is a bit width value set according to the maximum precision requirement that the addition tree circuit 100 can achieve, for example, 3.

[0064] likeFigure 4 As shown, taking floating-point number f1 as FP24, the mantissa M1 of f1 as 1100000100000011, the first 1 in M1 is a hidden 1, the cumulative error bit width is 6, the maximum bit width for the reserved precision margin is 3, and the right shift of M1 during the alignment process is 12 bits. See [link to relevant documentation] Figure 4 As shown, after shifting M1 right by 12 bits, some of the lower bits of M1 (see...) Figure 4 In the right shift result shown, the low-order part exceeding the set bit width exceeds the set bit width. The low-order part exceeding the set bit width in M1 is rounded, resulting in the mantissa M1' after f1 alignment as: 000000000001100000100000. The rounding method for the low-order part exceeding the set bit width can be, for example, rounding to the nearest integer, rounding up, rounding down, or rounding to the nearest even number, etc. This embodiment does not limit the specific method used.

[0065] based on Figure 2 The alignment processing circuit 102 shown can perform alignment on multiple floating-point input data once through the maximum exponent determination circuit 1021, the difference calculation circuit 1022 and the alignment circuit 1023, effectively reducing the area overhead of the logic operation circuit.

[0066] In some embodiments, such as Figure 3 As shown, the addition circuit 103 may include: a first rounding circuit 1031, a first conversion circuit 1032, a first addition circuit 1033, and a second conversion circuit 1034.

[0067] The first rounding circuit 1031 is used to round the mantissas of multiple floating-point input data after alignment, so as to obtain the rounded mantissas of the multiple floating-point input data respectively.

[0068] After obtaining the mantissas of the aligned exponents of multiple floating-point input data, the significant bit width of the target floating-point input data can be determined based on the mantissa of the target floating-point input data corresponding to the largest exponent among the multiple floating-point input data. Then, based on the significant bit width of the target floating-point input data, the rounding portions of the other floating-point input data (excluding the target floating-point input data) are determined. Rounding is then performed on these rounding portions to obtain the rounded mantissas of the multiple floating-point input data. Specifically, the significant bit width of the floating-point input data = mantissa bit width + 1 (bit width for hiding 1s) + 1 (sign bit width). The rounded mantissa of the target floating-point input data is the aligned exponent of the target floating-point input data.

[0069] For example, taking the addition operation with 64 floating-point input data as an example, such as Figure 5As shown in (a), multiple floating-point input data f1, f2, f3, ..., f 64 For example, in FP24, the target floating-point input data corresponding to the maximum exponent is f1, the maximum bit width for cumulative error is 6, and the maximum bit width for reserved precision margin is 3. f1, f2, f3, ..., f 64 The mantissa width is 15, the significant digit width of f1 is 17, and for f1, f2, f3, ..., f... 64 After performing alignment, due to the fact that f2, f3, ..., f 64 The last digits were shifted to the right, therefore f2, f3, ..., f 64 A portion of the last digit will be located to the right of the last digit of f1. This portion is defined as the part to be rounded, such as... Figure 5 (a) shows the rounding parts of f2, f3, ..., f 64 The part to be rounded. Where f 64 The D part in the equation is f when the order is equal. 64 The portion of the mantissa exceeding the set bit width has already been rounded off during index alignment, therefore f 64 The corresponding mantissa after alignment is the mantissa after rounding the D part. Based on this mantissa, we get: Figure 5 f shown in (a) 64 The part to be rounded. For f2, f3, ..., f 64 The unrounded portion of the decimal part is rounded to obtain the following result: Figure 5 The f1, f2, f3, ..., f shown in (b) n The corresponding rounded mantissas are respectively, where the rounded mantissa of f1 is the same as the mantissa of f1 after alignment.

[0070] It should be noted that in this embodiment, the maximum value of the cumulative error width is determined based on the number of floating-point input data used in the addition operation. That is, when the number of floating-point input data used in the addition operation is fixed, the maximum value of the cumulative error width is a fixed value. For example, if the number of floating-point input data used in the addition operation is 64, the maximum value of the cumulative error width = clog2(NUM) = 6; if the number of floating-point input data used in the addition operation is 32, the maximum value of the cumulative error width = clog2(NUM) = 5. With the maximum value of the cumulative error determined, the user can flexibly set the size of the cumulative error width within the range of 0 to the maximum value of the cumulative error width according to the actual accuracy requirements. For example, if the maximum value of the cumulative error width is 6, the user can set the size of the cumulative error width to 0, 1, 2, 3, 4, 5, or 6 according to the actual accuracy requirements. The user-set value of the cumulative error width is used as the set value of the cumulative error width. Different set values ​​of the cumulative error width correspond to different accuracies; the larger the set value of the cumulative error width, the higher the accuracy of the subsequent first calculation result.

[0071] When the error accumulation bit width is set to its maximum value, a higher precision addition result can be obtained by setting a reserved precision margin bit width. The maximum value of the reserved precision margin bit width is fixed, but the bit width can be flexibly set by the user according to the actual calculation precision requirements. For example, if the maximum value of the reserved precision margin bit width is 3, and the error accumulation bit width is set to its maximum value, the reserved precision margin bit width can be set to 1, 2, or 3 to further improve calculation precision. When only the error accumulation bit width setting needs to be adjusted to adjust the calculation result precision, the reserved precision margin bit width can be set to 0.

[0072] Figure 5The examples shown in (a) and (b) are the process of rounding the mantissas of multiple floating-point input data when both the error accumulation bit width setting and the reserved precision margin bit width are set to 0, to obtain the rounded mantissas of multiple floating-point input data respectively. When the set value of the cumulative error bit width is not 0, or when both the set value of the cumulative error bit width and the bit width of the reserved precision margin are not 0, the mantissas of the multiple floating-point input data are rounded to obtain the rounded mantissas of the multiple floating-point input data respectively. The process is as follows: After obtaining the mantissas of the multiple floating-point input data respectively, the effective bit width of the target floating-point input data can be determined according to the mantissa of the target floating-point input data corresponding to the largest exponent among the multiple floating-point input data. Then, according to the effective bit width of the target floating-point input data and the set value of the cumulative error bit width, the parts of the other floating-point input data besides the target floating-point input data are determined to be rounded. The parts of the other floating-point input data besides the target floating-point input data are rounded to obtain the rounded mantissas of the multiple floating-point input data respectively. The rounded mantissa of the target floating-point input data is the mantissa of the target floating-point input data after alignment.

[0073] For example, taking the addition operation with 64 floating-point input data as an example, such as Figure 6 As shown in (a), multiple floating-point input data f1, f2, f3, ..., f 64 For FP24, the target floating-point input data corresponding to the maximum exponent is f1, and the maximum bit width for the reserved precision margin is 3. In this case, f1, f2, f3, ..., f 64 The mantissa bit width is 15, the significant bit width of f1 is 17, and the maximum value of the cumulative error bit width is 6. If the cumulative error bit width is set to 4, and the bit width reserved for precision margin is 0, then for f1, f2, f3, ..., f n After performing alignment, due to the fact that f2, f3, ..., f 64 The last digits were shifted to the right, therefore f2, f3, ..., f 64 A portion of the mantissa after alignment will exceed the sum of the set value of the cumulative error bit width and the significant bit width of the mantissa in f1. This portion is defined as the part to be rounded, such as... Figure 6 (a) shows the rounding parts of f2, f3, ..., f 64 The part to be rounded, where f 64 The D part in the equation is f when the order is equal. 64 The portion of the mantissa exceeding the set bit width has already been rounded off during index alignment, therefore f 64The corresponding mantissa after alignment is the mantissa after rounding the D part. Based on this mantissa, we get: Figure 6 f shown in (a) 64 The part to be rounded. For f2, f3, ..., f 64 The unrounded portion of the decimal part is rounded to obtain the following result: Figure 6 The f1, f2, f3, ..., f shown in (b) 64 The corresponding rounded mantissas are respectively, where the rounded mantissa of f1 is the same as the mantissa of f1 after alignment.

[0074] Will Figure 6 The f1, f2, f3, ..., f shown in (b) 64 The corresponding rounded digits and Figure 5 The f1, f2, f3, ..., f shown in (b) 64 By comparing the rounded digits respectively, we can see that, as... Figure 6 The set value of the cumulative error bit width in (a) and (b) is greater than Figure 5 The set value of the cumulative error bit width in (a) and (b) is therefore... Figure 6 f2, f3, ..., f obtained from (b) 64 The corresponding rounded mantissas are more accurate than those of the rounded mantissas. Figure 5 f2, f3, ..., f obtained from (b) 64 The corresponding rounded digits.

[0075] When rounding the mantissas corresponding to multiple floating-point input data, there can be various rounding methods, such as: rounding to the nearest whole number, rounding up, rounding down, or banker's rounding (rounding to the nearest even number), etc. The embodiments of this disclosure do not limit the rounding method.

[0076] The first conversion circuit 1032 is used to convert the rounded mantissas of multiple floating-point input data into two's complement, so as to obtain the mantissas of the multiple floating-point input data after two's complement conversion.

[0077] To facilitate subsequent addition operations, the mantissa of each floating-point input data is converted to two's complement, thus obtaining the mantissa of each floating-point input data after two's complement conversion.

[0078] For example, based on Figure 5 The multiple floating-point input data f1, f2, f3, ..., f shown in (a) 64 The rounded-off digits will be Figure 5 The mantissa of f1 after rounding, as shown in (a), is converted to two's complement to obtain the following:Figure 7 The two's complement of the rounded mantissa of f1 shown; Figure 5 The mantissa of f2 after rounding, as shown in (a), is converted to two's complement to obtain the following: Figure 7 The rounded mantissa of f2, as shown, is used as the complement, and so on, until multiple floating-point input data f1, f2, f3, ..., f are obtained. 64 The two's complement of the corresponding rounded mantissa.

[0079] The first adder circuit 1033 is used to add the mantissas of multiple floating-point input data after performing two's complement conversion, and obtain the third operation result.

[0080] After converting multiple floating-point input data to two's complement, the corresponding mantissas are added to obtain the third result.

[0081] For example, please continue to see Figure 7 After obtaining f1, f2, f3, ..., f 64 After obtaining the two's complement of the corresponding rounded mantissas, for f1, f2, f3, ..., f 64 The two's complement of the rounded mantissas is added to obtain the third result. The mantissa of the third result includes a protection bit, a mantissa bit, an error accumulation bit, and a reserved precision margin. The width of the protection bit of the third result is equal to clog2(NUM)-1. When adding 64 floating-point input data, the width of the protection bit of the third result is clog2(64)-1=5, i.e., as shown below. Figure 7 The protection bit width of the third operation result shown is 5 (each box can store one binary number, and the width of one box is 1). The protection bit is set to prevent carry overflow in the result of adding NUM floating-point input data. The protection bit is set to store the carry data overflowing after adding NUM floating-point input data. The width of the mantissa bit of the third operation result = the mantissa bit width of the floating-point input data + 1 (hidden 1) + 1 (sign bit). For example Figure 7 The floating-point input data shown is FP24, and the mantissa width of the floating-point input data is 15 bits. Figure 7 The bit width of the mantissa of the third operation result shown is 17. Figure 7 The number of floating-point input data shown is 64, then Figure 7 The maximum bit width of the cumulative error bits in the third operation result shown is clog2(NUM) = 6. The maximum bit width for the reserved precision margin is 3.

[0082] The second conversion circuit 1034 is used to convert the third operation result into the original code to obtain the first operation result.

[0083] Since the mantissas of multiple floating-point input data are converted into two's complement form in the first conversion circuit 1032, the third operation result is in two's complement form. In this case, the second conversion circuit 1034 converts the third operation result back to its original code to obtain the first operation result. Figure 7 As shown, the structure of the mantissa portion of the first operation result is the same as the structure of the mantissa portion of the third operation result.

[0084] The accuracy of the first calculation result is analyzed below. See [link / reference] Figure 7 The mantissa width of the target floating-point input data f1 corresponding to the largest exponent among multiple floating-point input data is 16 (with the addition of 1 bit width corresponding to the hidden 1). The mantissa width of the first operation result is 17. The mantissa width of the first operation result is greater than the mantissa width of the target floating-point input data f1. The error of the first operation result is less than the least significant unit (Unit of Last Position, ULP) of the target floating-point input data. The error of each floating-point input data is less than the least significant unit (Unit of Last Position, ULP) / 2*clog2(NUM) of the target floating-point input data.

[0085] Based on such Figure 3 The addition circuit 103 shown can round the mantissas of multiple floating-point input data after alignment, obtaining the rounded mantissas of each floating-point input data. Then, it converts these rounded mantissas to two's complement before performing addition to obtain the third result. Finally, it converts the third result back to its original code to obtain the first result. By rounding the mantissas of multiple floating-point input data, the number of data points requiring addition is reduced, thus reducing the area overhead of the logic circuit and ensuring the accuracy of the addition result.

[0086] In some embodiments, such as Figure 8 As shown, the first adder circuit 1033 includes a first sub-adder circuit 10331 and a second sub-adder circuit 10332.

[0087] The first sub-adder circuit 10331 is used to add the mantissas of multiple floating-point input data after two's complement conversion to obtain the first sub-operation result and the second sub-operation result.

[0088] The first sub-adder circuit 10331 can be a hardware adder structure capable of accelerating the addition of multiple binary numbers in parallel, such as a Wallace tree. The first sub-operation result and the second sub-operation result are two intermediate results obtained by performing addition operations on the mantissas (which are the mantissas after two's complement conversion) corresponding to multiple floating-point input data.

[0089] The result of the first sub-operation can be the cumulative sum obtained by adding the mantissas of multiple floating-point input data after two's complement conversion. The result of the second sub-operation can be the carry sum at each position obtained by adding the mantissas of multiple floating-point input data after two's complement conversion. The cumulative sum refers to the portion excluding carry generated when adding multiple numbers bit by bit. The carry sum at each position refers to the sum of the carry generated when adding at that position and the carry passed from the lower bits to that position.

[0090] The second sub-adder circuit 10332 is used to add the results of the first and second sub-operations to obtain the third operation result.

[0091] The second sub-adder circuit 10332 adds the first sub-operation result and the second sub-operation result together to obtain the third operation result.

[0092] In this embodiment of the present disclosure, the addition operation of multiple floating-point input data can be accelerated and parallelized through the first sub-adder circuit 10331 and the second sub-adder circuit 10332, which effectively improves the efficiency of addition operation, reduces the total time required for addition operation, and reduces latency.

[0093] In some embodiments, such as Figure 9 As shown, the addition circuit 103 includes: a second rounding circuit 1035, a third conversion circuit 1036, a fourth conversion circuit 1037, a second addition circuit 1038, and a fifth conversion circuit 1039.

[0094] The second rounding circuit 1035 is used to round the mantissas of multiple floating-point input data after they have been aligned to obtain the truncated data and rounded carry data corresponding to the multiple floating-point input data.

[0095] After obtaining the mantissas of the aligned exponents of multiple floating-point input data, the effective bit width of the target floating-point input data can be determined based on the mantissa of the target floating-point input data corresponding to the largest exponent among the multiple floating-point input data. Then, based on the effective bit width of the target floating-point input data, the rounding portions of the other floating-point input data (excluding the target floating-point input data) are determined. For any floating-point input data (excluding the target floating-point input data), the rounding portion is truncated from the aligned exponent of that floating-point input data to obtain the truncated data. The rounding portion of the floating-point input data is then rounded to obtain the round-in data. The truncated data corresponding to the target floating-point input data is the aligned exponent of the target floating-point input data, and the round-in data of the target floating-point input data is 0.

[0096] For example, taking the addition operation with 64 floating-point input data as an example, such as Figure 10 As shown in (a), multiple floating-point input data f1, f2, f3, ..., f 64 For FP24, the target floating-point input data corresponding to the maximum exponent is f1, where f1 is 1010011000000000. The maximum bit width for cumulative error is 6, and the maximum bit width for reserved precision margin is 3. In this case, f1, f2, f3, ..., f 64 The mantissa width is 15, the significant digit width of f1 is 17, and for f1, f2, f3, ..., f... 64 After performing alignment, due to the fact that f2, f3, ..., f 64 The last digits were shifted to the right, therefore f2, f3, ..., f 64 A portion of the last digit will be located to the right of the last digit of f1. This portion is defined as the part to be rounded, such as... Figure 5 In (a) above, the mantissa of f2 after right shifting is 000001100100110111010, and the part to be rounded is 11010; the mantissa of f3 after right shifting is 0000000001100000010101000, and the part to be rounded is 010101000; f 64 The mantissa shifted to the right is 0000000000001000000011000001, f 64 The part to be rounded is 000001100. For example... Figure 10As shown in (b), the rounding part 11010 in the result of right-shifting the mantissa of f2 is truncated, resulting in 0000011001001101, which is the truncated data of f2; the rounding part 010101000 in the result of right-shifting the mantissa of f3 is truncated, resulting in 0000000001100000, which is the truncated data of f3; and so on, until the f2 mantissa is truncated. 64 After right-shifting the mantissa, the rounding part 010101000 is truncated, resulting in 0000000000000100, 00000000000000100, which is f. 64 The truncated data.

[0097] For any floating-point input data among multiple floating-point input data, the mantissa to be rounded is rounded. Based on the rounding result, a carry-over is determined. If a carry-over occurs, the carry-over data is 1; otherwise, the carry-over data is 0. Please continue to the next step. Figure 10 If the rounding method is rounding to the nearest whole number, then when rounding the part to be rounded in f2, 11010, is rounded, a carry-in will occur, so the carry-in data for f2 is 1; when rounding the part to be rounded in f3, 010101000, is rounded, no carry-in will occur, so the carry-in data for f3 is 0; and so on. 64 The part to be rounded, 000001100, is rounded. Since rounding 000001100 does not produce a carry, the result is f. 64 The rounded-over value is 0.

[0098] Figure 10The examples shown in (a) and (b) illustrate the process of rounding the mantissas of multiple floating-point input data after alignment, when both the error accumulation bit width setting and the reserved precision margin bit width are set to 0, to obtain the truncated and rounded data corresponding to the multiple floating-point input data. The process of rounding the mantissas of multiple floating-point input data after alignment, when the error accumulation bit width setting is not 0, or when both the error accumulation bit width setting and the reserved precision margin bit width are not 0, to obtain the truncated and rounded data corresponding to the multiple floating-point input data, can be as follows: After obtaining the mantissas of the multiple floating-point input data after alignment, the effective bit width of the target floating-point input data can be determined based on the mantissa of the target floating-point input data corresponding to the largest exponent among the multiple floating-point input data. Then... Based on the set values ​​of the significant bit width and the cumulative error bit width of the target floating-point input data, the rounding portions of the other floating-point input data (excluding the target floating-point input data) are determined. Rounding processing is performed on these other floating-point input data to obtain the truncated data and rounded-up data corresponding to each of the multiple floating-point input data sets. The truncated data corresponding to the target floating-point input data is the mantissa after alignment, and the rounded-up data is 0. If the set value of the cumulative error bit width is not 0, or if both the set value of the cumulative error bit width and the reserved precision margin bit width are not 0, the precision of the truncated data corresponding to the multiple floating-point input data sets obtained is higher than the precision of the truncated data sets obtained when both the set value of the cumulative error bit width and the reserved precision margin bit width are 0.

[0099] The third conversion circuit 1036 is used to process the truncated data corresponding to the multiple floating-point input data based on the symbols corresponding to the multiple floating-point input data respectively, and to determine the truncated data corresponding to the multiple floating-point input data after processing.

[0100] For any floating-point input data among multiple floating-point input data, the sign of the floating-point input data determines whether to perform inversion processing. If the sign of the floating-point input data is positive, the corresponding truncated data is not inverted, and the truncated data is directly determined as the truncated data corresponding to the processed floating-point input data. If the sign of the floating-point input data is negative, the corresponding truncated data is inverted, that is, each bit of the truncated data is inverted to obtain the inverted data, and this inverted data is determined as the truncated data corresponding to the processed floating-point input data.

[0101] The sign bit of the floating-point input data stores the sign of the floating-point input data. A sign bit of 0 indicates that the floating-point input data is positive, i.e., the sign of the floating-point input data is "+"; a sign bit of 1 indicates that the floating-point input data is negative, i.e., the sign of the floating-point input data is "-". In this embodiment of the disclosure, the sign of the floating-point input data can be determined based on the data stored in the sign bit of the floating-point input data.

[0102] For example, such as Figure 10 As shown in (b), the sign bit of f1 is 0, meaning the sign of f1 is negative. In this case, the truncated data corresponding to f1 is inverted, that is, each bit of the truncated data 1010011000000000 is inverted to obtain 0101100111111111, which is the truncated data corresponding to f1 after processing. The sign bit of f2 is 1, meaning the sign of f2 is positive. In this case, the truncated data corresponding to f2 is not inverted, and the truncated data 0000011001001101 is directly determined as the truncated data corresponding to f2 after processing.

[0103] The fourth conversion circuit 1037 is used to obtain the sum of multiple floating-point input data based on the signs corresponding to the multiple floating-point input data and the round-off data corresponding to the multiple floating-point input data.

[0104] For any floating-point input data among multiple floating-point input data, the corresponding data to be summed can be determined in the following way.

[0105] If the sign of the floating-point input data is negative and the round-off data corresponding to the floating-point input data is 1, then the data to be summed is 0.

[0106] It should be noted that when the floating-point input data is negative, adding 1 to the mantissa of the floating-point input data, and then converting the result to two's complement, yields the result of directly inverting each bit of the mantissa of the floating-point input data. For example, if the mantissa of a floating-point input data in binary is 0000000000000100, adding 1 to 0000000000000100 gives 00000000000000101. Converting 0000000000000101 to two's complement gives 11111111111111011. 1111111111111011 is the result of directly inverting each bit of the mantissa 0000000000000100 of the floating-point input data. Therefore, in this embodiment of the present disclosure, for floating-point input data with a negative sign (i.e., a sign bit of 1), when rounding the truncated data corresponding to the floating-point input data, if the carry-in during rounding is 1 (i.e., the carry-in data during rounding is 1), the truncated data corresponding to the floating-point input data can be directly inverted. The inverted result is the carry-in of the truncated data corresponding to the floating-point input data, and then the result after the carry-in is converted to the two's complement result. In this case, after inverting the truncated data corresponding to the floating-point input data with a negative sign, the data to be summed is set to 0 (i.e., only inversion is performed, without adding a carry-in of 1). This eliminates the need to carry-in the truncated data corresponding to the floating-point input data and perform the addition operation when converting to two's complement, further improving the operation speed.

[0107] If the sign of the floating-point input data is negative and the round-off data is 0, then the data to be summed is 1. In other words, if the sign of the floating-point input data is negative and the round-off data is 0, it means that no truncation 1 was added to the truncated data, and the data to be summed is set to 1. This data to be summed is the 1 that needs to be added during the inversion and addition process when converting the floating-point input data to two's complement.

[0108] If the sign of the floating-point input data is positive and the carry-in data is 1, then the data to be summed is 1. In other words, if the sign of the floating-point input data is positive and the carry-in data is 1, then the data to be summed is set to 1, which is the carry-in 1.

[0109] If the sign of the floating-point input data is positive and the carry-in value is 0, then the data to be summed is 0. In other words, if the sign of the floating-point input data is positive and the carry-in value is 0, it means that neither carry nor inversion plus 1 is needed, so the data to be summed is set to 0.

[0110] The second adder circuit 1038 is used to obtain the fourth operation result based on the truncated data corresponding to the multiple floating-point input data after processing and the data to be summed corresponding to the multiple floating-point input data.

[0111] The target sum is determined from the sums corresponding to the multiple floating-point input data, where the target sum is 1. The truncated data corresponding to the processed multiple floating-point input data and all the target sums are added together to obtain the fourth operation result.

[0112] In the second adder circuit 1038, only the data to be summed that is 1 needs to be added. Compared with the method of directly performing two's complement conversion, the amount of data to be added by 1 can be effectively reduced.

[0113] The fifth conversion circuit 1039 is used to convert the result of the fourth operation into the original code to obtain the result of the first operation.

[0114] The fourth operation result obtained by the second adder circuit 1038 is the two's complement form of the binary number. Therefore, in the fifth conversion circuit 1039, the fourth operation result is converted into the original code to obtain the first operation result.

[0115] In this embodiment of the disclosure, the second rounding circuit 1035, the third conversion circuit 1036, the fourth conversion circuit 1037, and the second adder circuit 1038 can eliminate the need to carry over 1 to the truncated data corresponding to negative floating-point input data and to perform the addition operation when converting negative floating-point input data to two's complement, thereby further reducing the computational overhead, further reducing the area overhead of the logic operation circuit, and improving the operation speed.

[0116] In some embodiments, such as Figure 11 As shown, the second adder circuit 1038 may include a third sub-adder circuit 10381, a fourth sub-adder circuit 10382, and a fifth sub-adder circuit 10383.

[0117] The third sub-adder circuit 10381 is used to add the truncated data corresponding to multiple floating-point input data after processing, so as to obtain the third sub-operation result and the fourth sub-operation result.

[0118] The third sub-adder circuit 10381 can be a hardware adder structure capable of accelerating the addition of multiple binary numbers in parallel, such as a Wallace tree. The results of the third and fourth sub-operations are two intermediate results obtained by performing addition operations on the truncated data corresponding to the processed multiple floating-point input data (the truncated data corresponding to the processed floating-point input data with positive signs is itself, and the truncated data corresponding to the processed floating-point input data with negative signs is the inverted result obtained by inverting each bit).

[0119] The result of the third sub-operation can be the cumulative sum obtained by performing addition operations on the truncated data corresponding to the multiple floating-point input data after processing. The result of the fourth sub-operation can be the carry sum at each position obtained by performing addition operations on the truncated data corresponding to the multiple floating-point input data after processing. The cumulative sum and carry sum can be referred to the description in the above embodiments, and will not be repeated here.

[0120] The fourth sub-adder circuit 10382 is used to add the corresponding data to be summed from multiple floating-point input data to obtain the sum of the data to be summed.

[0121] The fifth sub-adder circuit 10383 is used to add the sum of the third sub-operation result, the fourth sub-operation result, and the data to be summed to obtain the fourth operation result.

[0122] The fourth sub-adder circuit 10382 and the fifth sub-adder circuit 10383 can be hardware adder structures capable of accelerating the addition of multiple binary numbers in parallel, such as Wallace trees, or other adders. This disclosure does not limit the specific adder.

[0123] In this embodiment of the disclosure, the third sub-adder circuit 10381, the fourth sub-adder circuit 10382, and the fifth sub-adder circuit 10383 enable the second adder circuit 1038 to perform parallel processing on the addition of multiple floating-point input data, effectively improving the efficiency of addition operations, reducing the total time required for addition operations, and reducing latency.

[0124] In some embodiments, such as Figure 12 As shown, the addition tree circuit 100 also includes a judgment circuit 105 and a selector 106.

[0125] The judgment circuit 105 is used to output a first signal in response to the presence of preset data among multiple floating-point input data; or to output a second signal in response to the absence of preset data among multiple floating-point input data.

[0126] The preset data could be, for example, infinity. If infinity exists among the multiple floating-point input data, the result of the addition operation will inevitably be infinity. In this case, a first signal can be output so that the subsequent processor (i.e., selector 106) can directly state the result of the addition operation based on the first signal. If infinity does not exist among the multiple floating-point input data, then addition is required, and a second signal is output so that the subsequent processor (i.e., selector 106) can determine whether to perform the addition operation on the multiple floating-point input data based on the second signal.

[0127] Selector 106 is used to output preset data based on a first signal, or to output a second calculation result based on a second signal.

[0128] By using the judgment circuit 105 and the selector 106, the system can directly identify cases where preset data is present in multiple floating-point input data, thus eliminating the need for addition operations. If preset data is detected, the system outputs the calculation result directly without performing addition operations. Only if preset data is not detected will the system perform addition operations on the multiple floating-point input data, thereby further saving computational overhead and improving computational efficiency.

[0129] In some embodiments, such as Figure 13 As shown, the adder tree circuit also includes an input processing circuit 1001.

[0130] The input processing circuit 1001 is used to legalize multiple input parameters corresponding to the function operator to obtain multiple floating-point input data.

[0131] The multiple input parameters corresponding to the function operator are legalized by converting each input parameter into a form expressed in a binary floating-point system (such as the IEEE 754 standard), such as (-1)^s×1.M×2^e, where s is the sign bit, M is the mantissa, and e is the exponent, thus obtaining the floating-point input data corresponding to the input parameter.

[0132] The input processing circuit 1001 can legalize illegally represented input parameters so that the form of multiple input parameters is consistent and legal when performing addition operations in the future, thus ensuring the efficiency of the processing.

[0133] The accuracy of the second calculation result obtained in the embodiments of this disclosure will be described below.

[0134] In this embodiment of the disclosure, see Figure 7 As shown, the mantissa bit width of the first operation result is greater than the mantissa bit width of the target floating-point input data (the floating-point input data with the largest exponent among multiple floating-point input data) + 1 (hidden 1), and the error of the first operation result is greater than the ULP of the target floating-point input data.

[0135] The error accumulation bit width setting can be adjusted according to actual conditions. When the error accumulation bit width setting is not 0, for example, if the error accumulation bit width setting is 6, the error of the first calculation result is equal to ULP / 64 of the target floating-point input data (10000002 = 64 if there is a carry-over in the error accumulation bit). 10 ).

[0136] The bit width for the reserved precision margin can be set according to the actual situation. For example, the bit width for cumulative error can be set to 6, and the bit width for the reserved precision margin can be set to 3. The error of the first calculation result is equal to ULP / 512 of the target floating-point input data.

[0137] Since the second result is the result of normalizing the first result, the error of the second result is the same as the error of the first result.

[0138] Therefore, it can be seen that the error of the second calculation result in the embodiments of this disclosure is less than the ULP of the floating-point input data with the largest exponent among the multiple floating-point input data, thereby ensuring that the final calculation result has high accuracy.

[0139] In some embodiments, the relevant parameters of the floating-point numbers of the input and output of the adder tree circuit 100 can be found in Table 1, where SLK-W is the maximum value of the bit width reserved for precision margin.

[0140] Table 1

[0141]

[0142] Exemplary methods

[0143] Figure 14 A floating-point calculation method provided in this disclosure embodiment, such as Figure 14 As shown, the method includes the following steps 1201 to 1204.

[0144] Step 1201: Determine the multiple floating-point input data of the function operator, and parse the multiple floating-point input data respectively to obtain the exponent and mantissa corresponding to the multiple floating-point input data; wherein, the function operator is used to perform addition operation on the multiple floating-point input data;

[0145] Step 1202: Based on the exponents and mantissas corresponding to multiple floating-point input data respectively, the exponents corresponding to the multiple floating-point input data are aligned to obtain the aligned mantissas corresponding to the multiple floating-point input data respectively.

[0146] Step 1203: Perform addition operations on the mantissas of the multiple floating-point input data after alignment to obtain the first operation result;

[0147] Step 1204: Normalize the first calculation result to obtain the second calculation result.

[0148] The floating-point arithmetic method provided in this disclosure can determine multiple floating-point input data corresponding to a function operator, parse each of the multiple floating-point input data to obtain the exponent and mantissa of each of the multiple floating-point input data; then, based on the exponent and mantissa of each of the multiple floating-point input data, the exponents of each of the multiple floating-point input data are aligned to obtain the aligned mantissas of each of the multiple floating-point input data; then, an addition operation is performed based on the aligned mantissas of the multiple floating-point input data to obtain a first operation result; finally, the first operation result is normalized to obtain a second operation result. In the above process of adding multiple floating-point input data, this disclosure embodiment does not require normalization processing every time they are added pairwise, thus avoiding the need for multiple normalization processes. Instead, only one normalization process is required to obtain the normalized data of the addition operation result of multiple floating-point input data. In this case, this disclosure embodiment can effectively reduce the number of logic operation units required due to multiple normalization processes, effectively reduce the area overhead of the logic operation circuit, and ensure the accuracy of the addition operation result.

[0149] In some embodiments, when aligning the exponents of multiple floating-point input data based on their respective exponents and mantissas to obtain the aligned mantissas, the method includes:

[0150] Determine the largest exponent from the exponents corresponding to multiple floating-point input data;

[0151] Calculate the difference between the exponent and the maximum exponent for each of the multiple floating-point input data.

[0152] Based on the difference between the exponent and the maximum exponent corresponding to multiple floating-point input data, the mantissas corresponding to the multiple floating-point input data are adjusted to obtain the mantissas after alignment for the multiple floating-point input data.

[0153] In some embodiments, an addition operation is performed on the mantissa after the exponentiation of multiple floating-point input data to obtain a first operation result, including:

[0154] Round the mantissas of the multiple floating-point input data respectively to obtain the rounded mantissas of the multiple floating-point input data respectively.

[0155] Convert the rounded mantissas of multiple floating-point input data into two's complement to obtain the mantissas of the multiple floating-point input data after two's complement conversion.

[0156] After converting multiple floating-point input data to two's complement, the corresponding mantissas are added together to obtain the third operation result;

[0157] Convert the result of the third operation to its original code to obtain the result of the first operation.

[0158] In some embodiments, after converting multiple floating-point input data to two's complement, the corresponding mantissas are added together to obtain a third operation result, including:

[0159] After converting multiple floating-point input data to two's complement, the corresponding mantissas are added together to obtain the result of the first sub-operation and the result of the second sub-operation.

[0160] The result of the first suboperation is added to the result of the second suboperation to obtain the result of the third operation.

[0161] In some embodiments, an addition operation is performed on the mantissa after the exponentiation of multiple floating-point input data to obtain a first operation result, including:

[0162] The mantissas of multiple floating-point input data are rounded after the order is adjusted to obtain the truncated data and rounded carry data corresponding to the multiple floating-point input data respectively.

[0163] Based on the symbols corresponding to multiple floating-point input data, the truncated data corresponding to the multiple floating-point input data are processed to determine the truncated data corresponding to the multiple floating-point input data after processing.

[0164] Based on the signs corresponding to multiple floating-point input data and the rounding carry data corresponding to multiple floating-point input data, the sum data to be calculated corresponding to multiple floating-point input data is obtained.

[0165] Based on the truncated data corresponding to the processing of multiple floating-point input data and the data to be summed corresponding to the multiple floating-point input data, the fourth operation result is obtained;

[0166] Convert the result of the fourth operation to its original code to obtain the result of the first operation.

[0167] In some embodiments, a fourth operation result is obtained based on the truncated data corresponding to the processed multiple floating-point input data and the summation data corresponding to the multiple floating-point input data, including:

[0168] After processing multiple floating-point input data, the corresponding truncated data are added together to obtain the results of the third and fourth sub-operations.

[0169] Add the corresponding values ​​of the multiple floating-point input data to obtain the sum of the values ​​to be summed.

[0170] The result of the third sub-operation, the result of the fourth sub-operation, and the sum of the data to be summed are added together to obtain the result of the fourth operation.

[0171] In some embodiments, the floating-point calculation method further includes:

[0172] If a preset data is present among multiple floating-point input data, a first signal is output; or, if the preset data is not present among multiple floating-point input data, a second signal is output.

[0173] Based on the first signal, output preset data; or, based on the second signal, output the second calculation result.

[0174] In some embodiments, the floating-point calculation method further includes:

[0175] The multiple input parameters corresponding to the function operator are legalized to obtain multiple floating-point input data.

[0176] The beneficial technical effects of this method can be found in the corresponding beneficial technical effects of the exemplary system section above, and will not be repeated here.

[0177] This disclosure also provides a neural network processor. For example... Figure 15 As shown, the neural network processor 1300 includes multiple registers 1301 and an addition tree circuit 100. The multiple registers are used to store data during the operation of the addition tree circuit.

[0178] The beneficial effects of neural network processors can be found in the corresponding beneficial effects of the exemplary system section described above, and will not be repeated here.

[0179] Exemplary electronic devices

[0180] Figure 16 This is a structural diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device 11 includes at least one processor 111 and a memory 112.

[0181] The processor 111 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.

[0182] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 111 may execute one or more computer program instructions to implement the floating-point calculation methods and / or other desired functions of the various embodiments of this disclosure described above.

[0183] In one example, the electronic device 11 may also include an input device 113 and an output device 114, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0184] The input device 113 may also include, for example, a keyboard, a mouse, etc.

[0185] The output device 114 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0186] Of course, for the sake of simplicity, Figure 16 Only some of the components of the electronic device 11 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 11 may include any other suitable components depending on the specific application.

[0187] Exemplary computer program product and computer readable storage medium

[0188] In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the floating-point calculation methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0189] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0190] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the floating-point calculation methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0191] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0192] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0193] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. An adder tree circuit, comprising: A parsing circuit is used to determine multiple floating-point input data corresponding to a function operator, and to parse the multiple floating-point input data respectively to obtain the exponent and mantissa corresponding to the multiple floating-point input data respectively; wherein, the function operator is used to perform addition operations on the multiple floating-point input data; The alignment processing circuit is used to align the exponents corresponding to the multiple floating-point input data based on the exponents and mantissas corresponding to the multiple floating-point input data respectively, so as to obtain the aligned mantissas corresponding to the multiple floating-point input data respectively. An addition circuit is used to perform addition operations on the mantissas after the multiple floating-point input data are aligned, to obtain a first operation result; A normalization processing circuit is used to normalize the first calculation result to obtain a second calculation result.

2. The circuit according to claim 1, wherein, The alignment processing circuit includes a maximum exponent determination circuit, a difference calculation circuit, and an alignment circuit. The maximum exponent determination circuit is used to determine the maximum exponent from the exponents corresponding to the plurality of floating-point input data respectively. The difference calculation circuit is used to calculate the difference between the exponents corresponding to the multiple floating-point input data and the maximum exponent. The alignment circuit is used to adjust the mantissas corresponding to the multiple floating-point input data based on the difference between the exponents corresponding to the multiple floating-point input data and the maximum exponent, so as to obtain the aligned mantissas corresponding to the multiple floating-point input data.

3. The circuit according to claim 1, wherein, The addition circuit includes: a first rounding circuit, a first conversion circuit, a first addition circuit, and a second conversion circuit; The first rounding circuit is used to round the mantissas of the multiple floating-point input data respectively after alignment, so as to obtain the rounded mantissas of the multiple floating-point input data respectively. The first conversion circuit is used to convert the rounded mantissas of the multiple floating-point input data into two's complement, so as to obtain the mantissas of the multiple floating-point input data after two's complement conversion. The first addition circuit is used to perform two's complement conversion on the multiple floating-point input data and then add the corresponding mantissas to obtain the third operation result; The second conversion circuit is used to convert the third operation result into the original code to obtain the first operation result.

4. The circuit according to claim 3, wherein, The first adder circuit includes a first sub-adder circuit and a second sub-adder circuit: The first sub-adder circuit is used to add the mantissas corresponding to the multiple floating-point input data after two's complement conversion to obtain the first sub-operation result and the second sub-operation result; The second sub-adder circuit is used to add the result of the first sub-operation and the result of the second sub-operation to obtain the third operation result.

5. The circuit according to claim 1, wherein, The addition circuit includes: a second rounding circuit, a third conversion circuit, a fourth conversion circuit, a second addition circuit, and a fifth conversion circuit; The second rounding circuit is used to round the mantissas corresponding to the multiple floating-point input data after they are aligned to obtain the truncated data and rounded carry data corresponding to the multiple floating-point input data respectively. The third conversion circuit is used to process the truncated data corresponding to the multiple floating-point input data based on the symbols corresponding to the multiple floating-point input data respectively, and to determine the truncated data corresponding to the multiple floating-point input data respectively after processing. The fourth conversion circuit is used to obtain the sum of the multiple floating-point input data based on the signs corresponding to the multiple floating-point input data and the rounding carry data corresponding to the multiple floating-point input data. The second addition circuit is used to obtain a fourth operation result based on the truncated data corresponding to the multiple floating-point input data after processing and the data to be summed corresponding to the multiple floating-point input data. The fifth conversion circuit is used to convert the fourth operation result into original code to obtain the first operation result.

6. The circuit according to claim 5, wherein, The second adder circuit includes a third sub-adder circuit, a fourth sub-adder circuit, and a fifth sub-adder circuit; The third sub-adder circuit is used to add the truncated data corresponding to the processed multiple floating-point input data to obtain the third sub-operation result and the fourth sub-operation result. The fourth sub-adder circuit is used to add the corresponding data to be summed of the multiple floating-point input data to obtain the sum of the data to be summed. The fifth sub-adder circuit is used to add the sum of the third sub-operation result, the fourth sub-operation result, and the summation value of the data to be summed to obtain the fourth operation result.

7. The circuit according to any one of claims 1-6, wherein the addition tree circuit further includes a decision circuit and a selector; The judgment circuit is used to output a first signal in response to the presence of preset data among the plurality of floating-point input data; Alternatively, in response to the absence of preset data among the plurality of floating-point input data, a second signal is output; The selector is used to output the preset data based on the first signal; or to output the second calculation result based on the second signal.

8. The circuit according to any one of claims 1-6, wherein the adder tree circuit further comprises an input processing circuit; The input processing circuit is used to legalize multiple input parameters corresponding to the function operator to obtain multiple floating-point input data.

9. A neural network processor, comprising a plurality of registers and an adder tree circuit as described in any one of claims 1-8, wherein the plurality of registers are used to store data during the operation of the adder tree circuit.

10. A floating-point calculation method, comprising: Multiple floating-point input data of a function operator are determined, and the multiple floating-point input data are parsed to obtain the exponent and mantissa corresponding to the multiple floating-point input data respectively; wherein, the function operator is used to perform addition operation on the multiple floating-point input data; Based on the exponents and mantissas corresponding to the multiple floating-point input data respectively, the exponents corresponding to the multiple floating-point input data are aligned to obtain the aligned mantissas corresponding to the multiple floating-point input data respectively. The first calculation result is obtained by performing addition operations on the mantissas of the multiple floating-point input data after alignment. The first calculation result is normalized to obtain the second calculation result.

11. A computer-readable storage medium storing a computer program that is executed by a processor to perform the floating-point calculation method of claim 10.

12. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the floating-point calculation method of claim 10.

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