Multi-terminal clock synchronization method, system, equipment and medium

Abstract

The invention provides a multi-terminal clock synchronization method, system and device and a medium, and relates to the technical field of wireless communication, and the method comprises the following steps: a master device sends a synchronization request packet to an ith slave device at a first sending moment; the ith slave device receives the synchronization request packet at the first receiving moment and sends a synchronization response packet to the master device at the second sending moment; the master device receives a synchronization response packet at a second receiving moment, and determines a first receiving moment and a second sending moment according to the synchronization response packet; determining a transmission delay parameter and a clock offset parameter according to the first sending moment, the second sending moment, the first receiving moment and the second receiving moment, and sending the transmission delay parameter and the clock offset parameter to the ith slave device; and the ith slave device adjusts a local timer according to the transmission delay parameter and the clock offset parameter, so that clock synchronization between the ith slave device and the master device is realized. According to the invention, high-precision clock synchronization between multiple slave devices and the master device is realized.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and more specifically, to a multi-terminal clock synchronization method, system, device, and medium. Background Technology

[0002] In advanced applications such as smart manufacturing and intelligent transportation, numerous sensors and actuators need to work collaboratively, requiring clock synchronization accuracy at the microsecond or even millisecond level. Current technologies often use Bluetooth or Wi-Fi for clock synchronization, but their synchronization accuracy is insufficient and cannot meet the demands for high-precision, low-power clock synchronization. Summary of the Invention

[0003] In view of this, the purpose of this application is to overcome the shortcomings of the prior art and provide a multi-terminal clock synchronization method, system, device, and medium. This application provides the following technical solution: In a first aspect, this application provides a multi-terminal clock synchronization method, applied to a multi-terminal clock synchronization system, the multi-terminal clock synchronization system comprising: a master device and N slave devices, where N≥1, the method comprising: Step S1: The master device sends a synchronization request packet to the i-th slave device at the first transmission time, where 1 ≤ i ≤ N; Step S2: The i-th slave device receives the synchronization request packet at the first receiving time and sends a synchronization response packet to the master device at the second sending time; Step S3: The master device receives the synchronization response packet at the second receiving time, and determines the first receiving time and the second sending time based on the synchronization response packet; it determines the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first sending time, the second sending time, the first receiving time, and the second receiving time, and sends the transmission delay parameter and the clock offset parameter to the i-th slave device. Step S4: The i-th slave device adjusts its local timer according to the transmission delay parameter and the clock offset parameter to synchronize the clock between the i-th slave device and the master device.

[0004] In one embodiment, before the master device sends a synchronization request packet to the i-th slave device at the first transmission time, it further includes: The master device periodically sends a synchronization signal to the i-th slave device; When the synchronization signal is received, the i-th slave device sends identity authentication information and network registration information to the master device; The master device verifies the received identity authentication information and network registration information. If the verification is successful, the master device allocates communication resources to the i-th slave device and establishes a connection with the i-th slave device.

[0005] In one embodiment, the method further includes: When the synchronization signal is received, the i-th slave device records the arrival time of the synchronization signal and determines the clock period based on the synchronization signal; The i-th slave device performs initial configuration of the local timer based on the arrival time and the clock period. After initial configuration, the local timer starts local timing with the arrival time as the timing start point and the period is consistent with the clock period.

[0006] In one embodiment, the transmission delay parameter between the master device and the i-th slave device is determined based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and the calculation formula is as follows:

[0007] in, Indicates the first transmission time. Indicates the second receiving time. This indicates the first receiving time. This indicates the second transmission time.

[0008] In one embodiment, the clock offset parameter between the master device and the i-th slave device is determined based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and the calculation formula is as follows: .

[0009] In one embodiment, the method further includes step S5, in which the master device and the i-th slave device periodically execute steps S1-S4 to keep the clock synchronized between the i-th slave device and the master device.

[0010] In one embodiment, the method further includes: determining a frequency offset rate based on the clock offset parameter, and adjusting a local timer based on the transmission delay parameter and the frequency offset rate.

[0011] Secondly, this application provides a multi-terminal clock synchronization system, the system comprising: a master device and N slave devices; The master device is configured to send a synchronization request packet to the i-th slave device at the first transmission time, where 1≤i≤N; The i-th slave device is configured to receive the synchronization request packet at a first receiving time and send a synchronization response packet to the master device at a second sending time; The master device is configured to receive the synchronization response packet at the second receiving time, and determine the first receiving time and the second sending time based on the synchronization response packet; The master device is configured to determine the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first transmission time, the second transmission time, the first reception time and the second reception time, and send the transmission delay parameter and the clock offset parameter to the i-th slave device; The i-th slave device is configured to adjust a local timer according to the transmission delay parameter and the clock offset parameter, so that the i-th slave device and the master device are clock synchronized.

[0012] Thirdly, this application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the computer program executes the multi-terminal clock synchronization method described in the first aspect when it is run on the processor. Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the multi-terminal clock synchronization method described in the first aspect.

[0013] This application provides a multi-terminal clock synchronization method, system, device, and medium. The method includes: Step S1, where the master device sends a synchronization request packet to the i-th slave device at a first transmission time, where 1 ≤ i ≤ N; Step S2, where the i-th slave device receives the synchronization request packet at a first reception time and sends a synchronization response packet to the master device at a second transmission time; Step S3, where the master device receives the synchronization response packet at a second reception time and determines the first reception time and the second transmission time based on the synchronization response packet; and determines a transmission delay parameter and a clock offset parameter between the master device and the i-th slave device based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and sends the transmission delay parameter and the clock offset parameter to the i-th slave device; Step S4, where the i-th slave device adjusts its local timer according to the transmission delay parameter and the clock offset parameter to synchronize the clocks between the i-th slave device and the master device. This application achieves high-precision clock synchronization between a large number of slave devices and the master device, effectively overcoming the shortcomings of traditional Bluetooth, Wi-Fi, and wired networks in terms of synchronization accuracy, scalability, or flexibility, and meeting the application requirements of microsecond or even nanosecond-level clock synchronization scenarios.

[0014] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart of a multi-terminal clock synchronization method provided in an embodiment of this application is shown; Figure 2 A schematic diagram of a multi-terminal clock synchronization system provided in an embodiment of this application is shown; Figure 3 This illustration shows a schematic diagram of signal exchange between the master device and the i-th slave device according to an embodiment of this application; Figure 4 This paper illustrates another flowchart of the multi-terminal clock synchronization method provided in an embodiment of this application. Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.

[0017] Explanation of key component symbols: 200 - Multi-terminal clock synchronization system; 210 - Master device; 220 - Slave device; 500 - Electronic equipment; 501 - Transceiver; 502 - Processor; 503 - Memory. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the template description is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] Example 1 Current applications in smart manufacturing and intelligent transportation require clock synchronization at the microsecond or even nanosecond level. Existing technologies mostly use Bluetooth or Wireless Fidelity (Wi-Fi) for clock synchronization. Bluetooth synchronization technology suffers from low accuracy and reliability in complex electromagnetic environments and has poor scalability for multiple devices. Wi-Fi synchronization technology has high power consumption, and the uncertainty introduced by shared channel contention is difficult to eliminate. For more information, please refer to [link to relevant documentation / reference]. Figure 1 This application provides a multi-terminal clock synchronization method, applicable to, for example... Figure 2 The multi-terminal clock synchronization system shown includes: a master device and N slave devices, where N ≥ 1. The method includes: Step S1: The master device sends a synchronization request packet to the i-th slave device at the first transmission time, where 1≤i≤N.

[0022] The master device selects a specific transmission time, namely the first transmission time, on its own preset precise timeline. This first transmission time is recorded by the master device's local high-precision timer. The master device then sends a synchronization request packet for clock synchronization measurement to the i-th slave device. The purpose of the synchronization request packet is to trigger bidirectional data interaction between the master device and the i-th slave device. Subsequently, the master device will obtain the timestamps of the slave device receiving the synchronization request packet, the slave device sending the synchronization response packet, and the master device receiving the synchronization response packet. By using this series of timestamps, the master device calculates the clock offset and transmission delay between the two devices, providing raw measurement data for high-precision synchronization.

[0023] In one embodiment, before the master device sends a synchronization request packet to the i-th slave device at the first transmission time, the method further includes: the master device periodically sending a synchronization signal to the i-th slave device; when the synchronization signal is received, the i-th slave device sends authentication information and network registration information to the master device; the master device verifies the received authentication information and network registration information, and if the verification is successful, the master device allocates communication resources to the i-th slave device and establishes a connection with the i-th slave device.

[0024] It is understandable that before the master device sends a synchronization request packet to the i-th slave device at the first transmission time, it needs to complete the network preparation and resource allocation process: the master device will send a synchronization signal to the i-th slave device at a fixed period; after receiving the synchronization signal, the i-th slave device sends its own identity authentication information and network registration information to the master device; the master device verifies the received identity authentication information and network registration information, and if the verification is successful, the master device allocates dedicated communication resources to the i-th slave device and establishes a stable communication connection with the i-th slave device, laying the foundation for subsequent sending of synchronization request packets and conducting clock synchronization measurements.

[0025] In one embodiment, the method further includes: when the synchronization signal is received, the i-th slave device records the arrival time of the synchronization signal and determines the clock period based on the synchronization signal; the i-th slave device performs initial configuration of the local timer based on the arrival time and the clock period, and the local timer after initial configuration starts local timing with the arrival time as the timing start point and the period is consistent with the clock period.

[0026] In this embodiment, after receiving the synchronization signal sent by the master device, the i-th slave device completes the initial clock synchronization configuration. Specifically, when the i-th slave device receives the synchronization signal, it records the precise time when the synchronization signal arrives and parses the clock cycle of the master device from the synchronization signal. Subsequently, the i-th slave device uses the recorded arrival time as the starting point of its local timing and performs initial settings on its own local timer according to the parsed clock cycle, so that the initially configured local timer can count with a period consistent with the clock cycle of the master device, thereby achieving initial clock alignment with the master device.

[0027] In step S2, the i-th slave device receives the synchronization request packet at the first receiving time and sends a synchronization response packet to the master device at the second sending time.

[0028] In this embodiment, after receiving the synchronization request packet sent by the master device at its first recorded reception time, i.e. the precise time when the synchronization request packet arrives locally, the i-th slave device will send a synchronization response packet to the master device at its own determined second transmission time (a specific time controlled by the slave device's local timer). By matching the records of these two times with the relevant times of the master device in the future, key timestamp data is provided for calculating the transmission delay and clock offset between the two.

[0029] Step S3: The master device receives the synchronization response packet at the second receiving time, and determines the first receiving time and the second sending time based on the synchronization response packet; it determines the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first sending time, the second sending time, the first receiving time, and the second receiving time, and sends the transmission delay parameter and the clock offset parameter to the i-th slave device.

[0030] In this embodiment, please refer to Figure 3 After the master device receives the synchronization response packet sent by the i-th slave device at its own recorded second reception time, it obtains the first reception time recorded by the slave device (i.e., the time when the synchronization request packet arrives at the slave device) and the second transmission time (i.e., the time when the synchronization response packet is sent from the slave device) from the synchronization response packet. Subsequently, the master device combines its own recorded first transmission time (i.e., the time when the synchronization request packet is sent), the second reception time, and the first reception time and the second transmission time determined from the response packet to calculate the transmission delay parameter and clock offset parameter between the master device and the i-th slave device, and sends these two parameters to the i-th slave device to provide a basis for the slave device to adjust its local clock.

[0031] In one embodiment, the transmission delay parameter between the master device and the i-th slave device is determined based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and the calculation formula is as follows:

[0032] in, Indicates the first transmission time. Indicates the second receiving time. This indicates the first receiving time. This indicates the second transmission time.

[0033] In this embodiment, during the bidirectional data interaction between the master device and the i-th slave device, the master device records the first sending time of the synchronization request packet. and the second receiving time of receiving the synchronization response packet The device recorded the first moment of receiving the synchronization request packet. and the second transmission time of sending the synchronization response packet .

[0034] Since the wireless channel can be considered symmetrical in a single bidirectional transmission, meaning the transmission delay from the master device to the slave device is approximately equal to the transmission delay from the slave device to the master device, then the total time consumed by the master device... This includes the transmission delay from the master device to the slave device, the processing time of the slave device, and the transmission delay from the slave device to the master device. The total time consumed by the slave device... This includes the processing time from the equipment.

[0035] Subtracting the slave device's processing time from the master device's total processing time gives the transmission delay from the master device to the slave device. The sum of the master device's and slave device's transmission delays is then divided by 2 to separate the one-way transmission delay.

[0036] In one embodiment, the clock offset parameter between the master device and the i-th slave device is determined based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and the calculation formula is as follows: .

[0037] In this embodiment, clock skew refers to the time difference between the slave device's local clock and the master device's clock, i.e., how fast the slave device's clock is relative to the master device's clock. In the bidirectional interaction between the master device and the i-th slave device, the time taken on the master device's timeline from sending a synchronization request packet to receiving a synchronization response packet is... From the device's timeline, the time elapsed from receiving a synchronization request packet to sending a synchronization response packet is... .

[0038] Since the bidirectional latency of wireless transmission has been removed using the transmission delay formula, the difference between these two latency values ​​essentially reflects the combined effect of the clock offsets between the master and slave devices during bidirectional interaction. Adding them together and dividing by 2 separates the clock offset between the master and slave devices in a single interaction.

[0039] Step S4: The i-th slave device adjusts its local timer according to the transmission delay parameter and the clock offset parameter to synchronize the clock between the i-th slave device and the master device.

[0040] In this embodiment, after the i-th slave device receives the transmission delay parameter and clock offset parameter sent by the master device, it uses the clock offset parameter to compensate for the time difference between the local timer and the master device in one go. At the same time, combined with the implicit reference of the transmission delay parameter, it completes the adjustment of the local timer, thereby realizing clock synchronization between the i-th slave device and the master device.

[0041] In one implementation, please refer to Figure 4 The method further includes step S5, in which the master device and the i-th slave device periodically execute steps S1-S4 to keep the clock synchronized between the i-th slave device and the master device.

[0042] In this embodiment, the entire clock synchronization process from step S1 to step S4 is repeated. By periodically repeating this process, the possible clock deviations between the slave device and the master device are continuously corrected, thereby ensuring that the i-th slave device and the master device always maintain a clock-synchronized state.

[0043] In one embodiment, the method further includes: determining a frequency offset rate based on the clock offset parameter, and adjusting a local timer based on the transmission delay parameter and the frequency offset rate.

[0044] In this embodiment, the slave device first determines the frequency offset rate, i.e. the frequency drift rate, based on the clock offset parameter by linear fitting of multiple historical clock offset data. Then, it adjusts the local timer by combining the implicit reference of the transmission delay parameter and the frequency offset rate, thereby achieving long-term accurate clock synchronization with the master device.

[0045] The multi-terminal clock synchronization method provided in this application embodiment involves the master device sending a synchronization request packet (1≤i≤N) to the i-th slave device at a first transmission time; the i-th slave device receiving the synchronization request packet at a first reception time and sending a synchronization response packet to the master device at a second transmission time; the master device receiving the synchronization response packet at a second reception time and determining the first reception time and the second transmission time based on the synchronization response packet; determining the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and sending the transmission delay parameter and the clock offset parameter to the i-th slave device; and the i-th slave device adjusting its local timer according to the transmission delay parameter and the clock offset parameter to achieve clock synchronization between the i-th slave device and the master device. This method achieves high-precision clock synchronization between a large number of slave devices and the master device, effectively overcoming the shortcomings of traditional Bluetooth, Wi-Fi, and wired networks in terms of synchronization accuracy, scalability, or flexibility, and meeting the application requirements of microsecond or even nanosecond-level clock synchronization scenarios.

[0046] Example 2 In addition, please see again Figure 2 A multi-terminal clock synchronization system 200 includes: a master device 210 and N slave devices 220; The master device 210 is configured to send a synchronization request packet to the i-th slave device at the first transmission time, where 1≤i≤N; The i-th slave device 220 is configured to receive the synchronization request packet at a first receiving time and send a synchronization response packet to the master device at a second sending time; The master device 210 is configured to receive the synchronization response packet at the second receiving time, and determine the first receiving time and the second sending time based on the synchronization response packet; The master device 210 is configured to determine the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first transmission time, the second transmission time, the first reception time and the second reception time, and send the transmission delay parameter and the clock offset parameter to the i-th slave device; The i-th slave device 220 is configured to adjust a local timer according to the transmission delay parameter and the clock offset parameter so that the i-th slave device and the master device are clock synchronized.

[0047] The multi-terminal clock synchronization system 200 provided in this application embodiment can execute the multi-terminal clock synchronization method provided in the above method embodiment 1. To avoid repetition, it will not be described again here.

[0048] This application achieves high-precision clock synchronization between a large number of slave devices and the master device, effectively overcoming the shortcomings of traditional Bluetooth, Wi-Fi, and wired networks in terms of synchronization accuracy, scalability, or flexibility, and meeting the application requirements of microsecond or even nanosecond-level clock synchronization scenarios.

[0049] Example 3 Furthermore, this application provides an electronic device, including a memory and a processor. The memory stores a computer program, which executes the multi-terminal clock synchronization method provided in Embodiment 1 when the computer program is run on the processor.

[0050] For details, please see Figure 5 The electronic device 500 includes a transceiver 501, a bus interface, and a processor 502. The processor 502 is configured to perform the following steps: Step S1, the master device sends a synchronization request packet to the i-th slave device at a first transmission time, where 1 ≤ i ≤ N; Step S2, the i-th slave device receives the synchronization request packet at a first reception time and sends a synchronization response packet to the master device at a second transmission time; Step S3, the master device receives the synchronization response packet at a second reception time and determines the first reception time and the second transmission time based on the synchronization response packet; determines the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and sends the transmission delay parameter and the clock offset parameter to the i-th slave device; Step S4, the i-th slave device adjusts its local timer according to the transmission delay parameter and the clock offset parameter to synchronize the clock between the i-th slave device and the master device.

[0051] In this embodiment of the application, the electronic device 500 further includes a memory 503. Figure 5 In this context, the bus architecture can include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 502) and memory (memory 503). The bus architecture can also link together various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 501 can be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over a transmission medium. The processor 502 is responsible for managing the bus architecture and general processing, and the memory 503 can store data used by the processor 502 during operation.

[0052] The electronic device 500 provided in this application embodiment can execute the multi-terminal clock synchronization method provided in the above method embodiment 1. To avoid repetition, it will not be described again here.

[0053] Example 4 Furthermore, embodiments of the present invention provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the multi-terminal clock synchronization method provided in Embodiment 1.

[0054] In this embodiment, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0055] The computer-readable storage medium provided in this embodiment can implement the multi-terminal clock synchronization method provided in Embodiment 1. To avoid repetition, it will not be described again here.

[0056] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0057] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0058] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A multi-terminal clock synchronization method, characterized in that, The method is applied to a multi-terminal clock synchronization system, which includes a master device and N slave devices, where N ≥ 1. Step S1: The master device sends a synchronization request packet to the i-th slave device at the first transmission time, where 1 ≤ i ≤ N; Step S2: The i-th slave device receives the synchronization request packet at the first receiving time and sends a synchronization response packet to the master device at the second sending time; Step S3: The master device receives the synchronization response packet at the second receiving time, and determines the first receiving time and the second sending time based on the synchronization response packet; it determines the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first sending time, the second sending time, the first receiving time, and the second receiving time, and sends the transmission delay parameter and the clock offset parameter to the i-th slave device. Step S4: The i-th slave device adjusts its local timer according to the transmission delay parameter and the clock offset parameter to synchronize the clock between the i-th slave device and the master device.

2. The multi-terminal clock synchronization method according to claim 1, characterized in that, Before the master device sends a synchronization request packet to the i-th slave device at the first transmission time, it also includes: The master device periodically sends a synchronization signal to the i-th slave device; When the synchronization signal is received, the i-th slave device sends identity authentication information and network registration information to the master device; The master device verifies the received identity authentication information and network registration information. If the verification is successful, the master device allocates communication resources to the i-th slave device and establishes a connection with the i-th slave device.

3. The multi-terminal clock synchronization method according to claim 2, characterized in that, The method further includes: When the synchronization signal is received, the i-th slave device records the arrival time of the synchronization signal and determines the clock period based on the synchronization signal; The i-th slave device performs initial configuration of the local timer based on the arrival time and the clock period. After initial configuration, the local timer starts local timing with the arrival time as the timing start point and the period is consistent with the clock period.

4. The multi-terminal clock synchronization method according to claim 1, characterized in that, The transmission delay parameter between the master device and the i-th slave device is determined based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and the calculation formula is as follows: in, Indicates the first transmission time. Indicates the second receiving time. This indicates the first receiving time. This indicates the second transmission time.

5. The multi-terminal clock synchronization method according to claim 4, characterized in that, The clock offset parameter between the master device and the i-th slave device is determined based on the first transmission time, the second transmission time, the first reception time, and the second reception time, and the calculation formula is as follows: 。 6. The multi-terminal clock synchronization method according to any one of claims 1-5, characterized in that, The method further includes: In step S5, the master device and the i-th slave device periodically execute steps S1-S4 to keep the clock synchronized between the i-th slave device and the master device.

7. The multi-terminal clock synchronization method according to claim 1, characterized in that, The method further includes: The frequency offset rate is determined based on the clock offset parameter, and the local timer is adjusted based on the transmission delay parameter and the frequency offset rate.

8. A multi-terminal clock synchronization system, characterized in that, The system includes: a master device and N slave devices; The master device is configured to send a synchronization request packet to the i-th slave device at the first transmission time, where 1≤i≤N; The i-th slave device is configured to receive the synchronization request packet at a first receiving time and send a synchronization response packet to the master device at a second sending time; The master device is configured to receive the synchronization response packet at the second receiving time, and determine the first receiving time and the second sending time based on the synchronization response packet; The master device is configured to determine the transmission delay parameter and clock offset parameter between the master device and the i-th slave device based on the first transmission time, the second transmission time, the first reception time and the second reception time, and send the transmission delay parameter and the clock offset parameter to the i-th slave device; The i-th slave device is configured to adjust a local timer according to the transmission delay parameter and the clock offset parameter, so that the i-th slave device and the master device are clock synchronized.

9. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, which, when run on the processor, executes the multi-terminal clock synchronization method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the multi-terminal clock synchronization method according to any one of claims 1-7.

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