Automatic circuit design method of TAGE branch predictor
By constructing a parameterized superscalar front-end simulator and introducing a temporal-combinatorial logic decoupling paradigm, Verilog RTL code is generated, solving the problems of manual intervention dependence and poor adaptability in TAGE branch predictor design, and realizing efficient automated design and performance optimization.
Patent Information
- Application Number
- CN202511569621.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-30
- Publication Date
- 2026-03-20
AI Technical Summary
Existing TAGE branch predictor design and optimization require a lot of manual intervention and lack the ability to finely optimize for specific application scenarios. Furthermore, existing automatic design methods rely on data-driven approaches and lack human expert knowledge, resulting in low design efficiency and poor adaptability.
By constructing a parameterized superscalar front-end simulator, a decoupling paradigm of timing and combinational logic is introduced. The branch prediction unit is decomposed into timing components and combinational logic components. The Verilog RTL code is generated using an automatic circuit design algorithm, and human expert knowledge is incorporated to achieve automated design.
It improves the design efficiency and performance of the TAGE branch predictor, realizes automated design from high-dimensional modeling to RTL code, and enhances the flexibility and adaptability of the design.
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Figure CN121706680A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of processor design technology, and in particular to an automatic circuit design method for a TAGE branch predictor. Background Technology
[0002] Branch prediction is a key technique for improving instruction-level parallelism (ILP) in modern processors. The TAGE (Tagged Geometric History Length) branch predictor is a high-performance branch predictor that captures different patterns of branch behavior by using multiple tables with different history lengths and selects the appropriate prediction table based on the tags.
[0003] Automated design is a novel approach to architecture design that has emerged in recent years, overcoming the limitations of traditional architecture design which heavily relies on manual programming and verification. Through machine learning methods based on input-output examples, this approach can automatically generate large-scale Boolean function representations of circuit logic from scratch, without relying on formal programming languages (such as Verilog or Chisel).
[0004] Currently, the design and optimization of TAGE branch predictors typically require significant human intervention and specialized knowledge, lacking the ability to fine-tune optimization for specific application scenarios and incurring substantial R&D verification costs. Furthermore, existing design flows rely on manual parameter and table structure adjustments, limiting their rapid deployment and optimization capabilities across different application scenarios and hindering their ability to efficiently adapt to diverse workloads. In addition, existing automated design methods rely solely on data-driven circuit design, lacking the prior knowledge accumulated by human experts during the design process, thus their automated design effectiveness for specific tasks needs improvement. Summary of the Invention
[0005] To address the limitations of automated design of processor branch prediction components in sequential logic design, this invention provides an automated circuit design method for TAGE branch predictors. By decoupling sequential logic from combinational logic and introducing the branch prediction component architecture knowledge of human experts, the design efficiency and performance of automated branch prediction component design are improved.
[0006] To achieve the above-mentioned technical effects, this invention provides an automatic circuit design method for a TAGE branch predictor, comprising the following steps:
[0007] A superscalar front-end simulator is constructed. The superscalar front-end simulator adopts a modular architecture, including a branch prediction unit, an instruction cache, an instruction queue, and a prediction information cache, and simulates the behavior of the processor front-end through parameterized configuration.
[0008] In the branch prediction unit, a decoupling paradigm of timing and combinational logic is introduced, and the functional modules of the branch prediction unit are decomposed into timing components and combinational logic components. The timing components include a global history register, a folded history register, and a multi-level prediction table. The combinational logic components include a metadata generation unit, a direction prediction unit, a table entry update unit, and a history maintenance unit.
[0009] The superscalar front-end simulator is used to obtain the input and output data of the branch prediction unit during the execution process;
[0010] Based on the input and output data, the hardware description language code of the combinational logic component is generated using an automatic circuit design algorithm to realize the automatic circuit design of the TAGE branch predictor.
[0011] Furthermore, the superscalar front-end simulator is implemented using a high-level programming language.
[0012] Furthermore, the superscalar front-end simulator supports dynamic configuration of at least one of the following through parameterized hardware resource modeling: fetch bandwidth, commit throughput, cache access latency, and predictor entry size.
[0013] Furthermore, the timing and combinational logic decoupling paradigm exposes the behavioral characteristics of each functional module of the superscalar front-end simulator through standardized input / output interfaces, so that the automatic circuit design algorithm can use the combinational logic components as training sample generators.
[0014] Furthermore, the metadata generation unit is used to generate multi-level table indexes and corresponding tag values; the direction prediction unit is used to implement multi-level tag matching and the longest history priority arbitration mechanism; the table entry update unit is used to update table entries through utility counters and prediction information; and the history maintenance unit is used to manage the updates of the global history register and the folded history register.
[0015] Furthermore, the hardware description language code is Verilog RTL code.
[0016] This invention first constructs a parameterized superscalar front-end simulator, then uses a timing-combinational logic decoupling paradigm to decompose the TAGE predictor into timing components and combinational logic components. By exposing the behavioral characteristics of these components through standardized interfaces, and utilizing an automated circuit design algorithm, hardware code for the combinational logic is automatically generated based on data from the simulator. This integrates the architectural knowledge of human experts into the automated design process, overcoming the limitations of existing methods in timing logic design. It achieves automated design from high-dimensional modeling to RTL code, significantly improving design efficiency and optimizing predictor performance. Attached Figure Description
[0017] Figure 1 A flowchart illustrating the steps of an automatic circuit design method for a TAGE branch predictor provided in an embodiment of the present invention;
[0018] Figure 2 A schematic diagram of the basic architecture of the automatic circuit design method for the TAGE branch predictor provided in an embodiment of the present invention, which is modeled using parameterized hardware resources.
[0019] Figure 3 A schematic diagram of the overall architecture of the branch prediction unit when the instruction fetch width is set to 4 in the automatic circuit design method of the TAGE branch predictor provided in an embodiment of the present invention.
[0020] Figure 4 This is a schematic diagram of the basic design structure of the timing-combinatorial logic decoupling paradigm of the automatic circuit design method for the TAGE branch predictor provided in an embodiment of the present invention. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0022] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.
[0023] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.
[0024] Research into intelligent processor design revealed the aforementioned shortcomings in the design flow of existing TAGE branch predictors, and existing automated circuit design methods can only automate the design of combinational logic based on inputs and outputs. Further, architectural research on branch prediction units demonstrated that by artificially constraining the design space of sequential logic through high-dimensional modeling and decoupling sequential and combinational logic, and by introducing prior knowledge accumulated by human experts during the design process beyond the current reliance on data-driven automated design, the corresponding branch prediction component RTL code can be automatically designed directly from high-dimensional modeling, thereby achieving efficient TAGE branch predictor circuit design.
[0025] The automatic circuit design method for the TAGE branch predictor provided in the embodiments of this application will be further described in detail below with reference to the accompanying drawings.
[0026] Figure 1 This invention illustrates an automatic circuit design method for a TAGE branch predictor according to an embodiment of the present invention, comprising the following steps:
[0027] S101: Construct a superscalar front-end simulator. The superscalar front-end simulator adopts a modular architecture, including a branch prediction unit, an instruction cache, an instruction queue, and a prediction information cache, and simulates the behavior of the processor front-end through parameterized configuration. The superscalar front-end simulator in this embodiment is implemented using a high-level programming language (e.g., C++).
[0028] This embodiment of the superscalar front-end simulator adopts a modular architecture design. Its core subsystems include: Branch Prediction Unit (BPU), Instruction Cache (I-Cache), Instruction FIFO, and Predicted Target Address Buffer (PTAB). Through parameterized hardware resource modeling, this architecture supports dynamic configuration of multiple microarchitectural parameters such as fetch bandwidth (FETCH_WIDTH instructions / cycle), commit throughput (COMMIT_WIDTH instructions / cycle), cache access latency (HIT / MISS latency), and predictor entry size, constructing a fine-grained, adjustable hardware model. Its basic architecture is as follows: Figure 2 As shown.
[0029] As a core subsystem of superscalar front-end design, the Branch Prediction Unit (BPU) effectively solves the fetch interruption problem caused by control flow uncertainty by working collaboratively through both direction prediction and address prediction mechanisms. In the specific implementation of this simulator, branch direction prediction adopts a prediction algorithm based on tagged geometric history length (TAGE), while branch address prediction uses a combination of sub-predictors such as the Branch Target Buffer (BTB), Return Address Stack (RAS), and Target Cache (TC). This superscalar front-end simulator implements parametric design on the key components of all functional units. Figure 3 The overall architecture of the BPU is shown in a specific example with the fetch width set to 4.
[0030] S102: Introduce a decoupling paradigm between timing and combinational logic in the branch prediction unit, decompose the functional modules of the branch prediction unit into timing components and combinational logic components. The timing components include a global history register, a folded history register, and a multi-level prediction table. The combinational logic components include a metadata generation unit, a direction prediction unit, a table entry update unit, and a history maintenance unit.
[0031] Furthermore, the timing and combinational logic decoupling paradigm exposes the behavioral characteristics of each functional module of the superscalar front-end simulator through standardized input / output interfaces, so that the automatic circuit design algorithm can use the combinational logic components as training sample generators.
[0032] S103: Obtain the input and output data of the branch prediction unit during execution through a superscalar front-end simulator.
[0033] S104: Based on the input and output data, use an automatic circuit design algorithm to generate hardware description language code for the combinational logic component to achieve automatic circuit design of the TAGE branch predictor. Specifically, the hardware description language code is Verilog RTL code.
[0034] This embodiment introduces a timing-combinational logic decoupling paradigm on the basis of a superscalar front-end simulator, reconstructing each functional module into a functional unit with clear inputs and outputs. Each module exposes its behavioral characteristics through a standardized input / output interface, enabling existing circuit automatic design algorithms to use it as a training sample generator and automatically convert it into synthesizable Verilog RTL code. Figure 4This diagram illustrates the basic design structure of a time-combinatorial logic decoupling paradigm, specifically for the TAGE branch predictor. The blue squares represent the time-series components, including the global history register, folded history register, and various prediction tables. The orange sections represent the combinational logic functional modules to be trained. Their hardware implementation is decomposed into four orthogonal functional units: the metadata generation unit generates multi-level table indexes and corresponding tag values; the direction prediction unit implements multi-level tag matching and the longest history priority arbitration mechanism; the entry update unit updates entries using utility counters and prediction information; and the history maintenance unit manages the updates of the global history register and folded history register.
[0035] In summary, the automatic circuit design method for TAGE branch predictors provided by this invention first constructs a parameterized superscalar front-end simulator, then uses a timing-combinational logic decoupling paradigm to decompose the TAGE predictor into timing components and combinational logic components. It exposes the behavioral characteristics of these components through standardized interfaces and utilizes an automatic circuit design algorithm to automatically generate hardware code for the combinational logic based on data generated by the simulator. This integrates the architectural knowledge of human experts into the automatic design process, overcoming the limitations of existing methods in timing logic design, and achieving automated design from high-dimensional modeling to RTL code, significantly improving design efficiency and optimizing predictor performance.
[0036] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0037] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.
Claims
1. An automatic circuit design method for a TAGE branch predictor, characterized in that, Including the following steps: A superscalar front-end simulator is constructed. The superscalar front-end simulator adopts a modular architecture, including a branch prediction unit, an instruction cache, an instruction queue, and a prediction information cache, and simulates the behavior of the processor front-end through parameterized configuration. In the branch prediction unit, a decoupling paradigm of timing and combinational logic is introduced, and the functional modules of the branch prediction unit are decomposed into timing components and combinational logic components. The timing components include a global history register, a folded history register, and a multi-level prediction table. The combinational logic components include a metadata generation unit, a direction prediction unit, a table entry update unit, and a history maintenance unit. The superscalar front-end simulator is used to obtain the input and output data of the branch prediction unit during the execution process; Based on the input and output data, the hardware description language code of the combinational logic component is generated using an automatic circuit design algorithm to realize the automatic circuit design of the TAGE branch predictor.
2. The method according to claim 1, characterized in that, The superscalar front-end simulator is implemented using a high-level programming language.
3. The method according to claim 1 or 2, characterized in that, The superscalar front-end simulator supports dynamic configuration of at least one of the following through parameterized hardware resource modeling: fetch bandwidth, commit throughput, cache access latency, and predictor entry size.
4. The method according to claim 1, characterized in that, The timing and combinational logic decoupling paradigm exposes the behavioral characteristics of each functional module of the superscalar front-end simulator through standardized input / output interfaces, so that the automatic circuit design algorithm can use the combinational logic components as training sample generators.
5. The method according to claim 1, characterized in that, The metadata generation unit is used to generate multi-level table indexes and corresponding tag values; the direction prediction unit is used to implement multi-level tag matching and the longest history priority arbitration mechanism; the table entry update unit is used to update table entries through utility counters and prediction information; and the history maintenance unit is used to manage the updates of the global history register and the folded history register.
6. The method according to claim 1, characterized in that, The hardware description language code is Verilog RTL code.