Signal control system with phase coherence function and signal phase coherence method

Abstract

The invention discloses a signal control system with a phase coherence function and a signal phase coherence method. Firstly, a coherent output instruction input by a user and a specified signal coherence channel needing to achieve the phase coherence function on an output signal are monitored; based on the coherent output instruction and a specified signal coherent channel, outputting a phase memory instruction to the signal coherent channel; and finally, performing a phase memory function on the signal output by the signal coherent channel based on the phase memory instruction, so that the signal output by the signal coherent channel has the phase memory function, and the phase returns to the phase of the initial frequency when the initial frequency is changed in the operation process and then switched back. Therefore, phase coherence is generated among the output signals of the memorized channels. The phase coherence recovery function is realized by applying the phase memory function of the signal output channel, so that a predictable and repeatable multi-signal phase relationship is established and maintained, and the phase coherence function is realized more simply, more reliably and more quickly.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a signal control system with phase coherence function and a signal phase coherence method. BACKGROUND

[0002] At present, in the output signal control of multiple channels, the phase difference between the output signals can be adjusted. However, when the frequency of the signal output by one or more channels changes and then returns, the phase of the returned signal may be flipped or offset compared with the original signal phase. Similarly, when multiple channels output phase-coherent analog signals, when the frequency of the signal output by one channel changes and then returns, the returned signal cannot maintain the phase coherence of the analog signals output by the multiple channels. Please refer to Figure 1 The output signal waveform of the double RF channel in an embodiment is shown in the figure. In the first period, the frequencies of the signals output by the first channel and the second channel are the same, and ΔΦ is the phase difference between the two signals with the same frequency. When ΔΦ remains unchanged over time, it is considered that the first channel and the second channel output signals have a phase-coherent relationship. In the second period, the output signal of the first channel remains unchanged, and the frequency of the output signal of the second channel is switched (the frequency is changed). In the third period, when the frequency of the output signal of the second channel returns to the frequency value in the first period, the phase difference ΔΦ between the output signal of the second channel with the original frequency and the unchanged output signal of the first channel may be offset, which makes the first channel and the second channel lose the phase-coherent relationship between the output signals. In actual applications, in many scenarios, it is expected that the RF channel that has changed returns to the original frequency, and the phase difference ΔΦ between the RF signal output by the RF channel and other RF channels does not change, that is, the phase-coherent relationship between the two channels does not change.

[0003] The phase-coherent function of multiple channels is to set the signals output by multiple channels to the same frequency, and the multiple signals always have a determined relative phase position, that is, the phase difference remains unchanged over time. In simple terms, when one or more channels change the frequency, the frequency channel returns to the previous frequency, and the signals output by each channel can still maintain the original phase relationship. The ultimate purpose of the phase-coherent function is to establish and maintain a predictable and repeatable phase relationship in a signal control system with multiple channels.

[0004] At present, the ways to realize the phase-coherent function include: Method 1: Multiple channels use a "common phase reference" and a "synchronized clock".

[0005] The whole system shares a reference clock and local oscillator, using a main reference clock with ultra-low phase noise and high stability, which is distributed to all digital components (such as FPGA, DAC, ADC) in the system to ensure digital sampling synchronization.

[0006] Method 2, direct digital synthesis and digital up-conversion.

[0007] In the software-defined radio architecture, the phase coherent function is mainly implemented in the digital domain, but still needs to be driven by the main clock shared by all channel ADC modules and DAC modules. In the signal output channel, the numerically controlled oscillator that generates the signal for each channel uses the same clock and the same phase accumulator algorithm.

[0008] Method 3, achieved through calibration and compensation.

[0009] In theory, all channels should be completely consistent, but in reality, the slight differences in analog devices will cause phase errors. Therefore, initial calibration (measured and stored in the factory for the fixed phase offset of each channel) and real-time compensation (adjust the phase weight of each channel dynamically in the digital domain through an algorithm to compensate for drift caused by temperature changes, device aging, etc.) are also required. SUMMARY

[0010] The technical problem solved by the present application is how to reset or maintain the phase coherence between the output signals of specified channels in a signal control system with multiple signal output channels.

[0011] According to a first aspect, an embodiment provides a signal control system with a phase coherent function, comprising a coherent control module and a plurality of signal output channels; Each of the signal output channels comprises a phase memory device, which is used to perform a phase memory function on the signal output by the signal output channel based on a phase memory instruction, so that the output signal has a phase memory function, and when the initial frequency is changed during operation and then switched back to the initial frequency, the phase of the output signal returns to the phase of the initial frequency. The coherent control module is connected to the phase memory device in each of the signal output channels. The coherent control module is used to monitor a specified signal coherent channel that needs to implement a phase coherent function on the output signal and a coherent output instruction, and output the phase memory instruction to the signal coherent channel based on the coherent output instruction, the signal coherent channel being selected from a plurality of signal output channels. Wherein, the signal coherent channel is specified based on the input of the user through the human-computer interaction interface, and the coherent output instruction is generated based on the input of the user through the human-computer interaction interface.

[0012] And / or, the coherence control module is configured to monitor a designated signal coherence channel and a phase memory instruction, which needs to implement a phase coherence function on an output signal, and output the phase memory instruction to a phase memory device of the signal coherence channel selected from a plurality of signal output channels. Wherein, the signal coherence channel is designated based on user input through a human-machine interface, and the phase memory instruction is generated based on user input through the human-machine interface.

[0013] In an embodiment, the phase memory device comprises: a frequency synthesis circuit configured to perform phase accumulation based on a frequency control word at a clock tick, and output a digital waveform signal with a set frequency according to an accumulation result; a phase memory unit configured to receive an initial memory value corresponding to a memorized frequency and the frequency control word, and perform phase accumulation based on the initial memory value with the frequency control word corresponding to the memorized frequency as a step in synchronization with the frequency synthesis circuit, and obtain an accumulated memory value; a control module configured to obtain a set frequency, and output a frequency control word according to the set frequency, and output the frequency control word to the frequency synthesis circuit; the control module is further configured to output the initial memory value corresponding to the memorized frequency and the frequency control word to the phase memory unit based on a phase memory instruction, and when a new set frequency is obtained, determine whether the frequency control word corresponding to the new set frequency and the frequency control word corresponding to the memorized frequency in the phase memory unit are the same, and if so, output the current accumulated memory value corresponding to the memorized frequency to the frequency synthesis circuit as an initial value for phase accumulation by the frequency synthesis circuit.

[0014] In an embodiment, the signal control system further comprises a clock setting unit configured to provide a reference clock signal with a reference frequency to each phase memory device, so that the phase memory devices of the signal coherence channels perform phase accumulation with the same clock tick.

[0015] In an embodiment, the frequency synthesis circuit comprises a phase accumulator, a phase / amplitude converter, and a signal output module; the phase accumulator is connected to the clock setting unit, configured to obtain a frequency control word, and perform phase accumulation with the frequency control word as a step at the reference clock, and output a phase accumulation value; the phase / amplitude converter outputs an amplitude-controlled digital waveform signal according to the phase accumulation value and a set waveform type; and the signal output module is configured to output an analog signal with a set frequency according to the amplitude-controlled digital waveform signal. The phase memory unit is configured to include at least one memory subunit, each memory subunit is connected with a clock setting unit and a phase accumulator respectively, and is configured to receive an initial memory value corresponding to a memorized frequency and a frequency control word from the phase accumulator, and continue phase accumulation based on the initial memory value and the frequency control word corresponding to the memorized frequency as a step, to obtain an accumulated memory value; The control module is configured to output the frequency control word to the phase accumulator, configure a corresponding memory subunit for at least one memorized frequency in the phase memory unit based on the phase memory instruction, output the initial memory value corresponding to the memorized frequency and the frequency control word to the corresponding memory subunit, and update the frequency control word output to the phase accumulator based on the new set frequency, and judge whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, if yes, output the current accumulated memory value corresponding to the memorized frequency to the phase accumulator as an initial value for phase accumulation of the phase accumulator.

[0016] In an embodiment, the signal output module includes a digital-to-analog converter and a phase-locked loop, the input end of the digital-to-analog converter is connected with the output end of the phase / amplitude converter, and is configured to convert the digital amplitude control signal output by the phase / amplitude converter into an analog signal, and the output end of the digital-to-analog converter is connected with the phase-locked loop, and the phase-locked loop is configured to obtain a higher frequency output signal after phase-locked to the lower frequency analog signal output by the digital-to-analog converter.

[0017] In an embodiment, the clock setting unit includes a frequency source element, a power division module, a clock buffer module and a frequency multiplier; The frequency source element is configured to generate a reference clock with a preset single frequency; The power division module is configured to divide the reference clock generated by the frequency source element into two paths, and includes a first input end, a first output end and a second output end, the first input end is connected with the frequency source element, the first output end is connected with the clock buffer module, and the second output end is connected with the frequency multiplier; The clock buffer module is configured to convert the reference clock into the reference clock with a reference frequency, and output the reference clock to the phase accumulator and the phase memory unit of each phase memory device as a working clock of the phase accumulator and the phase memory unit; The frequency multiplier is configured to convert the reference clock into a sampling clock signal with a preset frequency value, and output the sampling clock signal to the digital-to-analog converter as a sampling clock of the digital-to-analog converter.

[0018] In one embodiment, the clock setting unit further includes a switch control module, which has multiple output terminals. Its input terminal is connected to the frequency source element, and the multiple output terminals are used to connect to the power divider module and another power divider module of the signal control system, respectively. The power divider module further includes a second input terminal for receiving a reference clock from the switch control module of the other signal control system.

[0019] In one embodiment, after receiving the coherent output command and the designated signal coherent channel, the coherent control module further determines whether the output signal frequencies of the signal coherent channels are the same. If they are the same, the module outputs the phase memory command to the signal coherent channel; if they are different, the module adjusts the output signal frequencies of each signal coherent channel to the same frequency before outputting the phase memory command to the signal coherent channel. Adjusting the output signal frequencies of each signal coherent channel to the same frequency includes: obtaining a reference channel specified by the user in the signal coherent channels and adjusting the frequencies of the output signals of other signal coherent channels to the frequency of the reference channel; or obtaining a frequency set by the user and adjusting the output signal frequencies of each signal coherent channel to the user-set frequency. According to a second aspect, one embodiment provides a signal phase coherence method for enabling a signal control system to output a phase-coherent signal, the signal control system including multiple signal output channels, the signal phase coherence method comprising: The system monitors the user-inputted coherent output command and the specified signal coherent channel that needs to achieve phase coherence on the output signal, wherein the signal coherent channel is selected from a plurality of the signal output channels; Based on the coherent output command and the specified signal coherent channel, a phase memory command is output to the signal coherent channel; The phase memory function is executed on the signal output by the signal coherence channel based on the phase memory command, so that the output signal of the signal coherence channel has the phase memory function, so that when the initial frequency is changed during operation and then switched back to the initial frequency, the phase of the output signal returns to the phase of the initial frequency, thereby generating phase coherence between the output signals of the signal coherence channel.

[0020] In one embodiment, the step of performing phase memory function on the signal output from the signal coherence channel based on phase memory instructions includes: Obtain the user's settings for the required output waveform frequency and waveform type; A frequency control word is generated based on a set frequency, so that the frequency synthesis circuit can output a waveform signal with the set frequency by phase accumulation based on the frequency control word; Monitor the phase memory command input by the user; based on the phase memory command, output the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit, and control the phase memory unit to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the frequency to be memorized as the step size, and obtain the accumulated memory value; The frequency control word is updated based on the new set frequency; The frequency control word corresponding to the new set frequency is matched with the frequency control word corresponding to the memorized frequency stored in the phase memory unit; If the match is successful, the accumulated memory value corresponding to the memory frequency that matches the new set frequency will be used as the initial value for the frequency synthesis circuit to perform phase accumulation based on the frequency control word, so as to output a waveform that is in phase with the memory frequency. If the matching fails, the updated frequency control word is output to the frequency synthesis circuit, so that the frequency synthesis circuit can output a waveform signal with the new set frequency based on the updated frequency control word by phase accumulation. According to a third aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the method as described in the second aspect.

[0021] According to the fourth aspect, one embodiment provides a computer program product including a computer program and / or instructions that, when executed by a processor, implement the method as described in the second aspect.

[0022] According to the signal phase coherence method of the above embodiments, the phase memory function of the signal output channel is used to realize the phase coherence recovery function, thereby establishing and maintaining a predictable and repeatable multi-signal phase relationship, making the realization of the phase coherence function simpler, more reliable and faster. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the output signal waveform of a dual RF channel in one embodiment; Figure 2 This is a waveform demonstration diagram of the phase memory function in one embodiment; Figure 3 This is a functional block diagram of a signal control system in one embodiment; Figure 4 A diagram of a human-computer interaction interface Figure 1 ; Figure 5 A diagram of a human-computer interaction interface Figure 2 ; Figure 6 This is a functional structural block diagram of a phase memory device in one embodiment; Figure 7 This is a schematic diagram showing the functional module connections of a frequency synthesis circuit in one embodiment; Figure 8 This is a functional structure block diagram of a phase memory unit in one embodiment; Figure 9 This is a structural block diagram of the processing device in one embodiment; Figure 10 This is a flowchart illustrating a phase memory method for a signal in one embodiment; Figure 11 This is a block diagram illustrating the functional implementation of the RF channel phase memory function in one embodiment. Figure 12 This is a flowchart illustrating a phase memory method for an RF channel in one embodiment. Figure 13 This is a flowchart illustrating the RF channel phase memory process in one embodiment; Figure 14 This is a schematic diagram of the clock setting unit connection in one embodiment; Figure 15 This is a schematic diagram illustrating the connection of clock setting units between multiple systems in one embodiment; Figure 16 This is a flowchart illustrating a signal phase coherence method. Figure 17 This is a schematic diagram illustrating the execution flow of the phase memory function in one embodiment. Detailed Implementation

[0024] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0025] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0026] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0027] In this embodiment, the phase coherence function is implemented using a phase memory function. The purpose of the phase memory function can be simply understood as how to acquire or save the phase information or phase parameters of the transmitted signal before the switching when the output frequency of one or more RF channels changes and then returns to its previous frequency, or when the transmitted signal switches between multiple RF channels. Please refer to... Figure 2 This is a waveform demonstration diagram of the phase memory function in one embodiment. The original signal waveform is a waveform diagram of the initial output signal of the RF channel on the time axis. The solid line waveform is the actual output waveform of the RF channel, and the dashed line waveform is the memory waveform for implementing the phase memory function. The output waveform is a waveform diagram of the recovery process after the frequency of the RF channel output signal changes. The first time period is the initial signal waveform, the second time period is the waveform after the signal frequency changes, and the third time period is the initial signal recovery waveform after restoring the original frequency. The phase memory function ensures that when the frequency of the RF signal output by the RF channel changes and returns to its original value, the phase information of the original frequency RF signal is not lost, thereby maintaining the continuity and consistency of RF channel signal processing.

[0028] Methods for implementing phase memory include single-sided phase compensation and double-sided phase synchronization. Double-sided phase synchronization involves phase offsets on both the transmitter's DDS and receiver's NCO. Single-sided phase compensation involves performing phase compensation on the returned channel signal when the RF channel returns to its previous frequency, ensuring the returned signal's phase matches the pre-switching phase, thus achieving phase memory. In one embodiment of this application, single-sided phase compensation is used for phase memory. Based on the principle and method of generating digital waveform signals using frequency control words, the accumulated memory value is stored through dynamic synchronous phase accumulation, enabling phase memory functionality when restoring the original digital waveform signal's frequency.

[0029] In one embodiment of this application, the phase coherence reset function is achieved by applying a phase memory function. The phase memory function is based on the principle and method of generating digital waveform signals using frequency control. It stores accumulated memory values ​​by employing a dynamic synchronous phase accumulation method, enabling the phase memory function to be realized when restoring the frequency of the original digital waveform signal.

[0030] In one embodiment of this application, the implementation of the phase coherence function is optimized based on the shared reference clock and local oscillator of the entire system. Specifically, the reference clocks of each signal output channel are uniformly managed, simplifying the implementation of the phase coherence function of the signal control system. Example

[0031] Please refer to Figure 3 The diagram below illustrates the functional structure of a signal control system in one embodiment. The multi-signal control system includes a coherent control module 1 and M signal output channels 100, where M is a natural number. Each signal output channel 100 includes a phase memory device 2. The phase memory device 2 performs a phase memory function on the signal output by its own signal output channel 100 based on a phase memory command. This ensures that the output signal has a phase memory function, so that when its initial frequency is changed during operation and then switched back to the initial frequency, the phase of the output signal returns to the phase of the initial frequency. The coherent control module 1 is connected to the phase memory device 2 in each signal output channel 100.

[0032] In one embodiment, the coherence control module 1 monitors designated signal coherence channels and coherence output commands that require phase coherence functionality on the output signal, and outputs phase memory commands to the signal coherence channels based on the coherence output commands. The signal coherence channels are selected from multiple signal output channels 100. For example, a user selects a first signal output channel and a second signal output channel on the human-machine interface, and then inputs a coherence output command, or inputs a coherence output command first, and then selects the first and second signal output channels. After detecting the user input, the coherence control module 1 outputs phase memory commands to the first and second signal output channels based on the coherence output commands. The first and second signal output channels perform a signal phase memory function on the frequency before the frequency change of their output signals. The graphical user interface is as follows: Figure 4 As shown, checking the box selects two signal output channels that need phase coherence functionality. When the user clicks the phase coherence icon, the icon is grayed out, indicating that it is selected and a coherent output command is generated.

[0033] In one embodiment, the coherence control module 1 monitors the designated signal coherence channel and phase memory command that need to implement phase coherence function on the output signal, and outputs the phase memory command to the phase memory device 2 of the signal coherence channel. The signal coherence channel is selected from multiple signal output channels 100. For example, the user selects a first signal output channel and phase memory function, and a second signal output channel and phase memory function respectively on the human-machine interface. After the coherence control module 1 detects the user input, it outputs the phase memory command to the first signal output channel and the second signal output channel based on the user input. The first signal output channel and the second signal output channel perform the signal phase memory function for the frequency before the frequency change of the output signal. The graphical user interface is as follows: Figure 5 As shown, when the phase memory icon on the right side of the signal output channel is clicked and turns gray, it indicates that the signal output channel is selected.

[0034] like Figure 3 As shown, the phase memory device 2 includes a frequency synthesis circuit 30, a phase memory unit 20, and a control module 10. The frequency synthesis circuit 30 performs phase accumulation based on a frequency control word according to a clock cycle, and outputs a digital waveform signal with a set frequency based on the accumulation result. The phase memory unit 20 receives the initial memory value and the frequency control word corresponding to the frequency to be memorized, and performs phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the frequency to be memorized, obtaining the accumulated memory value. The control module 10 acquires the set frequency and outputs the frequency control word according to the set frequency, sending the frequency control word to the frequency synthesis circuit. The control module is also used to output the initial memory value and the frequency control word corresponding to the frequency to be memorized to the phase memory unit based on a phase memory instruction. When a new set frequency is acquired, it determines whether the frequency control word corresponding to the new set frequency is the same as the frequency control word corresponding to the frequency to be memorized in the phase memory unit. If they are the same, it outputs the current accumulated memory value corresponding to the frequency to be memorized to the frequency synthesis circuit 30 as the initial value for phase accumulation by the frequency synthesis circuit 30.

[0035] Please refer to Figure 6The diagram below illustrates the functional structure of a phase memory device in one embodiment. The phase memory device includes a control module 10, a phase memory unit 20, and a frequency synthesis circuit 30. The frequency synthesis circuit 30 outputs a digital waveform signal with a set frequency based on a frequency control word through phase accumulation. The phase memory unit 20 receives the initial memory value corresponding to the memorized frequency and the frequency control word, and performs phase accumulation synchronously with the frequency synthesis circuit 30 based on the initial memory value and the frequency control word corresponding to the memorized frequency as a step size, to obtain the accumulated memory value. The control module 10 acquires a set frequency and outputs a frequency control word according to the set frequency, sending the frequency control word to the frequency synthesis circuit 30. The control module 10 also outputs the initial memory value corresponding to the memorized frequency and the frequency control word to the phase memory unit 20 based on a phase memory instruction. When a new set frequency is acquired, the control module 10 determines whether the frequency control word corresponding to the new set frequency is the same as the frequency control word corresponding to the memorized frequency in the phase memory unit 20. If they are the same, the current accumulated memory value corresponding to the memorized frequency is output to the frequency synthesis circuit 30 as the initial value for phase accumulation by the frequency synthesis circuit 30.

[0036] Please refer to Figure 7 This is a schematic diagram of the functional modules of a frequency synthesis circuit in one embodiment. In one embodiment, the frequency synthesis circuit 30 includes a phase accumulator 31, a phase-to-amplitude converter 32, and a signal output module 40. The phase accumulator 31 is used to acquire a frequency control word and accumulate the phase in steps of the frequency control word according to a preset reference clock, outputting the accumulated phase value. The phase-to-amplitude converter 32 is used to output an amplitude control signal based on the accumulated phase value and a set waveform type. For example, by looking up a table, the amplitude value is found in the phase-to-amplitude correspondence table corresponding to the set waveform type based on the accumulated phase value, and a digital amplitude control signal is output. The signal output module 40 is used to output an analog signal with a set frequency based on the amplitude control signal.

[0037] The phase memory unit 20 is configured to include at least one memory sub-unit 21. Each memory sub-unit 21 is connected to the phase accumulator 31 and is used to receive the initial memory value and frequency control word corresponding to the memory frequency from the phase accumulator 31. Based on the initial memory value, the phase is accumulated according to the beat of the reference clock with the frequency control word corresponding to the memory frequency as the step size to obtain the accumulated memory value.

[0038] The control module 10 outputs a frequency control word to the phase accumulator 31, configures a corresponding memory sub-unit 21 for at least one memorized frequency in the phase memory unit 20 based on the phase memory instruction, outputs the initial memory value and frequency control word corresponding to the memorized frequency to the corresponding memory sub-unit 21, updates the frequency control word output to the phase accumulator 31 based on the new set frequency, determines whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, and if so, outputs the current accumulated memory value corresponding to the memorized frequency to the phase accumulator 31 as the initial value for phase accumulation. In one embodiment, the memorized frequency is the current set frequency when the control module 10 receives the phase memory instruction, and the initial memory value is the phase accumulation value currently output by the phase accumulator 31 when the control module 10 receives the phase memory instruction, or the phase accumulation value currently output by the phase accumulator 31 when the control module 10 receives the new set frequency. In one embodiment, the frequency to be memorized is the current set frequency and subsequent set frequencies when the control module 10 receives the phase memory command. The initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator 31 each time a new set frequency is received, or the initial memory value is any phase accumulation value corresponding to the new set frequency currently output by the phase accumulator 31 each time a new set frequency is received.

[0039] like Figure 7 As shown, the memory subunit 21 includes a memory phase accumulator 211 and a control word memory 212. The memory phase accumulator 211 and the control word memory 212 are respectively connected to the phase accumulator 31. The control word memory 212 is used to acquire and store the frequency control word corresponding to the memory frequency. The memory phase accumulator 211 is used to perform phase accumulation synchronously with the frequency synthesis circuit 30 based on the initial memory value, using the frequency control word corresponding to the memory frequency as the step size, and obtain the accumulated memory value. In one embodiment, the signal output module 40 includes a digital-to-analog converter 41 and a phase-locked loop (PLL) 42. The input terminal of the digital-to-analog converter 41 is connected to the output terminal of the phase / amplitude converter 32, and is used to convert the digital amplitude control signal output by the phase / amplitude converter 32 into an analog signal. The output terminal of the digital-to-analog converter 41 is connected to the PLL 42, and the PLL 42 is used to phase-lock the lower frequency analog signal output by the digital-to-analog converter 41 to obtain a higher frequency output signal. In one embodiment, the analog signal output by the signal output module 40 is a radio frequency (RF) signal. When the output signal is a low-frequency signal, the signal output module 40 may include a digital-to-analog converter 41 but not a phase-locked loop 42. The digital-to-analog converter 41 converts the digital amplitude control signal output by the phase / amplitude converter 32 into an analog signal.

[0040] like Figure 6As shown, in one embodiment, it further includes a human-computer interaction module 50 and a clock setting unit 60. The user inputs setting frequency and / or phase memory commands through the human-computer interaction module 50. In one embodiment, the phase memory command is generated based on the user triggering the phase memory function key, or based on the user's setting operation of a new setting frequency. The clock setting unit 60 is used to provide clock signals to the frequency synthesis circuit 30 and the phase memory unit 20.

[0041] Please refer to Figure 8 The diagram below shows the functional structure of a phase memory unit in one embodiment. In one embodiment, the phase memory unit 20 includes n memory sub-units 21, where n is a natural number greater than 1. Each memory sub-unit 21 is used to record a memory frequency point fm, where m ∈ [1, n]. Each memory sub-unit 21 is connected to a phase accumulator 31. The memory phase accumulator 211 of each memory sub-unit 21 shares the same operating clock (reference clock) with the phase accumulator 31. When the phase memory unit needs to store multiple memory frequencies (f1, f2, f3, ..., fm, ..., fn), they can be stored independently by the n memory sub-units 21.

[0042] Please refer to Figure 9 The diagram below shows a structural block diagram of a processing device in one embodiment. In another embodiment, a signal processing device is disclosed for outputting a digital waveform signal. The digital waveform signal is an amplitude control signal generated based on a frequency control word and through phase accumulation. The processing device includes a phase memory unit 20 and a control module 10. The phase memory unit 20 is used to acquire an initial memory value and a frequency control word corresponding to the memorized frequency, and synchronizes the phase accumulation during the generation of the digital waveform signal with the frequency control word of the memorized frequency as a step size, based on the initial memory value, to obtain an accumulated memory value. The control module 10 is used to output the initial memory value and the frequency control word corresponding to the memorized frequency to the phase memory unit based on a phase memory instruction. When the processing device pre-outputs a new digital waveform signal, it determines whether the set frequency of the new digital waveform signal is the same as the memorized frequency in the phase memory unit. If so, the accumulated memory value in the phase memory unit is used as the initial value for phase accumulation during the generation of the digital waveform signal.

[0043] Please refer to Figure 10 This is a flowchart illustrating a signal phase memory method in one embodiment. This application also discloses a signal phase memory method, comprising: Step 101: Obtain waveform parameters.

[0044] Obtain the user's settings for the required output waveform frequency and waveform type.

[0045] Step 102: Generate the frequency control word.

[0046] A frequency control word is generated based on a set frequency, so that the frequency synthesis circuit can output a waveform signal with the set frequency by phase accumulation based on the frequency control word.

[0047] Step 103: Perform phase memory.

[0048] The system monitors the user-input phase memory command and, based on the command, outputs the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit. It then controls the phase memory unit to synchronously accumulate phase values ​​with the frequency control word corresponding to the frequency to be memorized, based on the initial memory value, and obtains the accumulated memory value. In one embodiment, the frequency to be memorized is the current set frequency when the control module receives the phase memory command, and the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency. In another embodiment, the frequency to be memorized includes the current set frequency and subsequent set frequencies when the control module receives the phase memory command, and the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received.

[0049] Step 104: Change the frequency control word.

[0050] The frequency control word is updated based on the new set frequency.

[0051] Step 105: Match frequency values.

[0052] The frequency control word corresponding to the new set frequency is matched with the frequency control word corresponding to the memorized frequency that has been stored in the phase memory unit.

[0053] Step 106, output signal.

[0054] If the match is successful, the accumulated memory value corresponding to the memorized frequency that matches the new set frequency is used as the initial value for the frequency synthesis circuit to perform phase accumulation based on the frequency control word, so as to output a waveform with the same phase as the memorized frequency. If the match is unsuccessful, the updated frequency control word is output to the frequency synthesis circuit, so that the frequency synthesis circuit can output a waveform signal with the new set frequency by phase accumulation based on the updated frequency control word.

[0055] The phase memory device disclosed in this application embodiment can be applied in spectrum analyzers and signal generators as a signal source.

[0056] To facilitate understanding of how the signal processing apparatus disclosed in this application implements the phase memory function, the following example uses the implementation of the phase memory function of an RF channel, specifically including: Please refer to Figure 11 This is a block diagram illustrating the functional implementation of the RF channel phase memory function in one embodiment. In one embodiment of this application, the RF channel transmitter adopts a hybrid frequency synthesizer architecture, including a phase memory unit 20, a frequency synthesis circuit 30, a signal output module 40, and an antenna 200. The phase memory unit 20 is located in the signal output channel (FPGA) 100. A reference clock is output by a clock setting unit. The signal output module 40 includes a digital-to-analog converter 41 and a phase-locked loop (PLL) 42. The frequency synthesis circuit 30 includes a phase accumulator 31 and a phase-to-amplitude converter 32. The phase accumulator 31 acquires a frequency control word and performs phase accumulation according to the reference clock with the frequency control word as the step size, outputting the accumulated phase value. The phase-to-amplitude converter 32 outputs an amplitude-controlled DDS-CTRL signal (amplitude control signal) based on the accumulated phase value and a set waveform type. The signal output module 40 outputs an analog signal (RF signal) with a set frequency based on the amplitude control signal (DDS-CTRL signal). Phase accumulator 31 accumulates a frequency control word once per operating clock cycle (the operating clock of the signal output channel, i.e., the reference clock), outputting a linearly increasing phase value. Phase / amplitude converter 32 is typically a lookup table that maps the phase value output by phase accumulator 31 to an amplitude value (e.g., a sampled value of a sine wave) and outputs a DDS-CTRL signal (essentially a digital sequence). The formula for obtaining the frequency value of the DDS-CTRL signal is: f out = (X / 2 N ) * f clk ; Where N is the bit width of the phase accumulator, X is the frequency control word, and f clk This is the operating clock frequency (reference clock frequency) of the signal output channel. The output frequency f can be changed with extremely fine precision by altering the frequency control word X. out .

[0057] A digital-to-analog converter (DAC) 41 receives the DDS-CTRL signal and converts it into a stepped analog waveform signal (DDS signal). The sampling frequency of the DAC 41 is controlled by a preset frequency DAC sampling clock. Since the DDS signal output by the DAC contains a large number of high-frequency harmonic components, in one embodiment, a low-pass filter (LPF) is also needed to filter the DDS signal to remove high-frequency noise and obtain an analog sine wave of the target frequency. The low-pass filtered DDS signal is used as the reference input signal for a phase-locked loop (PLL). The PLL 42 up-converts the DDS signal to the required radio frequency while cleaning the spectrum. In one embodiment, the PLL 42 includes a phase detector, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The phase detector compares the phase difference between the DDS signal (used as a reference signal) and the VCO signal of the feedback loop and outputs an error voltage. The loop filter filters out high-frequency components in the error voltage, generating a smooth DC control voltage. The design of the filter determines the locking speed, bandwidth, and noise performance of the PLL. The oscillation frequency of the voltage-controlled oscillator (VCO) is determined by the DC control voltage and is used to generate an RF signal at the target frequency. This RF signal is ultimately transmitted through antenna 200. The frequency divider divides the high-frequency signal generated by the VCO by N and then sends it back to the phase detector for comparison with the reference signal. When the phase-locked loop is locked, the frequency of the DDS signal and the loop lock frequency are: f vco / N = f ref ; Where N is the number of division stages in the frequency divider, f vco For loop-locked frequency, f ref The frequency of the DDS signal.

[0058] The final output frequency is: f rf = f vco = N * f ref ; Among them, f ref f is the frequency of the low-frequency DDS signal. rf This refers to the frequency of the RF signal.

[0059] By changing the N-division ratio, the output frequency can be varied over a wide range. The frequency control word of the DDS can be fine-tuned to change the f-value of the DDS signal. ref It allows for fine-tuning of the frequency within the frequency band corresponding to each N value.

[0060] In one embodiment, the phase memory unit 20 in the signal output channel 100 includes at least one memory sub-unit 21, each phase memory unit 20 being used to record a memory frequency point fm of the RF signal. The memory sub-unit 21 includes a memory phase accumulator 211 and a control word memory 212. The memory phase accumulator 211 is used to synchronize the phase accumulator 31 when performing the phase memory function. The synchronized phase accumulator 31 includes: After the phase memory function is enabled, the memory phase accumulator 211 inherits the phase accumulation value of the phase accumulator 31 and accumulates the phase accumulation value in each working clock cycle (the working clock of the signal output channel). Each accumulated value is related to the frequency control word of the pre-memorized memory frequency point fm. The control word memory 212 is used to store the frequency control word FTW of the phase / amplitude converter 32 when the phase memory function is enabled. fm Among them, the phase / amplitude converter 32 is based on the frequency control word FTW fm Output the DDS-CTRL signal to control the frequency of the RF signal output from the RF channel, i.e., the frequency of the RF signal output by the phase-locked loop 42 and the frequency control word FTW. fm Related.

[0061] When the RF channel output needs to be switched back to the memory frequency point f m When the RF signal is received (i.e., when the phase recovery function is executed), the phase accumulator 31 synchronizes with the memory phase accumulator 211. The synchronized memory phase accumulator 211 includes: Phase accumulator 31 inherits the phase accumulation value from memory phase accumulator 211, and accumulates the phase accumulation value in each working clock cycle (the working clock of the signal output channel), and outputs the accumulated phase accumulation value to phase / amplitude converter 32. Phase / amplitude converter 32 retrieves the frequency control word FTW from control word memory 212. fm and reset the frequency control word FTW of the phase / amplitude converter 32 to the frequency control word FTW. fm When the reset is successful, the DDS-CTRL signal is output. Since the phase accumulator 31 synchronizes with the memory phase accumulator 211 to be updated during the phase recovery function, the phase state of the RF signal will be consistent with that when the phase memory function is enabled, thus realizing the phase memory function.

[0062] Please refer to Figure 12 This is a flowchart illustrating a phase memory method for an RF channel in one embodiment, including: Step 201: Configure the RF channel output signal.

[0063] The RF channel is enabled and operating normally, outputting a variable-frequency RF signal. The signal output channel (FPGA) generates a variable-frequency amplitude control signal (DDS-CTRL signal). The phase accumulator accumulates one frequency control word per clock cycle and outputs it to the phase-to-amplitude converter. The phase-to-amplitude converter obtains the DDS-CTRL signal based on the accumulated value output by the phase accumulator. The DDS-CTRL signal controls the digital-to-analog converter to output a lower-frequency analog signal (DDS signal). The DDS signal is then input to a phase-locked loop (PLL) to obtain a higher-frequency RF signal. By changing the frequency control word and the N division ratio in the PLL, an RF signal of arbitrary frequency can be output.

[0064] Step 202: Monitor the phase memory command.

[0065] The system monitors the user-input phase memory command and, based on this command, outputs the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit. It then controls the phase memory unit to synchronously accumulate phase values ​​with the frequency control word corresponding to the frequency to be memorized, based on the initial memory value, and obtains the accumulated memory value. When executing the phase memory function, it needs to be implemented at a specific memory frequency f1. First, it must ensure that the RF channel outputs an RF signal corresponding to the memory frequency f1. Then, in response to the phase memory execution command, it uses the current phase / amplitude converter's frequency control word FTW. fm Latched to the control word memory. The phase / amplitude converter operates according to the frequency control word FTW. fm Output the DDS-CTRL signal to control the frequency of the RF signal output from the RF channel, i.e., the frequency of the RF signal output by the phase-locked loop (PLL) and the frequency control word FTW. fm Related. Additionally, a synchronous memory phase accumulator and a phase accumulator will be established, so that the phase accumulation value of the phase accumulator is inherited by the memory phase accumulator, and the phase accumulation value will be accumulated in each working clock cycle. Each accumulated value is related to the frequency control word of the pre-memorized memory frequency point fm.

[0066] Step 203: Change the output RF signal.

[0067] The RF channel changes the frequency of the currently output RF signal according to the channel signal frequency change command.

[0068] Step 204: Determine the frequency control word.

[0069] When performing a frequency change on the RF channel, if the phase memory unit stores a memory frequency point fm, it retrieves the frequency control word of the RF signal to be changed and compares it one by one with all the memory frequency points fm stored in the phase memory unit. If the memory frequency point fm does not contain the frequency control word of the RF signal to be changed, step 205 is executed, and the frequency of the RF signal output by the RF channel is directly changed. If the frequency control word of the RF signal to be changed is stored in the phase memory unit, then step 206 is executed.

[0070] Step 205, direct frequency conversion output.

[0071] When the frequency change of the RF channel is performed for the first time, if the phase memory unit has not yet saved any memory frequency point fm, or has only recorded the memory frequency point f1 before the current change, the frequency of the RF signal output by the RF channel is changed directly. Specifically, the frequency of the output RF signal can be changed by changing the frequency control word or the N division ratio in the phase lock.

[0072] Step 206: Inherit the accumulated value.

[0073] If the frequency control word of the RF signal to be modified is stored in the phase memory unit, then the RF signal corresponding to the memory frequency point fm of the frequency control word needs to be restored, i.e., the phase recovery execution instruction is executed. The phase accumulator and the memory phase accumulator are synchronized to inherit the accumulated value of the frequency control word in the memory phase accumulator. After synchronization, the phase accumulation value is accumulated in each working clock cycle, and the accumulated phase accumulation value is output to the phase / amplitude converter. Additionally, in response to the phase recovery execution instruction, the frequency control word FTW latched in the control word memory is retrieved. fm .

[0074] Step 207: Output the memorized RF signal.

[0075] Reset the frequency control word FTW of the phase / amplitude converter to the frequency control word FTW. fm When the reset is successful, a digital waveform signal is output to restore the frequency of the RF signal output by the RF channel to the frequency corresponding to the memory frequency point fm. Since the memory phase accumulator in the memory sub-unit is constantly updated, the phase state of the RF signal will also be consistent with that before the frequency change, thus realizing the phase memory function of the RF channel transmitter. Because the channel phase accumulator is synchronized dynamically in the memory sub-unit, it is ensured that the recovered RF signal phase state is consistent with that before the frequency change.

[0076] In one embodiment, when performing the phase memory function, a phase memory start command and a phase memory end command are sequentially acquired and executed. When acquiring the phase memory start command, the phase memory unit saves the phase of each frequency change according to the order of frequency control word changes and / or the frequency value change pattern (magnitude pattern, equal frequency interval pattern, etc.). When acquiring the phase memory end command, the phase memory function is stopped, and no new phases are saved. Please refer to [reference needed]. Figure 13 This is a flowchart illustrating the RF channel phase memory process in one embodiment, specifically including: Step 301: Monitor the phase memory start command.

[0077] When the phase memory start command is received, the memory function of the phase memory unit is activated.

[0078] Step 302: Activate automatic memory mode.

[0079] When the frequency to be memorized is the current set frequency when the control module receives the phase memory command, the initial memory value is the phase accumulation value currently output by the phase accumulator when the control module receives the phase memory command, or the phase accumulation value currently output by the phase accumulator when the control module receives a new set frequency. When the frequency to be memorized includes the current set frequency and subsequent set frequencies when the control module receives the phase memory command, the initial memory value is the phase accumulation value of the previous set frequency currently output by the phase accumulator each time a new set frequency is received, or the initial memory value is the phase accumulation value corresponding to the new set frequency currently output by the phase accumulator each time a new set frequency is received. That is, after obtaining the phase memory start command, the phase of each frequency change is saved according to the order of frequency control word changes and / or the frequency value change pattern. In one embodiment, during the time period between executing the phase memory start command and the phase memory end command, the phase memory unit only records the phase signal of the frequency change.

[0080] Step 303: Obtain the phase memory end command.

[0081] The phase memory unit's memory function is disabled, and the phase memory function is not executed when the output signal frequency of the RF channel changes.

[0082] Step 304, repetition frequency change process.

[0083] It acquires and responds to phase recovery commands, and sequentially recovers the frequency and phase transformation process of the channel output RF signal according to the order of phase storage in the phase memory unit and / or the frequency value change pattern during the execution of the phase memory start command and phase memory end command, thereby realizing the dynamic reproduction of the frequency change process of the channel output signal.

[0084] The signal processing apparatus disclosed in this application embodiment is used to generate digital waveform signals based on a frequency control word and through phase accumulation. It includes a phase memory unit and a control module. The phase memory unit is used to acquire an initial memory value and a frequency control word corresponding to the memorized frequency, and synchronizes the phase accumulation during digital waveform signal generation with the frequency control word of the memorized frequency as a step size based on the initial memory value to acquire an accumulated memory value. The control module is used to output the initial memory value and the frequency control word corresponding to the memorized frequency to the phase memory unit, and when the set frequency of the signal pre-output signal of the signal processing device is the memorized frequency in the phase memory unit, it uses the synchronized accumulated memory value as the initial value for phase accumulation during digital waveform signal generation. Because the accumulated memory value is stored using a dynamic synchronous phase accumulation method, the phase memory function can be realized when the signal frequency is recovered.

[0085] Those skilled in the art will understand that, in the above embodiments, some or all of the frequency synthesis circuit, phase memory unit, and control module can be integrated into one or more integrated circuit chips, or can be implemented in a discrete device manner, either partially or entirely.

[0086] In one embodiment, after receiving the coherent output command and the specified signal coherent channel, the coherent control module 1 further determines whether the output signal frequencies of the signal coherent channels are the same. If they are the same, it outputs a phase memory command to the signal coherent channel; if they are different, it adjusts the output signal frequencies of each signal coherent channel to the same frequency before outputting the phase memory command to the signal coherent channel. Adjusting the output signal frequencies of each signal coherent channel to the same frequency includes: Obtain the reference channel specified by the user in the signal coherence channel, and adjust the frequency of the output signal of other signal coherence channels to the frequency of the output signal of the reference channel; or obtain the frequency set by the user, and adjust the frequency of the output signal of each signal coherence channel to the frequency set by the user.

[0087] In one embodiment, the signal coherence channel is specified based on user input via a human-machine interface, and the coherence output command and / or phase memory command are generated based on user input via the human-machine interface. In another embodiment, the signal output by the signal output channel 100 is a radio frequency signal.

[0088] Please refer to Figure 14This is a schematic diagram of the clock setting unit connection in one embodiment. In one embodiment, the signal control system further includes a clock setting unit 60, used to provide a reference clock signal with a reference frequency to each phase memory device 2, so that the phase memory devices 2 of the signal coherence channel perform phase accumulation using the same clock beat. In one embodiment, the frequency synthesis circuit 30 includes a phase accumulator 31, a phase / amplitude converter 32, and a signal output module 40. The phase accumulator 31 is connected to the clock setting unit 60, used to acquire a frequency control word, and perform phase accumulation according to the reference clock with the frequency control word as the step size, outputting the phase accumulation value. The phase / amplitude converter 32 outputs an amplitude-controlled digital waveform signal according to the phase accumulation value and the set waveform type. The signal output module 40 is used to output an analog signal with a set frequency according to the amplitude-controlled digital waveform signal.

[0089] like Figure 9 As shown, the phase memory unit 20 is configured to include at least one memory subunit 21. Each memory subunit 21 is connected to the clock setting unit 60 and the phase accumulator 31, respectively. It receives the initial memory value and frequency control word corresponding to the frequency being memorized from the phase accumulator 31, and continues to accumulate phase based on the initial memory value, using the frequency control word corresponding to the frequency being memorized as a step size according to the beat of the reference clock, to obtain the accumulated memory value. The control module 10 outputs the frequency control word to the phase accumulator, configures a corresponding memory subunit for at least one frequency being memorized in the phase memory unit based on the phase memory instruction, outputs the initial memory value and frequency control word corresponding to the frequency being memorized to the corresponding memory subunit, updates the frequency control word output to the phase accumulator based on the new set frequency, determines whether the new frequency control word is the same as the frequency control word corresponding to the frequency being memorized, and if so, outputs the current accumulated memory value corresponding to the frequency being memorized to the phase accumulator 31 as the initial value for phase accumulation by the phase accumulator 31. In one embodiment, the memory subunit 21 includes a memory phase accumulator 211 and a control word memory 212. The memory phase accumulator 211 and the control word memory 212 are respectively connected to the phase accumulator 31. The control word memory 212 is used to acquire and store the frequency control word corresponding to the memory frequency. The memory phase accumulator 211 is used to perform phase accumulation synchronously with the frequency synthesis circuit 30 based on the initial memory value, with the frequency control word corresponding to the memory frequency as the step size, and obtain the accumulated memory value.

[0090] In one embodiment, the signal output module 40 includes a digital-to-analog converter 41 and a phase-locked loop (PLL) 42. The input terminal of the digital-to-analog converter 41 is connected to the output terminal of the phase-to-amplitude converter 32, and is used to convert the digital amplitude control signal output by the phase-to-amplitude converter 32 into an analog signal. The output terminal of the digital-to-analog converter 41 is connected to the PLL 42, and the PLL 42 is used to lock the lower frequency analog signal output by the digital-to-analog converter 41 to obtain a higher frequency output signal.

[0091] like Figure 14 As shown, the clock setting unit 60 includes a frequency source element 61, a power divider module 62, a clock buffer module 64, and a frequency multiplier 63. The frequency source element 61 generates a reference clock with a preset single frequency. The power divider module 62 splits the reference clock generated by the frequency source element 61 into two paths. The power divider module 62 includes a first input terminal, a first output terminal, and a second output terminal. Its first input terminal is connected to the frequency source element 61, its first output terminal is connected to the clock buffer module 64, and its second output terminal is connected to the frequency multiplier 63. The clock buffer module 64 converts the reference clock into a reference clock with a reference frequency and outputs it to the phase accumulator 31 and phase memory unit 20 of each phase memory device 2 as their operating clock. The frequency multiplier 63 converts the reference clock into a sampling clock signal with a preset frequency value and outputs the sampling clock signal to the digital-to-analog converter 41 as its sampling clock. In one embodiment, to improve accuracy, the frequency source element 61 uses a 100MHz temperature-controlled crystal oscillator. In one embodiment, to improve system integration, the output of the temperature-controlled crystal oscillator is used to obtain the sampling clock for the digital-to-analog converter via a power divider module 62 and a frequency multiplier 63. In another embodiment, the sampling clock may also be provided by another frequency source independently.

[0092] In one embodiment of this application, multiple signal output channels of the signal control system have phase memory functionality. To achieve phase coherence between any two signal output channels (channel a and channel b), phase synchronization between the two signal output channels is first required. That is, the phase difference between the two signal output channels remains constant when the FTW (Focus Transmission Time) is unchanged, and the sampling clock signals of the digital-to-analog converters (DACs) of the multiple signal output channels are shared. Based on the phase synchronization of channels a and b, assuming the current output frequency of the two channels is f1, the phase memory command is executed simultaneously on channels a and b. According to the aforementioned phase memory implementation principle, the phase relationship of a single channel is maintained by continuous updates from a phase accumulator. The update of the phase accumulator is controlled by the operating clock. Therefore, synchronizing the operating clock ensures that the update speed of the phase accumulator between the two channels is also consistent, thus ensuring that when the output frequency fout of one or both channels changes to another value and then back to f1, its phase relationship remains unchanged, without flipping or shifting. This achieves phase coherence between the two channels.

[0093] Please refer to Figure 15 This is a schematic diagram illustrating the connection of a clock setting unit between multiple systems in one embodiment. In one embodiment, the clock setting unit 60 further includes a switch control module 65. The switch control module 65 has multiple output terminals, with its input terminal connected to a frequency source element 61. The multiple output terminals are used to connect to a power divider module 62 and another power divider module 62 of a signal control system, respectively. The power divider module 62 also includes a second input terminal for receiving a reference clock from the switch control module 65 of the other signal control system. The clock setting unit connects the operating clock and the sampling clock to another system through the power divider module and the switch module, enabling the two systems to share the signal generated by the same temperature-controlled crystal oscillator. This ensures that the operating clock and sampling clock between any channels in the two systems are synchronized, thereby achieving phase coherence functionality between any channels in the systems.

[0094] Please refer to Figure 16 The diagram below illustrates a signal phase coherence method. Based on the signal control system described above, an embodiment of this application also discloses a signal phase coherence method, comprising: Step 401, monitoring instructions.

[0095] The system monitors user-inputted coherent output commands and specified coherent signal channels that require phase coherence on the output signal. These coherent signal channels are selected from multiple signal output channels.

[0096] Step 402, output the instruction.

[0097] Based on the coherent output command and the specified signal coherent channel, output phase memory command to the signal coherent channel.

[0098] Step 403: Execute the instruction.

[0099] The phase memory function is applied to the signal output from the coherent signal channel based on the phase memory instruction. This enables the output signal of the coherent signal channel to have a phase memory function, so that when the initial frequency is changed during operation and then switched back to the initial frequency, the phase of the output signal returns to the phase of the initial frequency, thereby generating phase coherence between the output signals of the coherent signal channel.

[0100] Please refer to Figure 17 This is a schematic diagram illustrating the execution flow of the phase memory function in one embodiment. In one embodiment, the phase memory function is executed on the signal output from the signal coherence channel based on the phase memory instruction, including: Step 501: Obtain the output waveform parameters.

[0101] Obtain the user's settings for the required output waveform frequency and waveform type.

[0102] Step 502: Generate the output signal.

[0103] A frequency control word is generated based on a set frequency, so that the frequency synthesis circuit can output a waveform signal with the set frequency by phase accumulation based on the frequency control word.

[0104] Step 503: Execute phase memory.

[0105] The system monitors the phase memory command input by the user. Based on the phase memory command, it outputs the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit. It then controls the phase memory unit to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the frequency to be memorized, and obtains the accumulated memory value.

[0106] Step 504: Perform phase recovery.

[0107] The frequency control word is updated based on the new set frequency. It is then matched with the frequency control word corresponding to the previously memorized frequency stored in the phase memory unit. If the match is successful, the accumulated memory value corresponding to the previously memorized frequency that matches the new set frequency is used as the initial value for phase accumulation by the frequency synthesis circuit based on the frequency control word, so as to output a waveform with phase consistent with the previously memorized frequency. If the match fails, the updated frequency control word is output to the frequency synthesis circuit, so that the frequency synthesis circuit outputs a waveform signal with the new set frequency through phase accumulation based on the updated frequency control word.

[0108] The signal phase coherence method disclosed in this application first monitors the user-input coherent output command and the specified signal coherence channel that needs to achieve phase coherence on the output signal; then, based on the coherent output command and the specified signal coherence channel, it outputs a phase memory command to the signal coherence channel; finally, based on the phase memory command, it performs a phase memory function on the signal output from the signal coherence channel, so that the output signal of the signal coherence channel has a phase memory function, so that when its initial frequency is changed during operation and then switched back, its phase returns to the initial frequency phase, thereby achieving phase coherence between the memoryed channel output signals. By applying the phase memory function of the signal output channel to achieve phase coherence recovery, and thus establishing and maintaining a predictable and repeatable multi-signal phase relationship, the implementation of phase coherence is simpler, more reliable, and faster.

[0109] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0110] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A signal control system with phase coherence function, characterized in that, Includes a coherent control module and multiple signal output channels; Each of the signal output channels includes a phase memory device, which is used to perform a phase memory function on the signal output by the signal output channel based on a phase memory command, so that the output signal has a phase memory function, so that when its initial frequency is changed during operation and then switched back to the initial frequency, the phase of the output signal returns to the phase of the initial frequency. The coherence control module is connected to the phase memory device in each of the signal output channels; The coherent control module is used to monitor the specified signal coherent channel and coherent output command that need to achieve phase coherence function on the output signal, and output the phase memory command to the signal coherent channel based on the coherent output command. The signal coherent channel is selected from multiple signal output channels. And / or, the coherence control module is used to monitor the specified signal coherence channel and phase memory command that need to achieve phase coherence function on the output signal, and output the phase memory command to the phase memory device of the signal coherence channel, wherein the signal coherence channel is selected from a plurality of the signal output channels.

2. The signal control system as described in claim 1, characterized in that, The signal coherent channel is specified based on user input through the human-computer interaction interface, and the coherent output command and the phase memory command are generated based on user input through the human-computer interaction interface.

3. The signal control system as described in claim 1, characterized in that, The phase memory device includes: A frequency synthesis circuit is used to perform phase accumulation based on a frequency control word according to the clock beat, and output a digital waveform signal with a set frequency based on the accumulation result. The phase memory unit is used to receive the initial memory value and frequency control word corresponding to the memory frequency, and to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the memory frequency as the step size, and to obtain the accumulated memory value. The control module is used to acquire a set frequency and output a frequency control word according to the set frequency, and output the frequency control word to the frequency synthesis circuit. The control module is also used to output the initial memory value corresponding to the memory frequency and the frequency control word to the phase memory unit based on the phase memory instruction, and when a new set frequency is acquired, to determine whether the frequency control word corresponding to the new set frequency is the same as the frequency control word corresponding to the memory frequency in the phase memory unit. If they are the same, the current accumulated memory value corresponding to the memory frequency is output to the frequency synthesis circuit as the initial value for the phase accumulation of the frequency synthesis circuit.

4. The signal control system as described in claim 3, characterized in that, It also includes a clock setting unit for providing a reference clock signal with a reference frequency to each of the phase memory devices, so that the phase memory devices of the signal coherence channel perform phase accumulation using the same clock beat.

5. The signal control system as described in claim 4, characterized in that, The frequency synthesis circuit includes a phase accumulator, a phase-to-amplitude converter, and a signal output module. The phase accumulator is connected to a clock setting unit and is used to acquire a frequency control word and perform phase accumulation according to the reference clock with the frequency control word as the step size, outputting a phase accumulation value. The phase-to-amplitude converter outputs an amplitude-controlled digital waveform signal based on the phase accumulation value and a set waveform type. The signal output module is used to output an analog signal with a set frequency based on the amplitude-controlled digital waveform signal. The phase memory unit is configured to include at least one memory sub-unit. Each memory sub-unit is connected to a clock setting unit and a phase accumulator, respectively. It is used to receive an initial memory value and a frequency control word corresponding to the memory frequency from the phase accumulator, and to continue to accumulate phase based on the initial memory value, with the frequency control word corresponding to the memory frequency as the step size according to the beat of the reference clock, to obtain the accumulated memory value. The control module is used to output the frequency control word to the phase accumulator, configure a corresponding memory sub-unit for at least one memorized frequency in the phase memory unit based on the phase memory instruction, output the initial memory value and frequency control word corresponding to the memorized frequency to the corresponding memory sub-unit, update the frequency control word output to the phase accumulator based on the new set frequency, determine whether the new frequency control word is the same as the frequency control word corresponding to the memorized frequency, if so, output the current accumulated memory value corresponding to the memorized frequency to the phase accumulator as the initial value for phase accumulation by the phase accumulator.

6. The signal control system as described in claim 5, characterized in that, The signal output module includes a digital-to-analog converter (DAC) and a phase-locked loop (PLL). The input terminal of the DAC is connected to the output terminal of the phase / amplitude converter (PAC) and is used to convert the digital amplitude control signal output by the PAC into an analog signal. The output terminal of the DAC is connected to the PLC, which is used to lock the lower frequency analog signal output by the DAC into a higher frequency output signal.

7. The signal control system as described in claim 6, characterized in that, The clock setting unit includes a frequency source element, a power divider module, a clock buffer module, and a frequency multiplier; The frequency source element is used to generate a reference clock with a preset single frequency; The power divider module is used to divide the reference clock generated by the frequency source element into two paths. The power divider module includes a first input terminal, a first output terminal and a second output terminal. Its first input terminal is connected to the frequency source element, its first output terminal is connected to the clock buffer module and its second output terminal is connected to the frequency multiplier. The clock buffer module is used to convert the reference clock into a reference clock with a reference frequency and output it to the phase accumulator and phase memory unit of each phase memory device, so as to serve as the working clock of the phase accumulator and phase memory unit. The frequency multiplier is used to convert the reference clock into a sampling clock signal with a preset frequency value, and outputs the sampling clock signal to the digital-to-analog converter as the sampling clock of the digital-to-analog converter.

8. The signal control system as described in claim 7, characterized in that, The clock setting unit further includes a switch control module, which has multiple output terminals. Its input terminal is connected to the frequency source element, and the multiple output terminals are used to connect to the power divider module and the power divider module of another signal control system, respectively. The power divider module also includes a second input terminal for receiving a reference clock from the switch control module of another signal control system.

9. The signal control system as described in claim 1, characterized in that, After receiving the coherent output command and the specified signal coherent channel, the coherent control module further determines whether the output signal frequencies of the signal coherent channels are the same. If they are the same, it outputs the phase memory command to the signal coherent channel. If they are different, it adjusts the output signal frequencies of each signal coherent channel to the same frequency before outputting the phase memory command to the signal coherent channel. Adjusting the output signal frequencies of each signal coherent channel to the same frequency includes: obtaining a reference channel specified by the user in the signal coherent channels and adjusting the frequency of the output signals of other signal coherent channels to the frequency of the reference channel; or obtaining a frequency set by the user and adjusting the output signal frequencies of each signal coherent channel to the user-set frequency.

10. A signal phase coherence method for enabling a signal control system to output a phase-coherent signal, the signal control system comprising multiple signal output channels, characterized in that... The signal phase coherence method includes: The system monitors the user-inputted coherent output command and the specified signal coherent channel that needs to achieve phase coherence on the output signal, wherein the signal coherent channel is selected from a plurality of the signal output channels; Based on the coherent output command and the specified signal coherent channel, a phase memory command is output to the signal coherent channel; The phase memory function is executed on the signal output by the signal coherence channel based on the phase memory command, so that the output signal of the signal coherence channel has the phase memory function, so that when the initial frequency is changed during operation and then switched back to the initial frequency, the phase of the output signal returns to the phase of the initial frequency, thereby generating phase coherence between the output signals of the signal coherence channel.

11. The signal phase coherence method as described in claim 10, characterized in that, The step of performing phase memory function on the signal output from the signal coherence channel based on phase memory instructions includes: Obtain the user's settings for the required output waveform frequency and waveform type; A frequency control word is generated based on a set frequency, so that the frequency synthesis circuit can output a waveform signal with the set frequency by phase accumulation based on the frequency control word; Monitor the phase memory command input by the user; based on the phase memory command, output the initial memory value and frequency control word corresponding to the frequency to be memorized to the phase memory unit, and control the phase memory unit to perform phase accumulation synchronously with the frequency synthesis circuit based on the initial memory value and the frequency control word corresponding to the frequency to be memorized as the step size, and obtain the accumulated memory value; The frequency control word is updated based on the new set frequency; The frequency control word corresponding to the new set frequency is matched with the frequency control word corresponding to the memorized frequency stored in the phase memory unit; If the match is successful, the accumulated memory value corresponding to the memory frequency that matches the new set frequency will be used as the initial value for the frequency synthesis circuit to perform phase accumulation based on the frequency control word, so as to output a waveform that is in phase with the memory frequency. If the matching fails, the updated frequency control word is output to the frequency synthesis circuit, so that the frequency synthesis circuit can output a waveform signal with a new set frequency by phase accumulation based on the updated frequency control word.

12. A computer-readable storage medium, characterized in that, The medium stores a computer program that can be executed by a processor to implement the signal phase coherence method as described in any one of claims 10 to 11.

13. A computer program product comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the signal phase coherence method as described in any one of claims 10 to 11.

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