Heterogeneous mixed precision data processing method, system, device and storage medium

Abstract

The application provides a heterogeneous mixed-precision data processing method, system, device and storage medium. The method comprises the following steps: generating heterogeneous task description information; configuring precision conversion parameters of a direct data channel based on the heterogeneous task description information, and establishing address alias mapping between an acceleration processing unit and a vector execution unit; transmitting, through the address alias mapping, to-be-processed data in the vector execution unit to the acceleration processing unit for calculation and processing via the direct data channel; and performing, in the process of transmitting the to-be-processed data via the direct data channel, stream online precision conversion on the to-be-processed data according to the precision conversion parameters. The technical scheme can improve the data collaborative processing efficiency of different processors.

Description

Technical Field

[0001] This application relates to the fields of data processing and computer technology and data processing technology, and in particular to a heterogeneous mixed-precision data processing method, system, device and storage medium. Background Technology

[0002] In related technologies, under heterogeneous system-on-chip architectures, the differences between general-purpose processor vector execution units and dedicated acceleration processing units in execution models and data precision lead to the following problems: They lack a hardware pass-through path, requiring data to be moved through multiple stages, resulting in memory access latency and the memory wall effect; data precision and layout incompatibility necessitates offline conversion by the general-purpose processor, wasting resources and increasing power consumption; the acceleration unit cannot parse the semantics of vector unit masks, leading to additional latency or computational redundancy; and the lack of a unified collaborative mapping mechanism results in high context switching overhead. These problems lead to poor interaction determinism, energy efficiency imbalance, storage and bandwidth redundancy, and wasted computational power. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] In a first aspect, this application proposes a heterogeneous hybrid precision data processing method, the method comprising: generating heterogeneous task description information, wherein the heterogeneous task description information includes at least one or more of the following fields: vector register index field, vector length and mask pointer field, precision and quantization configuration field, data layout and step description field, and task control and synchronization field; configuring precision conversion parameters for a pass-through data path based on the heterogeneous task description information, and establishing an address alias mapping between an accelerated processing unit and a vector execution unit; transmitting the data to be processed in the vector execution unit directly to the accelerated processing unit for computation processing via the pass-through data path through the address alias mapping; wherein, during the transmission of the data to be processed via the pass-through data path, the data to be processed has undergone streaming online precision conversion according to the precision conversion parameters.

[0005] In one implementation, the method further includes: configuring mask parsing logic based on the heterogeneous task description information to generate a mask signal corresponding to the data to be processed; controlling the enable state of precision conversion in the pass-through data path based on the mask signal; and controlling the computation enable state of the accelerated processing unit for the data to be processed based on the mask signal.

[0006] In one optional implementation, controlling the enable state of precision conversion in the pass-through data path based on the mask signal, and controlling the computation enable state of the acceleration processing unit for the data to be processed based on the mask signal, includes: when the mask signal indicates that the corresponding data element in the data to be processed is invalid, the corresponding data element in the pass-through data path performs hardware in-place zeroing or physical-level skip precision conversion, and the acceleration processing unit performs clock gating or computation skipping operation on the corresponding computation channel.

[0007] In one implementation, performing streaming online precision conversion on the data to be processed includes: during the transmission of the data to be processed via a pass-through data path, performing quantization mapping from high-precision representation to low-bit-width integer or fixed-point representation on the data to be processed according to the precision conversion parameters, and selectively performing truncation, saturation, or overflow processing strategies.

[0008] In one implementation, the heterogeneous task description information supports caching or prefetching mechanisms.

[0009] Secondly, this application proposes a heterogeneous hybrid precision data processing system, the system comprising: a vector execution unit for generating heterogeneous task description information; a hardware context cooperative mapping module for configuring precision conversion parameters of a pass-through data path based on the heterogeneous task description information; a pass-through data path for performing streaming online precision conversion on data under the control of the precision conversion parameters; and an accelerated processing unit for establishing an address alias mapping with the vector execution unit, and receiving the data to be processed after precision conversion by the pass-through data path based on the address alias mapping for performing computational processing.

[0010] In one implementation, the system further includes a mask parsing unit for generating a mask signal, controlling the enable state of precision conversion in the pass-through data path based on the mask signal, and controlling the computation enable state of the acceleration processing unit for the data to be processed based on the mask signal.

[0011] In one optional implementation, the mask parsing unit is specifically used to: control the enable state of precision conversion in the pass-through data path based on the mask signal, and control the computation enable state of the acceleration processing unit for the data to be processed based on the mask signal, including: when the mask signal indicates that the corresponding data element in the data to be processed is invalid, the corresponding data element in the pass-through data path performs hardware in-place zeroing or physical-level skip precision conversion, and the acceleration processing unit performs clock gating or computation skipping operation on the corresponding computation channel.

[0012] In one implementation, the pass-through data path is specifically used to: during the transmission of the data to be processed via the pass-through data path, perform quantization mapping from high-precision representation to low-bit-width integer or fixed-point representation on the data to be processed according to the precision conversion parameters, and selectively execute truncation, saturation or overflow processing strategies.

[0013] In one implementation, the heterogeneous task description information supports caching or prefetching mechanisms.

[0014] Thirdly, this application proposes an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the heterogeneous mixed-precision data processing method as described in the first aspect.

[0015] Fourthly, this application proposes a storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the method described in the first aspect.

[0016] Fifthly, this application proposes a program product comprising at least one of a program and instructions, wherein when the program or instructions are executed by an electronic device, they implement the steps of the method described in the first aspect.

[0017] The heterogeneous mixed-precision data processing method, system, device, and storage medium provided in this application enable a vector execution unit to generate heterogeneous task description information. This information is then sent to a hardware context co-mapping module, which configures the pass-through data path and the accelerated processing unit based on the task description information. This establishes an address alias mapping between the vector execution unit and the accelerated processing unit. The vector execution unit can then transmit the precision-converted data to be processed to the accelerated processing unit via the pass-through data path based on the address alias mapping. The accelerated processing unit can then obtain the data to be processed based on the address alias mapping and the pass-through data path, and acquire the corresponding mask information for processing. This improves the efficiency of data co-processing between different processors.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This is a flowchart illustrating a heterogeneous hybrid precision data processing method provided in an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the hardware architecture of a heterogeneous hybrid precision data processing system provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of a heterogeneous hybrid precision data processing flow provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of a heterogeneous hybrid precision data processing interaction process provided in an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0025] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0026] The heterogeneous hybrid precision data processing method and system of this application are described below with reference to the accompanying drawings.

[0027] Figure 1 This is a flowchart illustrating a heterogeneous hybrid precision data processing method provided in an embodiment of this application. Figure 1 As shown, the method may include, but is not limited to, the following steps:

[0028] S101: Generate heterogeneous task description information.

[0029] In the embodiments of this application, the heterogeneous task description information includes at least one or more of the following fields: vector register index field, vector length and mask pointer field, precision and quantization configuration field, data layout and step description field, and task control and synchronization field.

[0030] It should be noted that the vector register index field indicates the starting number of the vector register containing the data participating in the current heterogeneous task, as well as the register span information. Furthermore, this field may also contain register group identifiers to support concurrent mapping and combined access of multiple vector registers.

[0031] For example, the vector length and mask pointer fields may include information describing the number of elements involved in the valid computation of the current vector operation and the storage location of the corresponding vector mask. This field includes at least a length parameter indicating the valid vector length and a mask pointer parameter pointing to a mask register or mask storage region.

[0032] It should be noted that the Precision and Quantization Configuration field describes the data precision type and corresponding quantization conversion parameters used in heterogeneous tasks. This field includes at least the source data precision identifier, the target data precision identifier, and the quantization mapping parameters.

[0033] Among them, the source data precision identifier is used to identify the data precision corresponding to the vector execution unit, and the target data precision identifier is used to identify the data precision of the acceleration processing unit.

[0034] The quantization mapping parameters include the fixed-point representation of the quantization scaling factor and the selection of overflow, truncation, or saturation processing strategies.

[0035] It should be noted that the data layout and step description fields are used to describe how the vector data is arranged in the storage space and the memory access step relationship between adjacent vector elements. This field includes at least layout parameters indicating the data layout mode and step parameters indicating the memory access step size.

[0036] For example, the data layout and step description field may include a data transformation mode identifier to indicate whether bypass, saturation, or overflow handling strategies are enabled during vector data loading or write-back, and the transformation mode is automatically applied by the hardware execution path during memory access or computation phases.

[0037] It should be noted that the Task Control and Synchronization field is used to describe the control status and synchronization information of heterogeneous tasks. This field includes at least a start control bit, an execution status bit, and an interrupt or synchronization enable bit.

[0038] In one implementation, heterogeneous task description information supports caching or prefetching mechanisms to prepare configuration parameters for subsequent tasks in parallel during the execution of the current task, thereby achieving a pipelined overlap between task configuration and computation execution.

[0039] S102: Based on heterogeneous task description information, configure the precision conversion parameters of the pass-through data path, and establish an address alias mapping between the acceleration processing unit and the vector execution unit.

[0040] For example, the hardware context collaborative mapping module generates and sends first configuration information to the pass-through data path based on heterogeneous task description information to configure the data precision conversion engine in the pass-through data path. This engine performs data precision conversion on the data to be processed when the vector execution unit transmits the data to be processed to the acceleration processing unit through the pass-through data path. The hardware context collaborative mapping module can also generate and send second configuration information to the acceleration processing unit based on heterogeneous task description information. This allows the acceleration processing unit to establish an address alias mapping with the vector execution unit based on the second configuration information. As a result, the vector execution unit can send the data to be processed to the acceleration processing unit through the pass-through data path based on the address alias mapping.

[0041] For example, the first configuration information may include information related to the precision and quantization configuration fields, such as the data precision corresponding to the vector execution unit and the data precision corresponding to the acceleration processing unit, so that the data direct connection path can convert the data precision of the data to be processed sent by the vector execution unit into the data precision adapted to the acceleration processing unit.

[0042] For example, the second configuration information may include information related to the vector register index field, vector length and mask pointer field, data layout and step description field, thereby accelerating the processing unit to establish an address alias mapping between itself and the vector execution unit based on the second configuration information.

[0043] S103: Through address alias mapping, the data to be processed in the vector execution unit is directly transmitted to the acceleration processing unit for computation processing via the pass-through data path. During the transmission of the data to be processed via the pass-through data path, the data to be processed has already undergone streaming online precision conversion according to the precision conversion parameters.

[0044] As an example, the vector execution unit performs a write operation based on the local alias address mapped by the address alias to write the data to be processed to the local alias address. The data to be processed enters the pass-through data path, and after the data precision conversion engine in the pass-through data path performs data precision conversion, it is transmitted to the acceleration processing unit. The acceleration processing unit gates its own computing engine based on the mask of the data to be processed, so that the acceleration processing unit performs computation processing on the data to be processed.

[0045] As another example, the accelerated processing unit can access its own local alias address mapped to the target data of the accelerated processing unit to trigger a data forwarding request. Thus, the vector execution unit can pass the corresponding data to be processed into the pass-through data path. The pass-through data path performs precision conversion on the data to be processed and then transmits it to the accelerated processing unit so that the accelerated processing unit can perform computational processing on the data to be processed.

[0046] In one implementation, the above-mentioned online precision conversion of the data to be processed includes: during the transmission of the data to be processed via a pass-through data path, performing a quantization mapping from a high-precision representation to a low-bit-width integer or fixed-point representation of the data to be processed according to the precision conversion parameters, and selectively performing truncation, saturation, or overflow processing strategies.

[0047] For example, during the transmission of data to be processed via a pass-through data path, the pass-through data path first parses the precision and quantization configuration fields to determine the target low bit width and quantization mapping rules (e.g., scaling factor, zero offset, integer / fixed-point conversion mode). Then, based on the above information, the high-precision representation (e.g., floating-point, high-bit-width fixed-point) of the data to be processed is converted into a low-bit-width integer or fixed-point representation according to the mapping relationship. If the data exceeds the representation range of the target bit width during the conversion, a truncation (e.g., directly discarding low / high bits), saturation (e.g., clamping to the extreme value of the target bit width), or overflow (e.g., looping according to the overflow rule) processing strategy is selected according to the configuration. Finally, the low-bit-width data after quantization and strategy processing is output, completing the real-time data precision conversion during the transmission process.

[0048] By implementing the embodiments of this application, the vector execution unit can generate heterogeneous task description information and send it to the hardware context cooperative mapping module. The hardware context cooperative mapping module then configures the pass-through data path and the accelerated processing unit based on the task description information to establish an address alias mapping between the vector execution unit and the accelerated processing unit. The vector execution unit can then transmit the precision-converted data to be processed to the accelerated processing unit through the data pass-through path based on the address alias mapping. The accelerated processing unit can then obtain the data to be processed based on the address alias mapping and the pass-through data path, and obtain the corresponding mask information for processing. By introducing a cooperative mapping mechanism based on heterogeneous task descriptors, a physical-level pass-through data path, and a hardware-based precision and mask cooperative processing mechanism, low-copy, low-latency, and highly deterministic data interaction between heterogeneous processing units can be achieved, thereby significantly improving the system's energy efficiency and overall throughput performance while ensuring functional correctness.

[0049] In some embodiments, the above method may further include: configuring mask parsing logic based on heterogeneous task description information to generate a mask signal corresponding to the data to be processed; controlling the enable state of precision conversion in the pass-through data path based on the mask signal; and controlling the computation enable state of the accelerated processing unit for the data to be processed based on the mask signal.

[0050] For example, the vector execution unit can synchronize the mask vector corresponding to the currently transmitted data to the mask parsing unit. The mask parsing unit generates two mask signals in real time: one to control the precision conversion switch on the transmission path, and the other to configure the gating signal of the acceleration processing unit's arithmetic array and the skip offset of the address generation unit. Thus, the data pass-through path only performs data precision conversion on the data corresponding to the valid bits of the mask, performing hardware zeroing or skipping processing, achieving power consumption suppression during transmission. The acceleration processing unit can implement element-level clock gating based on the mask signal. For channels with a mask of 0, the hardware stops logic flipping, thereby skipping invalid operations without changing the algorithm logic, maximizing energy efficiency.

[0051] In one alternative implementation, the above-mentioned enabling state of precision conversion in the pass-through data path based on the mask signal, and the enabling state of computation of the data to be processed by the acceleration processing unit based on the mask signal, include: when the mask signal indicates that the corresponding data element in the data to be processed is invalid, the corresponding data element in the pass-through data path performs hardware in-place zeroing or physical-level skip precision conversion, and the acceleration processing unit performs clock gating or computation skipping operation on the corresponding computation channel.

[0052] For example, when the mask signal received by the pass-through data path is 0, a hardware in-place zeroing or physical-level skip precision conversion is performed on the data element.

[0053] For example, when the mask signal received by the acceleration processing unit is 0, clock gating or calculation skipping operation is performed on the corresponding computing channel.

[0054] Please see Figure 2 , Figure 2 This is a schematic diagram of the hardware architecture of a heterogeneous hybrid precision data processing system provided in an embodiment of this application. Figure 2 As shown, the architecture may include a VEU (Vector Execution Unit), an NPU (Neural Processing Unit) (i.e., the aforementioned acceleration processing unit), a datafast-path, an in-line precision mapping engine, a maskpass-through logic, and a heterogeneous context mapper (HCM). The VEU and NPU each have independent register files and local SRAMs, and they achieve hardware pass-through access through a hardware-level pass-through link, reducing dependence on the system bus.

[0055] The pass-through data path serves as a dedicated physical link between the VEU vector register file and the NPU local buffer. It uses address aliasing to map the physical indices of the VEU's internal registers to the NPU's logical address space. The NPU's DMA unit or read interface can directly retrieve operands from the VEU registers through this link, achieving "zero / low copy" data throughput. The path is configured with a hardware mutex or double-buffered switching mechanism to ensure data consistency between VEU write-back and NPU read, avoiding read-write conflicts.

[0056] The streaming precision mapping engine is seamlessly integrated into the pipeline stage of the pass-through data path, enabling quantization or dequantization conversion between FP32, FP16, and low-bit-width integer precision in a pipelined manner. This engine parses the vector mask from the VEU in real time using sideband signals. The conversion circuitry (including shifters and saturation cutoff logic) only operates when mask bits are valid; for invalid mask bits, the engine automatically performs forced-zeroing of the output. This "transfer-as-conversion" mode reduces storage footprint while eliminating the heavy format preprocessing burden on the VEU side.

[0057] The VEU's vector mask register (e.g., the v0 register) is transparently transmitted in real-time to the NPU's instruction scheduler and arithmetic array via a dedicated physical connection. During NPU computation cycles, the mask signal is directly connected to the clock gating pin of the multiply-accumulate (MAC) unit. When an invalid bit in the mask is parsed, the hardware automatically disables the toggling activity of the corresponding arithmetic unit. Simultaneously, the address generation unit (AGU) performs address skipping based on the mask state, preventing invalid data from consuming memory access bandwidth.

[0058] The hardware context coordination module manages the collaboration state between the VEU and NPU through a heterogeneous task descriptor. This descriptor encapsulates the start vector register number, the current mask vector length, the precision scaling factor, and data layout information. The NPU achieves "snapshot-level" inheritance of the VEU execution environment by reading this descriptor. During task switching, only the descriptor register (CSR) pointer needs to be updated, without having to move a large register context, thus keeping the switching latency of heterogeneous units within a few clock cycles.

[0059] Please see Figure 3 and Figure 4 , Figure 3This is a schematic diagram of a heterogeneous hybrid precision data processing flow provided in an embodiment of this application. Figure 4 This is a schematic diagram of a heterogeneous hybrid precision data processing interaction flow provided in an embodiment of this application. For example... Figure 3 and Figure 4 As shown, the interaction process may include the following steps:

[0060] S301: Cooperative task generation and descriptor initialization.

[0061] When executing vector computation streams, the VEU identifies specific heterogeneous cooperative instructions (e.g., cooperative trigger instructions from vectors to acceleration units). The cooperative instruction decoder constructs or selects the corresponding heterogeneous task descriptor in memory or registers based on the current task requirements, defining the precision mapping rules and mask application scope for this cooperative operation.

[0062] S302: Descriptor activation and hardware context synchronization.

[0063] The VEU writes the descriptor pointer to a dedicated control register. The hardware context mapping module responds immediately, parsing the descriptor into configuration information and distributing it to the precision mapping engine, mask parsing logic, and NPU scheduler. This process enables rapid hardware-level pass-through of the execution environment from the VEU to the NPU.

[0064] S303: Physical level pass-through path establishment.

[0065] Based on the register index in the descriptor, the NPU establishes an address alias mapping with the VEU's vector register file through a pass-through data path. This allows the accelerated processing unit to access the vector register data of the vector execution unit in a local address space manner. At this point, the NPU gains logical access to the valid data in the vector registers through the address alias mapping mechanism.

[0066] S304: Mask semantic passthrough and sparse strategy configuration.

[0067] The current mask vector of the VEU is synchronized to the mask parsing logic. The parsing logic generates two control signals in real time: one to control the precision conversion switch on the transmission path, and the other to configure the gating signal of the NPU computing array and the skip offset of the address generation unit.

[0068] S305: Streaming online quantization conversion and zero-copy transmission.

[0069] Data flows to the NPU via a pass-through path. During data transmission, the streaming precision mapping engine performs precision conversion according to the configuration (e.g., FP32 to INT8). Quantization logic is performed only on the elements corresponding to the valid bits of the mask, and hardware zeroing or skipping is performed to suppress power consumption during the transmission phase.

[0070] S306: Mask-aware parallel computation execution.

[0071] The NPU receives the converted data and sends it to the processing array. During execution, the array implements element-level clock gating based on the mask signal. For channels with a mask of 0, the hardware stops logic flipping, thus skipping invalid operations without changing the algorithm logic and maximizing energy efficiency.

[0072] S307: Task completion feedback and status synchronization.

[0073] Once the NPU completes the current heterogeneous task, it sends a hardware completion signal to the Hardware Context Coordination Mapping (HCM) via a hardware connection. In response to this signal, the HCM automatically updates the completion status bit (DoneBit) in the heterogeneous task descriptor. According to system presets, the HCM can also selectively send a hardware interrupt signal to the general-purpose processor to notify the software layer that the task has ended. This process allows the VEU to seamlessly enter the next task loop and allows the HCM to preload the descriptor of the next heterogeneous task in parallel during the execution of the current task, thereby achieving pipelined overlap between heterogeneous task scheduling and computation execution.

[0074] It should be noted that the foregoing explanation of the heterogeneous mixed precision data processing method embodiment also applies to the heterogeneous mixed precision data processing system of this embodiment, and will not be repeated here.

[0075] To implement the above embodiments, this application also proposes an electronic device. Please see [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the structure of the electronic device provided in an embodiment of this application. For example... Figure 5 As shown, the electronic device 500 includes: a processor 501 and a memory 502 communicatively connected to the processor 501; the memory 502 stores computer-executable instructions; the processor 501 executes the computer-executable instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0076] To implement the above embodiments, this application also proposes a storage medium storing instructions that, when executed on an electronic device, cause the electronic device to perform the methods provided in the foregoing embodiments.

[0077] To implement the above embodiments, this application also proposes a program product, including at least one of a program and instructions, wherein when the program and instructions are executed by an electronic device, they implement the steps of the method provided in the foregoing embodiments.

[0078] It should be noted that the acquisition, transmission, storage, use, and processing of data in this application comply with the relevant provisions of national laws and regulations and do not violate public order and good morals.

[0079] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0080] It is worth noting that in the embodiments of this application, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of this application. However, they do not mean that the applicant has used or necessarily used the solution.

[0081] In the description of this application, unless otherwise stated, " / " means "or", for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone.

[0082] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0084] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0085] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0086] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0087] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware, and the program can be stored in a computer-readable storage medium. When executed, the program includes one or a combination of the steps of the method embodiments.

[0088] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0089] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A heterogeneous hybrid precision data processing method, characterized in that, The method includes: Generate heterogeneous task description information, which includes at least one or more of the following fields: vector register index field, vector length and mask pointer field, precision and quantization configuration field, data layout and step description field, and task control and synchronization field. Based on the heterogeneous task description information, the precision conversion parameters of the pass-through data path are configured, and an address alias mapping is established between the acceleration processing unit and the vector execution unit. The address alias mapping is used to map the physical index of the internal register of the vector execution unit to the logical address space of the acceleration processing unit, so that the acceleration processing unit can access the register data of the vector execution unit in the manner of accessing the local address space. Through the address alias mapping, the data to be processed in the vector execution unit is directly transmitted to the acceleration processing unit for computation processing via the pass-through data path; wherein, during the transmission of the data to be processed via the pass-through data path, the data to be processed has already undergone streaming online precision conversion according to the precision conversion parameters; The process of performing streaming online precision conversion on the data to be processed includes: During the transmission of the data to be processed via the direct data path, the data to be processed is subjected to quantization mapping from high-precision representation to low-bit-width integer or fixed-point representation according to the precision conversion parameters, and truncation, saturation or overflow processing strategies are executed.

2. The method according to claim 1, characterized in that, The method further includes: Configure mask parsing logic based on the heterogeneous task description information to generate a mask signal corresponding to the data to be processed; The mask signal controls the enable state of precision conversion in the pass-through data path, and the mask signal also controls the enable state of computation of the data to be processed by the acceleration processing unit.

3. The method according to claim 2, characterized in that, The method of controlling the enable state of precision conversion in the pass-through data path based on the mask signal, and controlling the computation enable state of the accelerated processing unit for the data to be processed based on the mask signal, includes: When the mask signal indicates that the corresponding data element in the data to be processed is invalid, the corresponding data element in the pass-through data path performs hardware in-place zeroing or physical-level skip precision conversion, and the acceleration processing unit performs clock gating or calculation skip operation on the corresponding calculation channel.

4. The method according to claim 1, characterized in that, The heterogeneous task description information supports caching or prefetching mechanisms.

5. A heterogeneous hybrid precision data processing system, characterized in that, include: A vector execution unit is used to generate heterogeneous task description information, which includes at least one or more of the following fields: vector register index field, vector length and mask pointer field, precision and quantization configuration field, data layout and step description field, and task control and synchronization field. The hardware context collaborative mapping module is used to configure the precision conversion parameters of the pass-through data path based on the heterogeneous task description information. A direct data path, used to perform streaming online precision conversion on the data to be processed under the control of the precision conversion parameters, including: During the transmission of the data to be processed via the direct data path, according to the precision conversion parameters, the data to be processed is subjected to quantization mapping from high precision representation to low bit width integer or fixed point representation, and truncation, saturation or overflow processing strategies are executed. An accelerated processing unit is configured to establish an address alias mapping with the vector execution unit and receive data to be processed after precision conversion by the pass-through data path based on the address alias mapping to perform computational processing. The address alias mapping is used to map the physical index of the internal register of the vector execution unit to the logical address space of the accelerated processing unit, so that the accelerated processing unit can access the register data of the vector execution unit in a manner that accesses the local address space.

6. The system according to claim 5, characterized in that, The system also includes a mask parsing unit, which generates a mask signal and controls the enable state of precision conversion in the pass-through data path based on the mask signal, and controls the enable state of the acceleration processing unit for calculating the data to be processed based on the mask signal.

7. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 4.

8. A storage medium storing instructions, characterized in that, When the instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method of any one of claims 1 to 4.

9. A program product comprising at least one of a program and instructions, characterized in that, When at least one of the program or instructions is executed by an electronic device, it implements the steps of the method according to any one of claims 1 to 4.

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